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Introduce a struct dram_controller to be able to abstract these differences later. For now only add a few members, more will come in later patches. Signed-off-by: Sascha Hauer --- drivers/ddr/imx/ddrphy_train.c | 8 +++----- drivers/ddr/imx/imx8m_ddr_init.c | 16 ++++++++-------- include/soc/imx8m/ddr.h | 32 +++++++++++++++++++++++++------- 3 files changed, 36 insertions(+), 20 deletions(-) diff --git a/drivers/ddr/imx/ddrphy_train.c b/drivers/ddr/imx/ddrphy_train.c index 6a98fa0545..1683ffd9a8 100644 --- a/drivers/ddr/imx/ddrphy_train.c +++ b/drivers/ddr/imx/ddrphy_train.c @@ -93,10 +93,8 @@ void ddr_load_train_code(enum dram_type dram_type, enum fw_type fw_type) DDRC_PHY_DMEM, dmem, dsize); } -int ddr_cfg_phy(struct dram_timing_info *dram_timing, unsigned type) +int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *dram_timing) { - enum ddrc_type ddrc_type = get_ddrc_type(type); - enum dram_type dram_type = get_dram_type(type); struct dram_cfg_param *dram_cfg; struct dram_fsp_msg *fsp_msg; unsigned int num; @@ -118,11 +116,11 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing, unsigned type) for (i = 0; i < dram_timing->fsp_msg_num; i++) { pr_debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); /* set dram PHY input clocks to desired frequency */ - ddrphy_init_set_dfi_clk(fsp_msg->drate, ddrc_type); + ddrphy_init_set_dfi_clk(fsp_msg->drate, dram->ddrc_type); /* load the dram training firmware image */ dwc_ddrphy_apb_wr(0xd0000, 0x0); - ddr_load_train_code(dram_type, fsp_msg->fw_type); + ddr_load_train_code(dram->dram_type, fsp_msg->fw_type); /* load the frequency set point message block parameter */ dram_cfg = fsp_msg->fsp_cfg; diff --git a/drivers/ddr/imx/imx8m_ddr_init.c b/drivers/ddr/imx/imx8m_ddr_init.c index 9a86280d9c..8acacfac35 100644 --- a/drivers/ddr/imx/imx8m_ddr_init.c +++ b/drivers/ddr/imx/imx8m_ddr_init.c @@ -15,6 +15,8 @@ bool imx8m_ddr_old_spreadsheet = true; +struct dram_controller imx8m_dram_controller; + static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) { int i = 0; @@ -49,18 +51,16 @@ static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) */ #define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 -int imx8m_ddr_init(struct dram_timing_info *dram_timing, - unsigned type) +int imx8m_ddr_init(struct dram_controller *dram, struct dram_timing_info *dram_timing) { unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; unsigned int tmp, initial_drate, target_freq; - enum ddrc_type ddrc_type = get_ddrc_type(type); int ret; pr_debug("start DRAM init\n"); /* Step1: Follow the power up procedure */ - switch (ddrc_type) { + switch (dram->ddrc_type) { case DDRC_TYPE_MQ: reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f); reg32_write(src_ddrc_rcr, 0x8f00000f); @@ -82,7 +82,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, initial_drate = dram_timing->fsp_msg[0].drate; /* default to the frequency point 0 clock */ - ddrphy_init_set_dfi_clk(initial_drate, ddrc_type); + ddrphy_init_set_dfi_clk(initial_drate, dram->ddrc_type); /* D-aasert the presetn */ reg32_write(src_ddrc_rcr, 0x8F000006); @@ -112,7 +112,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, * might not have been called */ tmp = reg32_read(DDRC_MSTR(0)); - if (tmp & (0x1 << 5) && ddrc_type != DDRC_TYPE_MN) + if (tmp & (0x1 << 5) && dram->ddrc_type != DDRC_TYPE_MN) reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */ @@ -139,7 +139,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, */ pr_debug("ddrphy config start\n"); - ret = ddr_cfg_phy(dram_timing, type); + ret = ddr_cfg_phy(dram, dram_timing); if (ret) return ret; @@ -159,7 +159,7 @@ int imx8m_ddr_init(struct dram_timing_info *dram_timing, reg32_write(DDRC_SWCTL(0), 0x00000000); /* Apply rank-to-rank workaround */ - update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1, ddrc_type); + update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1, dram->ddrc_type); /* Step16: Set DFIMISC.dfi_init_start to 1 */ setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index e268892957..18d7c96193 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -384,6 +384,11 @@ struct dram_timing_info { unsigned int fsp_table[4]; }; +struct dram_controller { + enum ddrc_type ddrc_type; + enum dram_type dram_type; +}; + extern struct dram_timing_info dram_timing; void ddr_get_firmware_lpddr4(void); @@ -397,42 +402,55 @@ static inline void ddr_get_firmware(enum dram_type dram_type) ddr_get_firmware_ddr(); } -int imx8m_ddr_init(struct dram_timing_info *dram_timing, - unsigned type); +int imx8m_ddr_init(struct dram_controller *dram, struct dram_timing_info *dram_timing); + +extern struct dram_controller imx8m_dram_controller; static inline int imx8mm_ddr_init(struct dram_timing_info *dram_timing, enum dram_type dram_type) { + imx8m_dram_controller.ddrc_type = DDRC_TYPE_MM; + imx8m_dram_controller.dram_type = dram_type; + ddr_get_firmware(dram_type); - return imx8m_ddr_init(dram_timing, DDRC_TYPE_MM | dram_type); + return imx8m_ddr_init(&imx8m_dram_controller, dram_timing); } static inline int imx8mn_ddr_init(struct dram_timing_info *dram_timing, enum dram_type dram_type) { + imx8m_dram_controller.ddrc_type = DDRC_TYPE_MN; + imx8m_dram_controller.dram_type = dram_type; + ddr_get_firmware(dram_type); - return imx8m_ddr_init(dram_timing, DDRC_TYPE_MN | dram_type); + return imx8m_ddr_init(&imx8m_dram_controller, dram_timing); } static inline int imx8mq_ddr_init(struct dram_timing_info *dram_timing, enum dram_type dram_type) { + imx8m_dram_controller.ddrc_type = DDRC_TYPE_MQ; + imx8m_dram_controller.dram_type = dram_type; + ddr_get_firmware(dram_type); - return imx8m_ddr_init(dram_timing, DDRC_TYPE_MQ | dram_type); + return imx8m_ddr_init(&imx8m_dram_controller, dram_timing); } static inline int imx8mp_ddr_init(struct dram_timing_info *dram_timing, enum dram_type dram_type) { + imx8m_dram_controller.ddrc_type = DDRC_TYPE_MP; + imx8m_dram_controller.dram_type = dram_type; + ddr_get_firmware(dram_type); - return imx8m_ddr_init(dram_timing, DDRC_TYPE_MP | dram_type); + return imx8m_ddr_init(&imx8m_dram_controller, dram_timing); } -int ddr_cfg_phy(struct dram_timing_info *timing_info, unsigned type); +int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *timing_info); void load_lpddr4_phy_pie(void); void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); void dram_config_save(struct dram_timing_info *info, unsigned long base); -- 2.39.2