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Also remove some unused defines. Signed-off-by: Sascha Hauer --- drivers/ddr/imx/helper.c | 8 -------- drivers/ddr/imx/imx8m_ddr_init.c | 2 +- include/soc/imx8m/ddr.h | 11 +++-------- 3 files changed, 4 insertions(+), 17 deletions(-) diff --git a/drivers/ddr/imx/helper.c b/drivers/ddr/imx/helper.c index 98e4084958..81c3ed7f30 100644 --- a/drivers/ddr/imx/helper.c +++ b/drivers/ddr/imx/helper.c @@ -10,14 +10,6 @@ #include #include -#define IMEM_LEN 32768 /* byte */ -#define DMEM_LEN 16384 /* byte */ -#define IMEM_2D_OFFSET 49152 - -#define IMEM_OFFSET_ADDR 0x00050000 -#define DMEM_OFFSET_ADDR 0x00054000 -#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) - void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, unsigned int num) { diff --git a/drivers/ddr/imx/imx8m_ddr_init.c b/drivers/ddr/imx/imx8m_ddr_init.c index 856e7ee4fe..f76aafe769 100644 --- a/drivers/ddr/imx/imx8m_ddr_init.c +++ b/drivers/ddr/imx/imx8m_ddr_init.c @@ -543,7 +543,7 @@ int imx8m_ddr_init(struct dram_controller *dram, struct dram_timing_info *dram_t */ tmp = reg32_read(DDRC_MSTR(0)); if (tmp & (0x1 << 5) && dram->ddrc_type != DDRC_TYPE_MN) - reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + reg32_write(MX8M_DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */ target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3; diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index ec82f3233a..9ff9c0a2da 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -8,11 +8,9 @@ #include #include +#include -#define DDRC_DDR_SS_GPR0 0x3d000000 -#define DDRC_IPS_BASE_ADDR_0 0x3f400000 -#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) -#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) MX8M_DDRC_PHY_BASE_ADDR #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) @@ -320,7 +318,7 @@ #define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) #define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) -#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000)) +#define DDRC_IPS_BASE_ADDR(X) MX8M_DDRC_IPS_BASE_ADDR(X) /* user data type */ enum fw_type { @@ -391,8 +389,6 @@ struct dram_controller { void (*set_dfi_clk)(struct dram_controller *dram, unsigned int drate_mhz); }; -extern struct dram_timing_info dram_timing; - void ddr_get_firmware_lpddr4(void); void ddr_get_firmware_ddr(void); @@ -453,7 +449,6 @@ static inline int imx8mp_ddr_init(struct dram_timing_info *dram_timing, } int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *timing_info); -void load_lpddr4_phy_pie(void); void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); void dram_config_save(struct dram_timing_info *info, unsigned long base); -- 2.39.2