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Signed-off-by: Sascha Hauer --- drivers/ddr/imx/ddrphy_train.c | 24 ++++++++++++------------ drivers/ddr/imx/helper.c | 12 ++++++------ drivers/ddr/imx/imx8m_ddr_init.c | 13 ++++++------- include/soc/imx8m/ddr.h | 22 +++++++++++++++++----- 4 files changed, 41 insertions(+), 30 deletions(-) diff --git a/drivers/ddr/imx/ddrphy_train.c b/drivers/ddr/imx/ddrphy_train.c index b44f5ef9b4..af4d710dc0 100644 --- a/drivers/ddr/imx/ddrphy_train.c +++ b/drivers/ddr/imx/ddrphy_train.c @@ -107,7 +107,7 @@ int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *dram_timi num = dram_timing->ddrphy_cfg_num; for (i = 0; i < num; i++) { /* config phy reg */ - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dwc_ddrphy_apb_wr(dram, dram_cfg->reg, dram_cfg->val); dram_cfg++; } @@ -119,14 +119,14 @@ int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *dram_timi dram->set_dfi_clk(dram, fsp_msg->drate); /* load the dram training firmware image */ - dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x0); ddr_load_train_code(dram->dram_type, fsp_msg->fw_type); /* load the frequency set point message block parameter */ dram_cfg = fsp_msg->fsp_cfg; num = fsp_msg->fsp_cfg_num; for (j = 0; j < num; j++) { - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dwc_ddrphy_apb_wr(dram, dram_cfg->reg, dram_cfg->val); dram_cfg++; } @@ -140,10 +140,10 @@ int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *dram_timi * 4. read the message block result. * ------------------------------------------------------------- */ - dwc_ddrphy_apb_wr(0xd0000, 0x1); - dwc_ddrphy_apb_wr(0xd0099, 0x9); - dwc_ddrphy_apb_wr(0xd0099, 0x1); - dwc_ddrphy_apb_wr(0xd0099, 0x0); + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x1); + dwc_ddrphy_apb_wr(dram, 0xd0099, 0x9); + dwc_ddrphy_apb_wr(dram, 0xd0099, 0x1); + dwc_ddrphy_apb_wr(dram, 0xd0099, 0x0); /* Wait for the training firmware to complete */ ret = wait_ddrphy_training_complete(); @@ -151,17 +151,17 @@ int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *dram_timi return ret; /* Halt the microcontroller. */ - dwc_ddrphy_apb_wr(0xd0099, 0x1); + dwc_ddrphy_apb_wr(dram, 0xd0099, 0x1); /* Read the Message Block results */ - dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x0); ddrphy_init_read_msg_block(fsp_msg->fw_type); if (fsp_msg->fw_type != FW_2D_IMAGE) dram->get_trained_CDD(dram, i); - dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x1); fsp_msg++; } @@ -170,12 +170,12 @@ int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *dram_timi dram_cfg = dram_timing->ddrphy_pie; num = dram_timing->ddrphy_pie_num; for (i = 0; i < num; i++) { - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dwc_ddrphy_apb_wr(dram, dram_cfg->reg, dram_cfg->val); dram_cfg++; } /* save the ddr PHY trained CSR in memory for low power use */ - ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); + ddrphy_trained_csr_save(dram, ddrphy_trained_csr, ddrphy_trained_csr_num); return 0; } diff --git a/drivers/ddr/imx/helper.c b/drivers/ddr/imx/helper.c index 81c3ed7f30..0bd8d2688a 100644 --- a/drivers/ddr/imx/helper.c +++ b/drivers/ddr/imx/helper.c @@ -10,21 +10,21 @@ #include #include -void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, +void ddrphy_trained_csr_save(struct dram_controller *dram, struct dram_cfg_param *ddrphy_csr, unsigned int num) { int i = 0; /* enable the ddrphy apb */ - dwc_ddrphy_apb_wr(0xd0000, 0x0); - dwc_ddrphy_apb_wr(0xc0080, 0x3); + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x0); + dwc_ddrphy_apb_wr(dram, 0xc0080, 0x3); for (i = 0; i < num; i++) { - ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); + ddrphy_csr->val = dwc_ddrphy_apb_rd(dram, ddrphy_csr->reg); ddrphy_csr++; } /* disable the ddrphy apb */ - dwc_ddrphy_apb_wr(0xc0080, 0x2); - dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(dram, 0xc0080, 0x2); + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x1); } void dram_config_save(struct dram_timing_info *timing_info, diff --git a/drivers/ddr/imx/imx8m_ddr_init.c b/drivers/ddr/imx/imx8m_ddr_init.c index f76aafe769..8d473a3e63 100644 --- a/drivers/ddr/imx/imx8m_ddr_init.c +++ b/drivers/ddr/imx/imx8m_ddr_init.c @@ -15,7 +15,9 @@ bool imx8m_ddr_old_spreadsheet = true; -struct dram_controller imx8m_dram_controller; +struct dram_controller imx8m_dram_controller = { + .phy_base = IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)), +}; static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) { @@ -71,15 +73,13 @@ static void get_trained_CDD(struct dram_controller *dram, u32 fsp) ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; if (ddr_type == 0x20) { for (i = 0; i < 6; i++) { - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + - (0x54013UL + i) * 4); + tmp = dwc_ddrphy_apb_rd(dram, 0x54013UL + i); cdd_cha[i * 2] = tmp & 0xff; cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; } for (i = 0; i < 7; i++) { - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + - (0x5402cUL + i) * 4); + tmp = dwc_ddrphy_apb_rd(dram, 0x5402cUL + i); if (i == 0) { cdd_cha[0] = (tmp >> 8) & 0xff; } else if (i == 6) { @@ -106,8 +106,7 @@ static void get_trained_CDD(struct dram_controller *dram, u32 fsp) unsigned int ddr4_cdd[64]; for( i = 0; i < 29; i++) { - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + - (0x54012UL + i) * 4); + tmp = dwc_ddrphy_apb_rd(dram, 0x54012UL + i); ddr4_cdd[i * 2] = tmp & 0xff; ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff; } diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index 9ff9c0a2da..bdf0f25727 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -385,6 +385,7 @@ struct dram_timing_info { struct dram_controller { enum ddrc_type ddrc_type; enum dram_type dram_type; + void __iomem *phy_base; void (*get_trained_CDD)(struct dram_controller *dram, u32 fsp); void (*set_dfi_clk)(struct dram_controller *dram, unsigned int drate_mhz); }; @@ -449,7 +450,8 @@ static inline int imx8mp_ddr_init(struct dram_timing_info *dram_timing, } int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *timing_info); -void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); +void ddrphy_trained_csr_save(struct dram_controller *dram, struct dram_cfg_param *param, + unsigned int num); void dram_config_save(struct dram_timing_info *info, unsigned long base); /* utils function for ddr phy training */ @@ -464,10 +466,20 @@ static inline void reg32setbit(unsigned long addr, u32 bit) setbits_le32(addr, (1 << bit)); } -#define dwc_ddrphy_apb_wr(addr, data) \ - reg32_write(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr), data) -#define dwc_ddrphy_apb_rd(addr) \ - reg32_read(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr)) +static inline void *dwc_ddrphy_apb_addr(struct dram_controller *dram, unsigned int addr) +{ + return dram->phy_base + addr * 4; +} + +static inline void dwc_ddrphy_apb_wr(struct dram_controller *dram, unsigned int addr, u32 data) +{ + reg32_write(dwc_ddrphy_apb_addr(dram, addr), data); +} + +static inline u32 dwc_ddrphy_apb_rd(struct dram_controller *dram, unsigned int addr) +{ + return reg32_read(dwc_ddrphy_apb_addr(dram, addr)); +} extern bool imx8m_ddr_old_spreadsheet; extern struct dram_cfg_param ddrphy_trained_csr[]; -- 2.39.2