[PATCH 2/3] mci: imx-esdhc: Layerscape: fix clock setup

[Sascha Hauer <s.hauer@pengutronix.de>]

Set the PCS bit in the ESDHCCTL register. With this Peripheral/2 clock
is used which is the clock we are actually calculating the dividers for.
As the input clock is only half of the expected clock we have to account
for this in set_sysctl().

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc.c | 8 ++++++--
 drivers/mci/imx-esdhc.h | 2 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 90a6c12439..92aea9ed9d 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -51,6 +51,9 @@ static void set_sysctl(struct mci_host *mci, u32 clock, bool ddr)
 	u32 clk;
 	unsigned long  cur_clock;
 
+	if (esdhc_is_layerscape(host))
+		sdhc_clk >>= 1;
+
 	/*
 	 * With eMMC and imx53 (sdhc_clk=200MHz) a pre_div of 1 results in
 	 *	pre_div=1,div=4 (=50MHz)
@@ -231,9 +234,10 @@ static int esdhc_init(struct mci_host *mci, struct device *dev)
 	/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
 	sdhci_write32(&host->sdhci, SDHCI_MMC_BOOT, 0);
 
-	/* Enable cache snooping */
 	if (esdhc_is_layerscape(host))
-		esdhc_setbits32(host, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP);
+		esdhc_setbits32(host, ESDHC_DMA_SYSCTL,
+				ESDHC_SYSCTL_DMA_SNOOP | /* Enable cache snooping */
+				ESDHC_SYSCTL_PERIPHERAL_CLK_SEL);
 
 	/* Set the initial clock speed */
 	set_sysctl(mci, 400000, false);
diff --git a/drivers/mci/imx-esdhc.h b/drivers/mci/imx-esdhc.h
index 6810039a96..047c32615d 100644
--- a/drivers/mci/imx-esdhc.h
+++ b/drivers/mci/imx-esdhc.h
@@ -60,7 +60,7 @@
 
 #define ESDHC_DMA_SYSCTL	0x40c /* Layerscape specific */
 #define ESDHC_SYSCTL_DMA_SNOOP 	BIT(6)
-
+#define ESDHC_SYSCTL_PERIPHERAL_CLK_SEL	BIT(19)
 
 /*
  * The CMDTYPE of the CMD register (offset 0xE) should be set to
-- 
2.39.2