[PATCH 0/7] ARM: stm32mp: random STM32MP13 fixes

[PATCH 0/7] ARM: stm32mp: random STM32MP13 fixes

[Ahmad Fatoum]

STM32MP135-DK board support has been broken by a device tree sync with
the kernel as the kernel now uses SCMI to communicate with OP-TEE for
controlling some clocks, resets, regulators and OTP.

A series for that is incoming once OP-TEE communication upstreaming
is complete, but for now, this series fixes random other stuff.

Ahmad Fatoum (7):
  ARM: dts: stm32mp: stm32mp135-dk: drop duplicate property
  ARM: dts: stm32mp: fix model string for stm32mp135f-dk
  ARM: stm32mp: init: drop unused macros
  ARM: stm32mp: don't re-enable DBGCFGR clock
  ARM: stm32mp: init: handle differences between STM32MP13 and STM32MP15
  ARM: stm32mp: init: don't print STM32MP15 CPU type
  ARM: stm32mp: init: ignore of_register_fixup return value

 arch/arm/boards/stm32mp15xx-dkx/lowlevel.c |   2 +-
 arch/arm/dts/stm32mp135f-dk.dts            |   6 +-
 arch/arm/mach-stm32mp/init.c               | 106 +++++----------------
 include/mach/stm32mp/revision.h            |  41 +++-----
 4 files changed, 38 insertions(+), 117 deletions(-)

-- 
2.39.2

[PATCH 1/7] ARM: dts: stm32mp: stm32mp135-dk: drop duplicate property

[Ahmad Fatoum]

The upstream device tree being included already has the same
/chosen/stdout-path, so drop it from the barebox DT.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/dts/stm32mp135f-dk.dts | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
index 3859566281f5..a4e6614c4a38 100644
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -5,8 +5,4 @@
 
 / {
 	model = "STM32MP153F-DK";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
 };
-- 
2.39.2

[PATCH 2/7] ARM: dts: stm32mp: fix model string for stm32mp135f-dk

[Ahmad Fatoum]

STM32MP153 is another SoC. Fix the typo.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/dts/stm32mp135f-dk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
index a4e6614c4a38..f07f7f5536fe 100644
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -4,5 +4,5 @@
 #include "stm32mp131.dtsi"
 
 / {
-	model = "STM32MP153F-DK";
+	model = "STM32MP135F-DK";
 };
-- 
2.39.2

[PATCH 3/7] ARM: stm32mp: init: drop unused macros

[Ahmad Fatoum]

The use of the TAMP registers differs between STM32MP15 and STM32MP13,
so let's drop all register definitions that we don't use instead of
renaming them to be SoC-specific.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-stm32mp/init.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index b63c1be5beac..b0220fdb8c7d 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -42,12 +42,8 @@
 
 /* TAMP registers */
 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
-/* secure access */
-#define TAMP_BACKUP_MAGIC_NUMBER        TAMP_BACKUP_REGISTER(4)
-#define TAMP_BACKUP_BRANCH_ADDRESS      TAMP_BACKUP_REGISTER(5)
 /* non secure access */
 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
-#define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(21)
 
 #define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
 #define TAMP_BOOT_MODE_SHIFT            8
-- 
2.39.2

[PATCH 4/7] ARM: stm32mp: don't re-enable DBGCFGR clock

[Ahmad Fatoum]

TF-A will already enable the DBGMCU peripheral for us, so let's
skip setting the bit. This is useful, because while the peripheral's
base address stays the same between MP15 and MP13, the clock's offset
within the RCC peripheral doesn't, so by skipping the clock enablement,
we avoid having to differentiate between MP13 and MP15 that early.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 include/mach/stm32mp/revision.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/include/mach/stm32mp/revision.h b/include/mach/stm32mp/revision.h
index 63bdcb3a4dbb..47e2651432bc 100644
--- a/include/mach/stm32mp/revision.h
+++ b/include/mach/stm32mp/revision.h
@@ -64,9 +64,6 @@ int stm32mp_package(void);
 #define DBGMCU_IDC_REV_ID_MASK	GENMASK(31, 16)
 #define DBGMCU_IDC_REV_ID_SHIFT	16
 
-#define RCC_DBGCFGR		(STM32_RCC_BASE + 0x080C)
-#define RCC_DBGCFGR_DBGCKEN	BIT(8)
-
 /* BSEC OTP index */
 #define BSEC_OTP_RPN	1
 #define BSEC_OTP_PKG	16
@@ -77,7 +74,6 @@ int stm32mp_package(void);
 
 static inline u32 stm32mp_read_idc(void)
 {
-	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
 	return readl(IOMEM(DBGMCU_IDC));
 }
 
-- 
2.39.2

[PATCH 5/7] ARM: stm32mp: init: handle differences between STM32MP13 and STM32MP15

[Ahmad Fatoum]

setup_cpu_type() was responsible for registering fixups for STM32MP15
and for initializing the values returned by stm32mp_silicon_revision(),
stm32mp_cputype() and stm32mp_package().

It has no support for STM32MP13 and the OTP on that SoC is accessed
differently from the STM32MP15, so let's just mark the function
STM32MP15-specific and delete all helpers that have no users instead of
having to duplicate them for STM32MP13.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/boards/stm32mp15xx-dkx/lowlevel.c |  2 +-
 arch/arm/mach-stm32mp/init.c               | 54 +++++++++-------------
 include/mach/stm32mp/revision.h            | 37 ++++++---------
 3 files changed, 36 insertions(+), 57 deletions(-)

diff --git a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
index f52a3f4375c0..402658d592d0 100644
--- a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
+++ b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
@@ -24,7 +24,7 @@ ENTRY_FUNCTION(start_stm32mp15xx_dkx, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	err = __stm32mp_get_cpu_type(&cputype);
+	err = __stm32mp15_get_cpu_type(&cputype);
 	if (!err && cputype == CPU_STM32MP157Axx)
 		fdt = __dtb_z_stm32mp157a_dk1_start;
 	else
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index b0220fdb8c7d..90f331ecd0dd 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -43,7 +43,8 @@
 /* TAMP registers */
 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
 /* non secure access */
-#define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
+#define STM32MP13_TAMP_BOOT_CONTEXT     TAMP_BACKUP_REGISTER(30)
+#define STM32MP15_TAMP_BOOT_CONTEXT     TAMP_BACKUP_REGISTER(20)
 
 #define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
 #define TAMP_BOOT_MODE_SHIFT            8
@@ -56,9 +57,8 @@
 #define FIXUP_CPU_NUM(mask) ((mask) >> 16)
 #define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL)
 
-static void setup_boot_mode(void)
+static void setup_boot_mode(u32 boot_ctx)
 {
-	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
 	u32 boot_mode =
 		(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
 	int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
@@ -97,24 +97,6 @@ static void setup_boot_mode(void)
 	bootsource_set_raw(src, instance);
 }
 
-static int __stm32mp_cputype;
-int stm32mp_cputype(void)
-{
-	return __stm32mp_cputype;
-}
-
-static int __stm32mp_silicon_revision;
-int stm32mp_silicon_revision(void)
-{
-	return __stm32mp_silicon_revision;
-}
-
-static int __stm32mp_package;
-int stm32mp_package(void)
-{
-	return __stm32mp_package;
-}
-
 static u32 get_cpu_revision(void)
 {
 	return (stm32mp_read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
@@ -177,15 +159,15 @@ static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg)
 	return fixup_pinctrl(root, "st,stm32mp157-z-pinctrl", pkg);
 }
 
-static int setup_cpu_type(void)
+static int stm32mp15_setup_cpu_type(void)
 {
 	const char *cputypestr, *cpupkgstr, *cpurevstr;
 	unsigned long cpufixupctx = 0, pkgfixupctx = 0;
-	u32 pkg;
+	int cputype, silicon_revision, package;
 	int ret;
 
-	__stm32mp_get_cpu_type(&__stm32mp_cputype);
-	switch (__stm32mp_cputype) {
+	__stm32mp15_get_cpu_type(&cputype);
+	switch (cputype) {
 	case CPU_STM32MP157Fxx:
 		cputypestr = "157F";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
@@ -239,8 +221,8 @@ static int setup_cpu_type(void)
 		break;
 	}
 
-	get_cpu_package(&__stm32mp_package );
-	switch (__stm32mp_package) {
+	get_cpu_package(&package);
+	switch (package) {
 	case PKG_AA_LBGA448:
 		cpupkgstr = "AA";
 		pkgfixupctx = STM32MP_PKG_AA;
@@ -262,8 +244,8 @@ static int setup_cpu_type(void)
 		break;
 	}
 
-	__stm32mp_silicon_revision = get_cpu_revision();
-	switch (__stm32mp_silicon_revision) {
+	silicon_revision = get_cpu_revision();
+	switch (silicon_revision) {
 	case CPU_REV_A:
 		cpurevstr = "A";
 		break;
@@ -278,7 +260,7 @@ static int setup_cpu_type(void)
 	}
 
 	pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n",
-		 __stm32mp_cputype, pkg, __stm32mp_silicon_revision);
+		 cputype, package, silicon_revision);
 	pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr);
 
 	if (cpufixupctx) {
@@ -302,6 +284,8 @@ int stm32mp_soc(void)
 
 static int stm32mp_init(void)
 {
+	u32 boot_ctx;
+
 	if (of_machine_is_compatible("st,stm32mp135"))
 		__st32mp_soc = 32135;
 	else if (of_machine_is_compatible("st,stm32mp151"))
@@ -313,8 +297,14 @@ static int stm32mp_init(void)
 	else
 		return 0;
 
-	setup_cpu_type();
-	setup_boot_mode();
+	if (__st32mp_soc == 32135) {
+		boot_ctx = readl(STM32MP13_TAMP_BOOT_CONTEXT);
+	} else {
+		stm32mp15_setup_cpu_type();
+		boot_ctx = readl(STM32MP15_TAMP_BOOT_CONTEXT);
+	}
+
+	setup_boot_mode(boot_ctx);
 
 	return 0;
 }
diff --git a/include/mach/stm32mp/revision.h b/include/mach/stm32mp/revision.h
index 47e2651432bc..73cc862a4e66 100644
--- a/include/mach/stm32mp/revision.h
+++ b/include/mach/stm32mp/revision.h
@@ -32,30 +32,14 @@
 #define CPU_STM32MP151Fxx	0x050000AE
 #define CPU_STM32MP151Dxx	0x050000AF
 
-#define cpu_stm32_is(mask, val) ({ \
-	u32 type; \
-	__stm32mp_get_cpu_type(&type) == 0 ? (type & mask) == val : 0; \
-})
-
-#define cpu_stm32_is_stm32mp15() cpu_stm32_is(0xFFFF0000, 0x05000000)
-#define cpu_stm32_is_stm32mp13() cpu_stm32_is(0xFFFF0000, 0x05010000)
+#define cpu_stm32_is_stm32mp15() (__stm32mp_get_cpu() == 0x0500)
+#define cpu_stm32_is_stm32mp13() (__stm32mp_get_cpu() == 0x0501)
 
 /* silicon revisions */
 #define CPU_REV_A	0x1000
 #define CPU_REV_B	0x2000
 #define CPU_REV_Z	0x2001
 
-int stm32mp_silicon_revision(void);
-int stm32mp_cputype(void);
-int stm32mp_package(void);
-
-#define cpu_is_stm32mp157c() (stm32mp_cputype() == CPU_STM32MP157Cxx)
-#define cpu_is_stm32mp157a() (stm32mp_cputype() == CPU_STM32MP157Axx)
-#define cpu_is_stm32mp153c() (stm32mp_cputype() == CPU_STM32MP153Cxx)
-#define cpu_is_stm32mp153a() (stm32mp_cputype() == CPU_STM32MP153Axx)
-#define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx)
-#define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx)
-
 /* DBGMCU register */
 #define DBGMCU_APB4FZ1		(STM32_DBGMCU_BASE + 0x2C)
 #define DBGMCU_IDC		(STM32_DBGMCU_BASE + 0x00)
@@ -77,8 +61,13 @@ static inline u32 stm32mp_read_idc(void)
 	return readl(IOMEM(DBGMCU_IDC));
 }
 
+static inline u32 __stm32mp_get_cpu(void)
+{
+	return stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK >> DBGMCU_IDC_DEV_ID_SHIFT;
+}
+
 /* Get Device Part Number (RPN) from OTP */
-static inline int __stm32mp_get_cpu_rpn(u32 *rpn)
+static inline int __stm32mp15_get_cpu_rpn(u32 *rpn)
 {
 	int ret = bsec_read_field(BSEC_OTP_RPN, rpn);
 	if (ret)
@@ -88,15 +77,15 @@ static inline int __stm32mp_get_cpu_rpn(u32 *rpn)
 	return 0;
 }
 
-static inline int __stm32mp_get_cpu_type(u32 *type)
+static inline int __stm32mp15_get_cpu_type(u32 *type)
 {
-	u32 id;
-	int ret = __stm32mp_get_cpu_rpn(type);
+	int ret;
+
+	ret = __stm32mp15_get_cpu_rpn(type);
 	if (ret)
 		return ret;
 
-	id = (stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
-	*type |= id << 16;
+	*type |= __stm32mp_get_cpu() << 16;
 	return 0;
 }
 
-- 
2.39.2

[PATCH 6/7] ARM: stm32mp: init: don't print STM32MP15 CPU type

[Ahmad Fatoum]

TF-A already reads the OTP and unconditionally prints at a higher log
level:

  NOTICE:  CPU: STM32MP157AAA Rev.B

barebox reads the OTP again via the secure monitor only to print:

  stm32mp-init: detected STM32MP157AAA Rev.B

which doesn't add any extra information, so drop it.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-stm32mp/init.c | 45 ++----------------------------------
 1 file changed, 2 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index 90f331ecd0dd..2b0a665220ce 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -97,11 +97,6 @@ static void setup_boot_mode(u32 boot_ctx)
 	bootsource_set_raw(src, instance);
 }
 
-static u32 get_cpu_revision(void)
-{
-	return (stm32mp_read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
-}
-
 static int get_cpu_package(u32 *pkg)
 {
 	int ret = bsec_read_field(BSEC_OTP_PKG, pkg);
@@ -161,107 +156,71 @@ static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg)
 
 static int stm32mp15_setup_cpu_type(void)
 {
-	const char *cputypestr, *cpupkgstr, *cpurevstr;
 	unsigned long cpufixupctx = 0, pkgfixupctx = 0;
-	int cputype, silicon_revision, package;
+	int cputype, package;
 	int ret;
 
 	__stm32mp15_get_cpu_type(&cputype);
 	switch (cputype) {
 	case CPU_STM32MP157Fxx:
-		cputypestr = "157F";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
 		break;
 	case CPU_STM32MP157Dxx:
-		cputypestr = "157D";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
 		break;
 	case CPU_STM32MP157Cxx:
-		cputypestr = "157C";
 		cpufixupctx = FIXUP_CPU_MASK(2, 650);
 		break;
 	case CPU_STM32MP157Axx:
-		cputypestr = "157A";
 		cpufixupctx = FIXUP_CPU_MASK(2, 650);
 		break;
 	case CPU_STM32MP153Fxx:
-		cputypestr = "153F";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
 		break;
 	case CPU_STM32MP153Dxx:
-		cputypestr = "153D";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
 		break;
 	case CPU_STM32MP153Cxx:
-		cputypestr = "153C";
 		cpufixupctx = FIXUP_CPU_MASK(2, 650);
 		break;
 	case CPU_STM32MP153Axx:
-		cputypestr = "153A";
 		cpufixupctx = FIXUP_CPU_MASK(2, 650);
 		break;
 	case CPU_STM32MP151Cxx:
-		cputypestr = "151C";
 		cpufixupctx = FIXUP_CPU_MASK(1, 650);
 		break;
 	case CPU_STM32MP151Axx:
-		cputypestr = "151A";
 		cpufixupctx = FIXUP_CPU_MASK(1, 650);
 		break;
 	case CPU_STM32MP151Fxx:
-		cputypestr = "151F";
 		cpufixupctx = FIXUP_CPU_MASK(1, 800);
 		break;
 	case CPU_STM32MP151Dxx:
-		cputypestr = "151D";
 		cpufixupctx = FIXUP_CPU_MASK(1, 800);
 		break;
 	default:
-		cputypestr = "????";
 		break;
 	}
 
 	get_cpu_package(&package);
 	switch (package) {
 	case PKG_AA_LBGA448:
-		cpupkgstr = "AA";
 		pkgfixupctx = STM32MP_PKG_AA;
 		break;
 	case PKG_AB_LBGA354:
-		cpupkgstr = "AB";
 		pkgfixupctx = STM32MP_PKG_AB;
 		break;
 	case PKG_AC_TFBGA361:
-		cpupkgstr = "AC";
 		pkgfixupctx = STM32MP_PKG_AC;
 		break;
 	case PKG_AD_TFBGA257:
-		cpupkgstr = "AD";
 		pkgfixupctx = STM32MP_PKG_AD;
 		break;
 	default:
-		cpupkgstr = "??";
 		break;
 	}
 
-	silicon_revision = get_cpu_revision();
-	switch (silicon_revision) {
-	case CPU_REV_A:
-		cpurevstr = "A";
-		break;
-	case CPU_REV_B:
-		cpurevstr = "B";
-		break;
-	case CPU_REV_Z:
-		cpurevstr = "Z";
-		break;
-	default:
-		cpurevstr = "?";
-	}
-
-	pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n",
-		 cputype, package, silicon_revision);
-	pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr);
+	pr_debug("cputype = 0x%x, package = 0x%x\n", cputype, package);
 
 	if (cpufixupctx) {
 		ret = of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
-- 
2.39.2

[PATCH 7/7] ARM: stm32mp: init: ignore of_register_fixup return value

[Ahmad Fatoum]

of_register_fixup can't actually fail, so drop the return value check
and propagation to make the code a bit more concise.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-stm32mp/init.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index 2b0a665220ce..2eb8b6beec2a 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -158,7 +158,6 @@ static int stm32mp15_setup_cpu_type(void)
 {
 	unsigned long cpufixupctx = 0, pkgfixupctx = 0;
 	int cputype, package;
-	int ret;
 
 	__stm32mp15_get_cpu_type(&cputype);
 	switch (cputype) {
@@ -222,14 +221,10 @@ static int stm32mp15_setup_cpu_type(void)
 
 	pr_debug("cputype = 0x%x, package = 0x%x\n", cputype, package);
 
-	if (cpufixupctx) {
-		ret = of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
-		if (ret)
-			return ret;
-	}
-
+	if (cpufixupctx)
+		of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
 	if (pkgfixupctx)
-		return of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx);
+		of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx);
 
 	return 0;
 }
-- 
2.39.2

Re: [PATCH 0/7] ARM: stm32mp: random STM32MP13 fixes

[Sascha Hauer]

On Wed, Nov 22, 2023 at 07:11:09PM +0100, Ahmad Fatoum wrote:
> STM32MP135-DK board support has been broken by a device tree sync with
> the kernel as the kernel now uses SCMI to communicate with OP-TEE for
> controlling some clocks, resets, regulators and OTP.
> 
> A series for that is incoming once OP-TEE communication upstreaming
> is complete, but for now, this series fixes random other stuff.
> 
> Ahmad Fatoum (7):
>   ARM: dts: stm32mp: stm32mp135-dk: drop duplicate property
>   ARM: dts: stm32mp: fix model string for stm32mp135f-dk
>   ARM: stm32mp: init: drop unused macros
>   ARM: stm32mp: don't re-enable DBGCFGR clock
>   ARM: stm32mp: init: handle differences between STM32MP13 and STM32MP15
>   ARM: stm32mp: init: don't print STM32MP15 CPU type
>   ARM: stm32mp: init: ignore of_register_fixup return value

Applied, thanks

Sascha

> 
>  arch/arm/boards/stm32mp15xx-dkx/lowlevel.c |   2 +-
>  arch/arm/dts/stm32mp135f-dk.dts            |   6 +-
>  arch/arm/mach-stm32mp/init.c               | 106 +++++----------------
>  include/mach/stm32mp/revision.h            |  41 +++-----
>  4 files changed, 38 insertions(+), 117 deletions(-)
> 
> -- 
> 2.39.2
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |