[PATCH 1/2] mci: core: check for both 3.3v and 1.8v DDR support

[PATCH 1/2] mci: core: check for both 3.3v and 1.8v DDR support

[Ahmad Fatoum]

We don't yet support the higher speed modes that require voltage
switching, so regulator interaction in barebox was so far limited to
enabling the supply. barebox also doesn't keep track what voltage the
eMMC is running on, so it doesn't know whether MMC_CAP_MMC_1_8V_DDR
or MMC_CAP_MMC_3_3V_DDR is the correct bit to check. Let's just accept
either until we add support for higher speed modes. barebox will
fallback to the non-DDR speed mode anyway if it fails to read the
ext_csd using it.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/mci/mci-core.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index 175753cca5d7..07eca96a9d61 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -1289,7 +1289,13 @@ static int mci_mmc_select_hs_ddr(struct mci *mci)
 	struct mci_host *host = mci->host;
 	int ret;
 
-	if (!(mci_caps(mci) & MMC_CAP_MMC_1_8V_DDR))
+	/*
+	 * barebox MCI core does not change voltage, so we don't know here
+	 * if we should check for the 1.8v or 3.3v mode. Until we support
+	 * higher speed modes that require voltage switching like HS200/HS400,
+	 * let's just check for either bit.
+	 */
+	if (!(mci_caps(mci) & (MMC_CAP_MMC_1_8V_DDR | MMC_CAP_MMC_3_3V_DDR)))
 		return 0;
 
 	ret = mci_mmc_try_bus_width(mci, host->bus_width, MMC_TIMING_MMC_DDR52);
-- 
2.39.2

[PATCH 2/2] mci: stm32_sdmmc2: enable eMMC 52MHz DDR mode

[Ahmad Fatoum]

Dual data rate can be enabled on STM32 SDMMC2 host by toggling a bit in
the CLKRC register and avoiding clock bypass. Let's do that for a nice
boost in throughput. Before:

  barebox@STM32MP157C-ED1:/ time cp /dev/mmc0.data /tmp
  time: 2684ms

After:

  barebox@STM32MP157C-ED1:/ time cp /dev/mmc1.data /tmp
  time: 1624ms

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/mci/stm32_sdmmc2.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/mci/stm32_sdmmc2.c b/drivers/mci/stm32_sdmmc2.c
index 90e969a867e6..1bfef1ccf0eb 100644
--- a/drivers/mci/stm32_sdmmc2.c
+++ b/drivers/mci/stm32_sdmmc2.c
@@ -538,11 +538,14 @@ static void stm32_sdmmc2_set_ios(struct mci_host *mci, struct mci_ios *ios)
 	struct stm32_sdmmc2_priv *priv = to_mci_host(mci);
 	u32 desired = mci->clock;
 	u32 sys_clock = clk_get_rate(priv->clk);
-	u32 clk = 0;
+	u32 clk = 0, ddr = 0;
 
 	dev_dbg(priv->dev, "%s: bus_width = %d, clock = %d\n", __func__,
 		mci->bus_width, mci->clock);
 
+	if (mci_timing_is_ddr(ios->timing))
+		ddr = SDMMC_CLKCR_DDR;
+
 	if (mci->clock)
 		stm32_sdmmc2_pwron(priv);
 	else
@@ -555,13 +558,15 @@ static void stm32_sdmmc2_set_ios(struct mci_host *mci, struct mci_ios *ios)
 	 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 	 * SDMMCCLK falling edge
 	 */
-	if (desired && (sys_clock > desired ||
+	if (desired && (sys_clock > desired || ddr ||
 			IS_RISING_EDGE(priv->clk_reg_msk))) {
 		clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 		if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 			clk = SDMMC_CLKCR_CLKDIV_MAX;
 	}
 
+	clk |= ddr;
+
 	if (mci->bus_width == MMC_BUS_WIDTH_4)
 		clk |= SDMMC_CLKCR_WIDBUS_4;
 	if (mci->bus_width == MMC_BUS_WIDTH_8)
@@ -624,6 +629,11 @@ static int stm32_sdmmc2_probe(struct amba_device *adev,
 	if (mci->f_max >= 52000000)
 		mci->host_caps |= MMC_CAP_MMC_HIGHSPEED_52MHZ;
 
+	if (of_property_read_bool(np, "mmc-ddr-3_3v"))
+		mci->host_caps |= MMC_CAP_MMC_3_3V_DDR;
+	if (of_property_read_bool(np, "mmc-ddr-1_8v"))
+		mci->host_caps |= MMC_CAP_MMC_1_8V_DDR;
+
 	return mci_register(&priv->mci);
 
 priv_free:
-- 
2.39.2

Re: [PATCH 2/2] mci: stm32_sdmmc2: enable eMMC 52MHz DDR mode

[Ahmad Fatoum]

On 23.11.23 11:38, Ahmad Fatoum wrote:
> Dual data rate can be enabled on STM32 SDMMC2 host by toggling a bit in
> the CLKRC register and avoiding clock bypass. Let's do that for a nice
> boost in throughput. Before:
> 
>   barebox@STM32MP157C-ED1:/ time cp /dev/mmc0.data /tmp
>   time: 2684ms
> 
> After:
> 
>   barebox@STM32MP157C-ED1:/ time cp /dev/mmc1.data /tmp
>   time: 1624ms

while reading a 100 MiB partition, i.e. 37.2 MiB/s -> 61.5 MiB/s.

> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  drivers/mci/stm32_sdmmc2.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mci/stm32_sdmmc2.c b/drivers/mci/stm32_sdmmc2.c
> index 90e969a867e6..1bfef1ccf0eb 100644
> --- a/drivers/mci/stm32_sdmmc2.c
> +++ b/drivers/mci/stm32_sdmmc2.c
> @@ -538,11 +538,14 @@ static void stm32_sdmmc2_set_ios(struct mci_host *mci, struct mci_ios *ios)
>  	struct stm32_sdmmc2_priv *priv = to_mci_host(mci);
>  	u32 desired = mci->clock;
>  	u32 sys_clock = clk_get_rate(priv->clk);
> -	u32 clk = 0;
> +	u32 clk = 0, ddr = 0;
>  
>  	dev_dbg(priv->dev, "%s: bus_width = %d, clock = %d\n", __func__,
>  		mci->bus_width, mci->clock);
>  
> +	if (mci_timing_is_ddr(ios->timing))
> +		ddr = SDMMC_CLKCR_DDR;
> +
>  	if (mci->clock)
>  		stm32_sdmmc2_pwron(priv);
>  	else
> @@ -555,13 +558,15 @@ static void stm32_sdmmc2_set_ios(struct mci_host *mci, struct mci_ios *ios)
>  	 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
>  	 * SDMMCCLK falling edge
>  	 */
> -	if (desired && (sys_clock > desired ||
> +	if (desired && (sys_clock > desired || ddr ||
>  			IS_RISING_EDGE(priv->clk_reg_msk))) {
>  		clk = DIV_ROUND_UP(sys_clock, 2 * desired);
>  		if (clk > SDMMC_CLKCR_CLKDIV_MAX)
>  			clk = SDMMC_CLKCR_CLKDIV_MAX;
>  	}
>  
> +	clk |= ddr;
> +
>  	if (mci->bus_width == MMC_BUS_WIDTH_4)
>  		clk |= SDMMC_CLKCR_WIDBUS_4;
>  	if (mci->bus_width == MMC_BUS_WIDTH_8)
> @@ -624,6 +629,11 @@ static int stm32_sdmmc2_probe(struct amba_device *adev,
>  	if (mci->f_max >= 52000000)
>  		mci->host_caps |= MMC_CAP_MMC_HIGHSPEED_52MHZ;
>  
> +	if (of_property_read_bool(np, "mmc-ddr-3_3v"))
> +		mci->host_caps |= MMC_CAP_MMC_3_3V_DDR;
> +	if (of_property_read_bool(np, "mmc-ddr-1_8v"))
> +		mci->host_caps |= MMC_CAP_MMC_1_8V_DDR;
> +
>  	return mci_register(&priv->mci);
>  
>  priv_free:

-- 
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Re: [PATCH 1/2] mci: core: check for both 3.3v and 1.8v DDR support

[Sascha Hauer]

On Thu, Nov 23, 2023 at 11:38:07AM +0100, Ahmad Fatoum wrote:
> We don't yet support the higher speed modes that require voltage
> switching, so regulator interaction in barebox was so far limited to
> enabling the supply. barebox also doesn't keep track what voltage the
> eMMC is running on, so it doesn't know whether MMC_CAP_MMC_1_8V_DDR
> or MMC_CAP_MMC_3_3V_DDR is the correct bit to check. Let's just accept
> either until we add support for higher speed modes. barebox will
> fallback to the non-DDR speed mode anyway if it fails to read the
> ext_csd using it.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  drivers/mci/mci-core.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)

Applied, thanks

Sascha

> 
> diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
> index 175753cca5d7..07eca96a9d61 100644
> --- a/drivers/mci/mci-core.c
> +++ b/drivers/mci/mci-core.c
> @@ -1289,7 +1289,13 @@ static int mci_mmc_select_hs_ddr(struct mci *mci)
>  	struct mci_host *host = mci->host;
>  	int ret;
>  
> -	if (!(mci_caps(mci) & MMC_CAP_MMC_1_8V_DDR))
> +	/*
> +	 * barebox MCI core does not change voltage, so we don't know here
> +	 * if we should check for the 1.8v or 3.3v mode. Until we support
> +	 * higher speed modes that require voltage switching like HS200/HS400,
> +	 * let's just check for either bit.
> +	 */
> +	if (!(mci_caps(mci) & (MMC_CAP_MMC_1_8V_DDR | MMC_CAP_MMC_3_3V_DDR)))
>  		return 0;
>  
>  	ret = mci_mmc_try_bus_width(mci, host->bus_width, MMC_TIMING_MMC_DDR52);
> -- 
> 2.39.2
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |