[PATCH 1/3] mci: imx-esdhc: Fix WML setting for layerscape PBL

[PATCH 1/3] mci: imx-esdhc: Fix WML setting for layerscape PBL

[Sascha Hauer]

For the Layerscape PBL to correctly work in PBL we have to configure the
read watermark level to 0x80 aka one full block of 512 bytes (0x80 * sizeof(u32))

With the current value of 0x10 the ESDHC will signal data available, but
we are only allowed to read 0x10 words. After that we would have to wait
for data being ready again, but sdhci_rx_pio() does not do that.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc-common.c | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/mci/imx-esdhc-common.c b/drivers/mci/imx-esdhc-common.c
index 3c1ff98824..3d93889143 100644
--- a/drivers/mci/imx-esdhc-common.c
+++ b/drivers/mci/imx-esdhc-common.c
@@ -59,19 +59,14 @@ static int esdhc_setup_data(struct fsl_esdhc_host *host, struct mci_data *data,
 	u32 wml_value;
 
 	wml_value = data->blocksize / 4;
+	if (wml_value > 0x80)
+		wml_value = 0x80;
 
-	if (data->flags & MMC_DATA_READ) {
-		if (wml_value > 0x10)
-			wml_value = 0x10;
-
+	if (data->flags & MMC_DATA_READ)
 		esdhc_clrsetbits32(host, IMX_SDHCI_WML, WML_RD_WML_MASK, wml_value);
-	} else {
-		if (wml_value > 0x80)
-			wml_value = 0x80;
-
+	else
 		esdhc_clrsetbits32(host, IMX_SDHCI_WML, WML_WR_WML_MASK,
 					wml_value << 16);
-	}
 
 	host->sdhci.sdma_boundary = 0;
 
-- 
2.39.2

[PATCH 2/3] mci: imx-esdhc-pbl: ls1046a: Add missing ESDHC_FLAG_MULTIBLK_NO_INT

[Sascha Hauer]

LS1046a needs the ESDHC_FLAG_MULTIBLK_NO_INT flag. Without it we run
into a timeout ("timeout 2") during a MMC_CMD_STOP_TRANSMISSION command.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc-pbl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index f789f43b69..892329de51 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -321,7 +321,7 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
 	int ret;
 	uint32_t val;
 	struct esdhc_soc_data data = {
-		.flags = ESDHC_FLAG_BIGENDIAN,
+		.flags = ESDHC_FLAG_MULTIBLK_NO_INT | ESDHC_FLAG_BIGENDIAN,
 	};
 	struct fsl_esdhc_host host = {
 		.sdhci.base = IOMEM(0x01560000),
-- 
2.39.2

[PATCH 3/3] mci: imx-esdhc-pbl: fix prediv setting

[Sascha Hauer]

We use a hardcoded minimum pre_div value of 2. This leads to suboptimal
rates on some SoCs. The pre_div minimum of 2 is required only on one
controller found on the i.MX53, so limit this quirk to this controller
only and use pre_div minimum of 1 for all other controllers.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index e1d4e3c2d4..d2a590a967 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -21,6 +21,8 @@
 #include <platform_data/mmc-esdhc-imx.h>
 #include <gpio.h>
 #include <of_device.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx53-regs.h>
 
 #include "sdhci.h"
 #include "imx-esdhc.h"
@@ -57,15 +59,11 @@ static void set_sysctl(struct mci_host *mci, u32 clock, bool ddr)
 	if (esdhc_is_layerscape(host))
 		sdhc_clk >>= 1;
 
-	/*
-	 * With eMMC and imx53 (sdhc_clk=200MHz) a pre_div of 1 results in
-	 *	pre_div=1,div=4 (=50MHz)
-	 * which is valid and should work, but somehow doesn't.
-	 * Starting with pre_div=2 gives
-	 *	pre_div=2, div=2 (=50MHz)
-	 * and works fine.
-	 */
-	pre_div = 2;
+	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+	if (cpu_is_mx53() && host->sdhci.base == (void *)MX53_ESDHC3_BASE_ADDR)
+		pre_div = 2;
+	else
+		pre_div = 1;
 
 	if (sdhc_clk == clock)
 		pre_div = 1;
-- 
2.39.2