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Wed, 03 Jan 2024 19:30:53 +0100 Received: from localhost ([::1] helo=dude05.red.stw.pengutronix.de) by dude05.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1rL5k3-001j4X-1x; Wed, 03 Jan 2024 19:13:23 +0100 From: Ahmad Fatoum To: barebox@lists.infradead.org Cc: Michael Olbrich , Ahmad Fatoum Date: Wed, 3 Jan 2024 19:12:19 +0100 Message-Id: <20240103181312.409668-60-a.fatoum@pengutronix.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103181312.409668-1-a.fatoum@pengutronix.de> References: <20240103181312.409668-1-a.fatoum@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240103_183055_601088_E445E404 X-CRM114-Status: GOOD ( 14.13 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-6.3 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 059/112] efi: payload: init: restrict barebox mem to first 1G only on x86 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) When run as EFI payload, barebox will not have full access to DRAM and will have to ask the EFI firmware for memory. It does so once at the beginning and since commit 356aaef5a37d ("efi: improve malloc pool allocation"), the buffer was always placed beneath the 1G boundary. Aforementioned commit didn't elaborate why a maximum of 1G in particular was chosen. Anyways, non-PC architectures have different memory maps, so a 1G limit doesn't make sense there. Therefore restrict the limit to ARCH_X86. On non-x86, we allow the memory pages to be located anywhere. This can break PCI drivers on systems that so far assumed barebox memory is located in the first 4G, but that's ok. That code will need to be fixed eventually anyway. Cc: Michael Olbrich Signed-off-by: Ahmad Fatoum --- efi/payload/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/efi/payload/init.c b/efi/payload/init.c index 4b612e61afb3..0c2f38e9c86a 100644 --- a/efi/payload/init.c +++ b/efi/payload/init.c @@ -292,7 +292,7 @@ void efi_main(efi_handle_t image, struct efi_system_table *sys_table) BS->handle_protocol(efi_loaded_image->device_handle, &efi_device_path_protocol_guid, (void **)&efi_device_path); - mem = 0x3fffffff; + mem = IS_ENABLED(CONFIG_X86) ? 0x3fffffff : ~0ULL; for (memsize = SZ_256M; memsize >= SZ_8M; memsize /= 2) { efiret = BS->allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, EFI_LOADER_DATA, -- 2.39.2