[PATCH 02/19] soc/fsl/immap_lsch2.h: cleanup

[Sascha Hauer <s.hauer@pengutronix.de>]

Some values differ between LS1046a and LS1021. Move them directly where
needed so that we can drop the #ifdef SOC_TYPE from immap_lsch2.h

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-layerscape/lowlevel-ls102xa.c | 5 +++++
 include/soc/fsl/immap_lsch2.h               | 6 ------
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-layerscape/lowlevel-ls102xa.c b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
index 259d8866d5..7ea0a5b071 100644
--- a/arch/arm/mach-layerscape/lowlevel-ls102xa.c
+++ b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
@@ -299,6 +299,11 @@ static void fsl_epu_clean(void *epu_base)
 		out_be32(epu_base + offset, 0);
 }
 
+#define TIMER_COMP_VAL			0xffffffffffffffffull
+#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
+#define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
+#define SCFG_QSPI_CLKSEL		0x50100000
+
 /* ls102xa_init_lowlevel
  * Based on ls1046 and U-boot ls102xa arch_cpu_init
  */
diff --git a/include/soc/fsl/immap_lsch2.h b/include/soc/fsl/immap_lsch2.h
index 62e48ae746..ce840d4223 100644
--- a/include/soc/fsl/immap_lsch2.h
+++ b/include/soc/fsl/immap_lsch2.h
@@ -63,10 +63,6 @@
 #define LSCH2_QDMA_BASE_ADDR		(LSCH2_IMMR + 0x07380000)
 #define LSCH2_EHCI_USB1_ADDR		(LSCH2_IMMR + 0x07600000)
 
-#define TIMER_COMP_VAL			0xffffffffffffffffull
-#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
-#define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
-
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK	0xFF800000
@@ -306,13 +302,11 @@ struct ls102xa_ccsr_gur {
 #define SCFG_USB_PHY3			0x08510000
 #define SCFG_USB_PHY_RX_OVRD_IN_HI		0x200c
 #if defined CONFIG_ARCH_LS1046
-#define SCFG_QSPI_CLKSEL		0x40100000
 #define USB_PHY_RX_EQ_VAL_1		0x0000
 #define USB_PHY_RX_EQ_VAL_2		0x0080
 #define USB_PHY_RX_EQ_VAL_3		0x0380
 #define USB_PHY_RX_EQ_VAL_4		0x0b80
 #elif defined CONFIG_ARCH_LS1021
-#define SCFG_QSPI_CLKSEL		0x50100000
 #define USB_PHY_RX_EQ_VAL_1		0x0000
 #define USB_PHY_RX_EQ_VAL_2		0x8000
 #define USB_PHY_RX_EQ_VAL_3		0x8004
-- 
2.39.2