[PATCH 03/19] ARM: layerscape: decide SCFG endianess during runtime

[Sascha Hauer <s.hauer@pengutronix.de>]

SCFG endianess differs between SoCs. Currently supported SoCs have a big
endian SCFG unit, but upcoming LS1028a support has a little endian SCFG.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-layerscape/Makefile           |  2 +-
 arch/arm/mach-layerscape/errata.c           |  4 +-
 arch/arm/mach-layerscape/lowlevel-ls102xa.c |  2 +
 arch/arm/mach-layerscape/lowlevel-ls1046a.c |  2 +
 arch/arm/mach-layerscape/soc.c              | 56 +++++++++++++++++++++
 include/soc/fsl/scfg.h                      | 19 +++++++
 6 files changed, 81 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-layerscape/soc.c
 create mode 100644 include/soc/fsl/scfg.h

diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index ed55867390..ebb030a1cb 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -4,7 +4,7 @@ obj- := __dummy__.o
 lwl-y += errata.o
 lwl-$(CONFIG_ARCH_LS1046) += lowlevel.o lowlevel-ls1046a.o
 obj-$(CONFIG_ARCH_LS1046) += icid.o
-obj-pbl-y += boot.o
+obj-pbl-y += boot.o soc.o
 pbl-y += xload-qspi.o xload.o
 obj-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa.o ppa-entry.o
 obj-$(CONFIG_BOOTM) += pblimage.o
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index 6cb95453e7..e3793b3bcd 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -6,9 +6,7 @@
 #include <asm/system.h>
 #include <mach/layerscape/errata.h>
 #include <mach/layerscape/lowlevel.h>
-
-#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
-#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
+#include <soc/fsl/scfg.h>
 
 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
 {
diff --git a/arch/arm/mach-layerscape/lowlevel-ls102xa.c b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
index 7ea0a5b071..440d50282a 100644
--- a/arch/arm/mach-layerscape/lowlevel-ls102xa.c
+++ b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
@@ -14,6 +14,7 @@
 #include <mach/layerscape/fsl_epu.h>
 #include <soc/fsl/immap_lsch2.h>
 #include <soc/fsl/fsl_immap.h>
+#include <soc/fsl/scfg.h>
 
 void udelay(unsigned long usecs)
 {
@@ -320,6 +321,7 @@ void ls102xa_init_lowlevel(void)
 	cortex_a7_lowlevel_init();
 	arm_cpu_lowlevel_init();
 
+	scfg_init(SCFG_ENDIANESS_BIG);
 	init_csu();
 
 	writel(SYS_COUNTER_CTRL_ENABLE, LSCH2_SYS_COUNTER_ADDR);
diff --git a/arch/arm/mach-layerscape/lowlevel-ls1046a.c b/arch/arm/mach-layerscape/lowlevel-ls1046a.c
index b2aa839f55..3393dc4903 100644
--- a/arch/arm/mach-layerscape/lowlevel-ls1046a.c
+++ b/arch/arm/mach-layerscape/lowlevel-ls1046a.c
@@ -7,6 +7,7 @@
 #include <mach/layerscape/lowlevel.h>
 #include <soc/fsl/immap_lsch2.h>
 #include <soc/fsl/fsl_immap.h>
+#include <soc/fsl/scfg.h>
 
 enum csu_cslx_access {
 	CSU_NS_SUP_R = 0x08,
@@ -222,6 +223,7 @@ void ls1046a_init_lowlevel(void)
 	struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR);
 	struct ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR);
 
+	scfg_init(SCFG_ENDIANESS_BIG);
 	init_csu();
 	ls1046a_init_l2_latency();
 	set_cntfrq(25000000);
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
new file mode 100644
index 0000000000..2d9a2b4629
--- /dev/null
+++ b/arch/arm/mach-layerscape/soc.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <soc/fsl/scfg.h>
+#include <io.h>
+#include <linux/bug.h>
+
+static enum scfg_endianess scfg_endianess = SCFG_ENDIANESS_INVALID;
+
+static void scfg_check_endianess(void)
+{
+	BUG_ON(scfg_endianess == SCFG_ENDIANESS_INVALID);
+}
+
+void scfg_clrsetbits32(void __iomem *addr, u32 clear, u32 set)
+{
+	scfg_check_endianess();
+
+	if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+		clrsetbits_le32(addr, clear, set);
+	else
+		clrsetbits_be32(addr, clear, set);
+}
+
+void scfg_clrbits32(void __iomem *addr, u32 clear)
+{
+	scfg_check_endianess();
+
+	if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+		clrbits_le32(addr, clear);
+	else
+		clrbits_be32(addr, clear);
+}
+
+void scfg_setbits32(void __iomem *addr, u32 set)
+{
+	scfg_check_endianess();
+
+	if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+		setbits_le32(addr, set);
+	else
+		setbits_be32(addr, set);
+}
+
+void scfg_out16(void __iomem *addr, u16 val)
+{
+	scfg_check_endianess();
+
+	if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+		out_le16(addr, val);
+	else
+		out_be16(addr, val);
+}
+
+void scfg_init(enum scfg_endianess endianess)
+{
+	scfg_endianess = endianess;
+}
diff --git a/include/soc/fsl/scfg.h b/include/soc/fsl/scfg.h
new file mode 100644
index 0000000000..bea184218e
--- /dev/null
+++ b/include/soc/fsl/scfg.h
@@ -0,0 +1,19 @@
+#ifndef __SOC_FSL_SCFG_H
+#define __SOC_FSL_SCFG_H
+
+#include <soc/fsl/scfg.h>
+#include <linux/compiler.h>
+
+enum scfg_endianess {
+	SCFG_ENDIANESS_INVALID,
+	SCFG_ENDIANESS_LITTLE,
+	SCFG_ENDIANESS_BIG,
+};
+
+void scfg_clrsetbits32(void __iomem *addr, u32 clear, u32 set);
+void scfg_clrbits32(void __iomem *addr, u32 clear);
+void scfg_setbits32(void __iomem *addr, u32 set);
+void scfg_out16(void __iomem *addr, u16 val);
+void scfg_init(enum scfg_endianess endianess);
+
+#endif /* __SOC_FSL_SCFG_H */
-- 
2.39.2