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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH v2 04/11] RISC-V: StarFive: J7100: set /soc/dma-noncoherent
Date: Wed, 10 Jan 2024 17:01:06 +0100	[thread overview]
Message-ID: <20240110160112.4134162-5-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20240110160112.4134162-1-a.fatoum@pengutronix.de>

With upcoming changes, cache handling will be skipped on RISC-V, because
arch is cache-coherent by default. StarFive JH7100 has non-coherent DMA
masters though, so note that in the DT.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - no change
---
 arch/riscv/Kconfig.socs    | 1 +
 arch/riscv/dts/jh7100.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 56ba5ecf5865..cef9cd52300c 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -88,6 +88,7 @@ config SOC_STARFIVE_JH7100
 	bool
 	select SOC_STARFIVE_JH71XX
 	select SIFIVE_L2
+	select OF_DMA_COHERENCY
 	help
 	  Unlike JH7110 and later, CPU on the JH7100 are not cache-coherent
 	  with respect to DMA masters like GMAC and DW MMC controller.
diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi
index e3990582af97..b11801553bf7 100644
--- a/arch/riscv/dts/jh7100.dtsi
+++ b/arch/riscv/dts/jh7100.dtsi
@@ -212,6 +212,7 @@ soc {
 		#clock-cells = <1>;
 		compatible = "simple-bus";
 		ranges;
+		dma-noncoherent;
 
 		intram0: sram@18000000 {
 			compatible = "mmio-sram";
-- 
2.39.2




  parent reply	other threads:[~2024-01-10 16:02 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10 16:01 [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 01/11] dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 02/11] dma: select ARCH_DMA_DEFAULT_COHERENT for x86 and sandbox Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 03/11] dma: introduce CONFIG_OF_DMA_COHERENCY Ahmad Fatoum
2024-01-10 16:01 ` Ahmad Fatoum [this message]
2024-01-10 16:01 ` [PATCH v2 05/11] ARM: dts: layerscape: add header for barebox DT overrides Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 06/11] ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DT Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 07/11] of: populate new device_d::dma_coherent attribute Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 08/11] dma: fix dma_sync when not all device DMA is equally coherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 09/11] dma: align barebox DMA coherency setting with kernel's Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 10/11] ARM: layerscape: configure all DMA masters to be cache-coherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 11/11] ARM: layerscape: enable DWC3 snooping on ls1046a Ahmad Fatoum
2024-01-11 14:11 ` [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent Sascha Hauer
2024-01-11 14:15   ` Ahmad Fatoum
2024-01-11 14:44     ` Sascha Hauer

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