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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH v2 08/11] dma: fix dma_sync when not all device DMA is equally coherent
Date: Wed, 10 Jan 2024 17:01:10 +0100	[thread overview]
Message-ID: <20240110160112.4134162-9-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20240110160112.4134162-1-a.fatoum@pengutronix.de>

The LS1046A features a cache-coherent interconnect and the drivers
configure the hardware appropriately, e.g. setting the FMan PRAM_MODE_GLOBAL
bit, so the existing Ethernet Controllers snoop caches.

Yet, we use the standard arm64 cache maintenance routines when the MMU
is enabled and thus risk memory corruption if CPU prefetches receive buffers
in the time window between dma_map_single() cleaning them to
Point-of-Coherency and dma_unmap_single() invalidating them[1].

To properly solve this issue, we need to consult the newly added per-device
dma coherent attribute to decide whether to do manual cache maintenance.

[1]: https://lore.kernel.org/all/a5d6cc26-cd23-7c31-f56e-f6d535ea39b0@arm.com/

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
v1 -> v2:
  - switch to boolean comparisons instead of comparison <= or >= to zero
---
 drivers/dma/map.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/map.c b/drivers/dma/map.c
index e320f6aad4ac..ab86a8c7b139 100644
--- a/drivers/dma/map.c
+++ b/drivers/dma/map.c
@@ -9,7 +9,8 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t address,
 
 	debug_dma_sync_single_for_cpu(dev, address, size, dir);
 
-	arch_sync_dma_for_cpu(ptr, size, dir);
+	if (!dev_is_dma_coherent(dev))
+		arch_sync_dma_for_cpu(ptr, size, dir);
 }
 
 void dma_sync_single_for_device(struct device *dev, dma_addr_t address,
@@ -19,7 +20,8 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t address,
 
 	debug_dma_sync_single_for_device(dev, address, size, dir);
 
-	arch_sync_dma_for_device(ptr, size, dir);
+	if (!dev_is_dma_coherent(dev))
+		arch_sync_dma_for_device(ptr, size, dir);
 }
 
 dma_addr_t dma_map_single(struct device *dev, void *ptr,
@@ -29,7 +31,8 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr,
 
 	debug_dma_map(dev, ptr, size, dir, dma_addr);
 
-	arch_sync_dma_for_device(ptr, size, dir);
+	if (!dev_is_dma_coherent(dev))
+		arch_sync_dma_for_device(ptr, size, dir);
 
 	return dma_addr;
 }
@@ -37,7 +40,8 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr,
 void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
 				    size_t size, enum dma_data_direction dir)
 {
-	dma_sync_single_for_cpu(dev, dma_addr, size, dir);
+	if (!dev_is_dma_coherent(dev))
+		dma_sync_single_for_cpu(dev, dma_addr, size, dir);
 
 	debug_dma_unmap(dev, dma_addr, size, dir);
 }
-- 
2.39.2




  parent reply	other threads:[~2024-01-10 16:02 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10 16:01 [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 01/11] dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 02/11] dma: select ARCH_DMA_DEFAULT_COHERENT for x86 and sandbox Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 03/11] dma: introduce CONFIG_OF_DMA_COHERENCY Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 04/11] RISC-V: StarFive: J7100: set /soc/dma-noncoherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 05/11] ARM: dts: layerscape: add header for barebox DT overrides Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 06/11] ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DT Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 07/11] of: populate new device_d::dma_coherent attribute Ahmad Fatoum
2024-01-10 16:01 ` Ahmad Fatoum [this message]
2024-01-10 16:01 ` [PATCH v2 09/11] dma: align barebox DMA coherency setting with kernel's Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 10/11] ARM: layerscape: configure all DMA masters to be cache-coherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 11/11] ARM: layerscape: enable DWC3 snooping on ls1046a Ahmad Fatoum
2024-01-11 14:11 ` [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent Sascha Hauer
2024-01-11 14:15   ` Ahmad Fatoum
2024-01-11 14:44     ` Sascha Hauer

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