[PATCH 0/3] soc: imx: featctrl: finalize support for i.MX8MP

[PATCH 0/3] soc: imx: featctrl: finalize support for i.MX8MP

[Ahmad Fatoum]

We only had preliminary feature controller support for i.MX8MP and
support for detecting missing VPU, DSP, NPU, LVDS and CPUs was missing.

Add support for them, so barebox may fix up the kernel device tree to
disable these nodes. This is especially important for the VPU and NPU as
the kernel's blk-ctrl power domain driver may try to power them down as
they are unused, which would make the SoC hang.

Ahmad Fatoum (3):
  soc: imx: imx8m-featctrl: make header self-contained
  nvmem: ocotp: prepare adding tester3 support
  soc: imx: featctrl: finalize support for i.MX8MP

 arch/arm/dts/imx8mp.dtsi             | 54 +++++++++++++++++++++++++++-
 drivers/nvmem/ocotp.c                | 27 +++++++++-----
 drivers/soc/imx/imx8m-featctrl.c     | 45 +++++++++++++++--------
 include/dt-bindings/features/imx8m.h |  5 ++-
 include/soc/imx8m/featctrl.h         | 25 +++++++++----
 5 files changed, 123 insertions(+), 33 deletions(-)

-- 
2.39.2

[PATCH 1/3] soc: imx: imx8m-featctrl: make header self-contained

[Ahmad Fatoum]

struct device is the only undefined type in the header, so
forward-declare it to make the header independent of include order.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 include/soc/imx8m/featctrl.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/soc/imx8m/featctrl.h b/include/soc/imx8m/featctrl.h
index 9c494f071d02..91d14bc68c0a 100644
--- a/include/soc/imx8m/featctrl.h
+++ b/include/soc/imx8m/featctrl.h
@@ -14,6 +14,8 @@ struct imx8m_featctrl_data {
 	bool check_cpus;
 };
 
+struct device;
+
 #ifdef CONFIG_IMX8M_FEATCTRL
 int imx8m_feat_ctrl_init(struct device *dev, u32 tester4,
 			 const struct imx8m_featctrl_data *data);
-- 
2.39.2

[PATCH 2/3] nvmem: ocotp: prepare adding tester3 support

[Ahmad Fatoum]

The tester fuses are written to the OCOTP by NXP during production.
So far, we only evaluated tester4 to determine which peripherals
are missing from the SoC. On the i.MX8MP, VPU and CPUs existence is
instead encoded into the tester3 fuse word. In preparation for adding
support for tester4, rename the existing masks to be tester4-specific.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/nvmem/ocotp.c            | 14 +++++++-------
 drivers/soc/imx/imx8m-featctrl.c | 32 +++++++++++++++++++-------------
 include/soc/imx8m/featctrl.h     | 12 +++++++-----
 3 files changed, 33 insertions(+), 25 deletions(-)

diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index 66a88ae48033..ccdc8a417ed1 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -959,9 +959,9 @@ static struct imx_ocotp_data vf610_ocotp_data = {
 };
 
 static struct imx8m_featctrl_data imx8mp_featctrl_data = {
-	.gpu_bitmask = 0xc0,
-	.mipi_dsi_bitmask = 0x60000,
-	.isp_bitmask = 0x3,
+	.tester4.gpu_bitmask = 0xc0,
+	.tester4.mipi_dsi_bitmask = 0x60000,
+	.tester4.isp_bitmask = 0x3,
 };
 
 static struct imx_ocotp_data imx8mp_ocotp_data = {
@@ -990,8 +990,8 @@ static struct imx_ocotp_data imx8mq_ocotp_data = {
 };
 
 static struct imx8m_featctrl_data imx8mm_featctrl_data = {
-	.vpu_bitmask = 0x1c0000,
-	.check_cpus = true,
+	.tester4.vpu_bitmask = 0x1c0000,
+	.tester4.cpu_bitmask = 0x3,
 };
 
 static struct imx_ocotp_data imx8mm_ocotp_data = {
@@ -1008,8 +1008,8 @@ static struct imx_ocotp_data imx8mm_ocotp_data = {
 };
 
 static struct imx8m_featctrl_data imx8mn_featctrl_data = {
-	.gpu_bitmask = 0x1000000,
-	.check_cpus = true,
+	.tester4.gpu_bitmask = 0x1000000,
+	.tester4.cpu_bitmask = 0x3,
 };
 
 static struct imx_ocotp_data imx8mn_ocotp_data = {
diff --git a/drivers/soc/imx/imx8m-featctrl.c b/drivers/soc/imx/imx8m-featctrl.c
index 9a2b66555dce..23a3f990160d 100644
--- a/drivers/soc/imx/imx8m-featctrl.c
+++ b/drivers/soc/imx/imx8m-featctrl.c
@@ -33,6 +33,19 @@ static inline bool is_fused(u32 val, u32 bitmask)
 	return bitmask && (val & bitmask) == bitmask;
 }
 
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+
+static void check_cpus(u32 mask, u32 reg, unsigned long *features)
+{
+	switch (field_get(mask, reg)) {
+	case 0b11:
+		clear_bit(IMX8M_FEAT_CPU_DUAL, features);
+		fallthrough;
+	case 0b10:
+		clear_bit(IMX8M_FEAT_CPU_QUAD, features);
+	}
+}
+
 int imx8m_feat_ctrl_init(struct device *dev, u32 tester4,
 			 const struct imx8m_featctrl_data *data)
 {
@@ -49,24 +62,17 @@ int imx8m_feat_ctrl_init(struct device *dev, u32 tester4,
 
 	bitmap_fill(features, IMX8M_FEAT_END);
 
-	if (is_fused(tester4, data->vpu_bitmask))
+	if (is_fused(tester4, data->tester4.vpu_bitmask))
 		clear_bit(IMX8M_FEAT_VPU, features);
-	if (is_fused(tester4, data->gpu_bitmask))
+	if (is_fused(tester4, data->tester4.gpu_bitmask))
 		clear_bit(IMX8M_FEAT_GPU, features);
-	if (is_fused(tester4, data->mipi_dsi_bitmask))
+	if (is_fused(tester4, data->tester4.mipi_dsi_bitmask))
 		clear_bit(IMX8M_FEAT_MIPI_DSI, features);
-	if (is_fused(tester4, data->isp_bitmask))
+	if (is_fused(tester4, data->tester4.isp_bitmask))
 		clear_bit(IMX8M_FEAT_ISP, features);
 
-	if (data->check_cpus) {
-		switch (tester4 & 3) {
-		case 0b11:
-			clear_bit(IMX8M_FEAT_CPU_DUAL, features);
-			fallthrough;
-		case 0b10:
-			clear_bit(IMX8M_FEAT_CPU_QUAD, features);
-		}
-	}
+	if (data->tester4.cpu_bitmask)
+		check_cpus(data->tester4.cpu_bitmask, tester4, features);
 
 	priv->feat.dev = dev;
 	priv->feat.check = imx8m_feat_check;
diff --git a/include/soc/imx8m/featctrl.h b/include/soc/imx8m/featctrl.h
index 91d14bc68c0a..cfbc3fad80f4 100644
--- a/include/soc/imx8m/featctrl.h
+++ b/include/soc/imx8m/featctrl.h
@@ -7,11 +7,13 @@
 #include <linux/types.h>
 
 struct imx8m_featctrl_data {
-	u32 vpu_bitmask;
-	u32 gpu_bitmask;
-	u32 mipi_dsi_bitmask;
-	u32 isp_bitmask;
-	bool check_cpus;
+	struct {
+		u32 vpu_bitmask;
+		u32 gpu_bitmask;
+		u32 mipi_dsi_bitmask;
+		u32 isp_bitmask;
+		u32 cpu_bitmask;
+	} tester4;
 };
 
 struct device;
-- 
2.39.2

[PATCH 3/3] soc: imx: featctrl: finalize support for i.MX8MP

[Ahmad Fatoum]

We only had preliminary feature controller support for i.MX8MP and
support for detecting missing VPU, DSP, NPU, LVDS and CPUs was missing.

Add support for them, so barebox may fix up the kernel device tree to
disable these nodes. This is especially important for the VPU and NPU as
the kernel's blk-ctrl power domain driver may try to power them down as
they are unused, which would make the SoC hang.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/dts/imx8mp.dtsi             | 54 +++++++++++++++++++++++++++-
 drivers/nvmem/ocotp.c                | 13 +++++--
 drivers/soc/imx/imx8m-featctrl.c     | 17 ++++++---
 include/dt-bindings/features/imx8m.h |  5 ++-
 include/soc/imx8m/featctrl.h         | 11 ++++--
 5 files changed, 90 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 6af9d3924ac6..3eb3c7a5dfa5 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -21,8 +21,12 @@ aliases {
  * The DSP reserved memory will collide with the Barebox malloc area for some
  * DRAM sizes, even though the DSP itself is disabled in most configurations.
  */
-/delete-node/ &dsp;
 /delete-node/ &dsp_reserved;
+&dsp {
+	barebox,feature-gates = <&feat IMX8M_FEAT_DSP>;
+	/delete-property/ memory-region;
+	status = "disabled";
+};
 
 &edacmc {
 	compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
@@ -53,6 +57,14 @@ &pgc_mipi_phy2 {
 	barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
 };
 
+&mipi_dsi {
+	barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
+};
+
+&lcdif1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
+};
+
 &pgc_ispdwp {
 	barebox,feature-gates = <&feat IMX8M_FEAT_ISP>;
 };
@@ -64,3 +76,43 @@ &gpu3d {
 &gpu2d {
 	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
 };
+
+&pgc_vpumix {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_vc8000e {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_g1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_g2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpumix_blk_ctrl {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_mlmix {
+	barebox,feature-gates = <&feat IMX8M_FEAT_NPU>;
+};
+
+&lcdif2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_LVDS>;
+};
+
+&lvds_bridge {
+	barebox,feature-gates = <&feat IMX8M_FEAT_LVDS>;
+};
diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index ccdc8a417ed1..28c121152e8b 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -736,7 +736,7 @@ static int imx_ocotp_init_dt(struct ocotp_priv *priv)
 	char mac[MAC_BYTES];
 	const __be32 *prop;
 	struct device_node *node = priv->dev.parent->of_node;
-	u32 tester4;
+	u32 tester3, tester4;
 	int ret, len = 0;
 
 	if (!node)
@@ -764,11 +764,15 @@ static int imx_ocotp_init_dt(struct ocotp_priv *priv)
 	if (!of_property_read_bool(node, "barebox,feature-controller"))
 		return 0;
 
+	ret = regmap_read(priv->map, OCOTP_OFFSET_TO_ADDR(0x440), &tester3);
+	if (ret != 0)
+		return ret;
+
 	ret = regmap_read(priv->map, OCOTP_OFFSET_TO_ADDR(0x450), &tester4);
 	if (ret != 0)
 		return ret;
 
-	return imx8m_feat_ctrl_init(priv->dev.parent, tester4, priv->data->feat);
+	return imx8m_feat_ctrl_init(priv->dev.parent, tester3, tester4, priv->data->feat);
 }
 
 static void imx_ocotp_set_unique_machine_id(void)
@@ -959,9 +963,14 @@ static struct imx_ocotp_data vf610_ocotp_data = {
 };
 
 static struct imx8m_featctrl_data imx8mp_featctrl_data = {
+	.tester3.cpu_bitmask = 0xc0000,
+	.tester3.vpu_bitmask = 0x43000000,
+	.tester4.npu_bitmask = 0x8,
 	.tester4.gpu_bitmask = 0xc0,
 	.tester4.mipi_dsi_bitmask = 0x60000,
+	.tester4.lvds_bitmask = 0x180000,
 	.tester4.isp_bitmask = 0x3,
+	.tester4.dsp_bitmask = 0x10,
 };
 
 static struct imx_ocotp_data imx8mp_ocotp_data = {
diff --git a/drivers/soc/imx/imx8m-featctrl.c b/drivers/soc/imx/imx8m-featctrl.c
index 23a3f990160d..31579aff7ef4 100644
--- a/drivers/soc/imx/imx8m-featctrl.c
+++ b/drivers/soc/imx/imx8m-featctrl.c
@@ -46,7 +46,7 @@ static void check_cpus(u32 mask, u32 reg, unsigned long *features)
 	}
 }
 
-int imx8m_feat_ctrl_init(struct device *dev, u32 tester4,
+int imx8m_feat_ctrl_init(struct device *dev, u32 tester3, u32 tester4,
 			 const struct imx8m_featctrl_data *data)
 {
 	unsigned long *features;
@@ -55,14 +55,15 @@ int imx8m_feat_ctrl_init(struct device *dev, u32 tester4,
 	if (!dev || !data)
 		return -ENODEV;
 
-	dev_dbg(dev, "tester4 = 0x%08x\n", tester4);
+	dev_dbg(dev, "tester3 = 0x%08x, tester4 = 0x%08x\n", tester3, tester4);
 
 	priv = xzalloc(sizeof(*priv));
 	features = priv->features;
 
 	bitmap_fill(features, IMX8M_FEAT_END);
 
-	if (is_fused(tester4, data->tester4.vpu_bitmask))
+	if (is_fused(tester3, data->tester3.vpu_bitmask) ||
+	    is_fused(tester4, data->tester4.vpu_bitmask))
 		clear_bit(IMX8M_FEAT_VPU, features);
 	if (is_fused(tester4, data->tester4.gpu_bitmask))
 		clear_bit(IMX8M_FEAT_GPU, features);
@@ -70,8 +71,16 @@ int imx8m_feat_ctrl_init(struct device *dev, u32 tester4,
 		clear_bit(IMX8M_FEAT_MIPI_DSI, features);
 	if (is_fused(tester4, data->tester4.isp_bitmask))
 		clear_bit(IMX8M_FEAT_ISP, features);
+	if (is_fused(tester4, data->tester4.npu_bitmask))
+		clear_bit(IMX8M_FEAT_NPU, features);
+	if (is_fused(tester4, data->tester4.lvds_bitmask))
+		clear_bit(IMX8M_FEAT_LVDS, features);
+	if (is_fused(tester4, data->tester4.dsp_bitmask))
+		clear_bit(IMX8M_FEAT_DSP, features);
 
-	if (data->tester4.cpu_bitmask)
+	if (data->tester3.cpu_bitmask)
+		check_cpus(data->tester3.cpu_bitmask, tester3, features);
+	else if (data->tester4.cpu_bitmask)
 		check_cpus(data->tester4.cpu_bitmask, tester4, features);
 
 	priv->feat.dev = dev;
diff --git a/include/dt-bindings/features/imx8m.h b/include/dt-bindings/features/imx8m.h
index e1ed40413ca2..ff063257b74a 100644
--- a/include/dt-bindings/features/imx8m.h
+++ b/include/dt-bindings/features/imx8m.h
@@ -10,7 +10,10 @@
 #define IMX8M_FEAT_GPU		4
 #define IMX8M_FEAT_MIPI_DSI	5
 #define IMX8M_FEAT_ISP		6
+#define IMX8M_FEAT_NPU		7
+#define IMX8M_FEAT_LVDS		8
+#define IMX8M_FEAT_DSP		9
 
-#define IMX8M_FEAT_END		7
+#define IMX8M_FEAT_END		10
 
 #endif
diff --git a/include/soc/imx8m/featctrl.h b/include/soc/imx8m/featctrl.h
index cfbc3fad80f4..380e417778df 100644
--- a/include/soc/imx8m/featctrl.h
+++ b/include/soc/imx8m/featctrl.h
@@ -7,22 +7,29 @@
 #include <linux/types.h>
 
 struct imx8m_featctrl_data {
+	struct {
+		u32 vpu_bitmask;
+		u32 cpu_bitmask;
+	} tester3;
 	struct {
 		u32 vpu_bitmask;
 		u32 gpu_bitmask;
 		u32 mipi_dsi_bitmask;
 		u32 isp_bitmask;
 		u32 cpu_bitmask;
+		u32 npu_bitmask;
+		u32 lvds_bitmask;
+		u32 dsp_bitmask;
 	} tester4;
 };
 
 struct device;
 
 #ifdef CONFIG_IMX8M_FEATCTRL
-int imx8m_feat_ctrl_init(struct device *dev, u32 tester4,
+int imx8m_feat_ctrl_init(struct device *dev, u32 tester3, u32 tester4,
 			 const struct imx8m_featctrl_data *data);
 #else
-static inline int imx8m_feat_ctrl_init(struct device *dev, u32 tester4,
+static inline int imx8m_feat_ctrl_init(struct device *dev, u32 tester3, u32 tester4,
 				       const struct imx8m_featctrl_data *data)
 {
 	return -ENODEV;
-- 
2.39.2

Re: [PATCH 0/3] soc: imx: featctrl: finalize support for i.MX8MP

[Sascha Hauer]

On Fri, 19 Jan 2024 23:45:19 +0100, Ahmad Fatoum wrote:
> We only had preliminary feature controller support for i.MX8MP and
> support for detecting missing VPU, DSP, NPU, LVDS and CPUs was missing.
> 
> Add support for them, so barebox may fix up the kernel device tree to
> disable these nodes. This is especially important for the VPU and NPU as
> the kernel's blk-ctrl power domain driver may try to power them down as
> they are unused, which would make the SoC hang.
> 
> [...]

Applied, thanks!

[1/3] soc: imx: imx8m-featctrl: make header self-contained
      https://git.pengutronix.de/cgit/barebox/commit/?id=e21b25c8210e (link may not be stable)
[2/3] nvmem: ocotp: prepare adding tester3 support
      https://git.pengutronix.de/cgit/barebox/commit/?id=897ca1a97280 (link may not be stable)
[3/3] soc: imx: featctrl: finalize support for i.MX8MP
      https://git.pengutronix.de/cgit/barebox/commit/?id=aaea50bbcde2 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>

Re: [PATCH 2/3] nvmem: ocotp: prepare adding tester3 support

[Sascha Hauer]

On Fri, Jan 19, 2024 at 11:45:21PM +0100, Ahmad Fatoum wrote:
> The tester fuses are written to the OCOTP by NXP during production.
> So far, we only evaluated tester4 to determine which peripherals
> are missing from the SoC. On the i.MX8MP, VPU and CPUs existence is
> instead encoded into the tester3 fuse word. In preparation for adding
> support for tester4, rename the existing masks to be tester4-specific.
> 
> diff --git a/drivers/soc/imx/imx8m-featctrl.c b/drivers/soc/imx/imx8m-featctrl.c
> index 9a2b66555dce..23a3f990160d 100644
> --- a/drivers/soc/imx/imx8m-featctrl.c
> +++ b/drivers/soc/imx/imx8m-featctrl.c
> @@ -33,6 +33,19 @@ static inline bool is_fused(u32 val, u32 bitmask)
>  	return bitmask && (val & bitmask) == bitmask;
>  }
>  
> +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))

It's likely time to find a common place for this. We already have that
defined in drivers/clk/at91/pmc.h and the kernel also has this defined
three times.

Sascha


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