[PATCH master 2/4] ARM: socfpga: populate HANDOFF_FPGA2SDR with Quartus value

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

The Terasic DE10-Nano is the only upstream board that has a non-zero
value for CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST in the headers generated by
Quartus. Yet, barebox ignored this value, with the effect that either:

  - The Linux bridge driver reads a zero value from the handoff3 register
    and keeps all fpga2sdram ports in reset

  - The barebox bridge driver uses its hardcoded mask of 0x3fff, when
    the bridge is enabled, which is different than the Quartus value
    of 0x1FF.

Fix the first point by populating the handoff3 register, so an enabled
Linux driver can enable the correct ports. A fix for barebox configurations
with CONFIG_SOCFPGA_FPGA_BRIDGE=y follows in the follow-up commit.

Cc: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 include/mach/socfpga/cyclone5-sdram-config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/mach/socfpga/cyclone5-sdram-config.h b/include/mach/socfpga/cyclone5-sdram-config.h
index 06f06ef5d78f..2abef7f31121 100644
--- a/include/mach/socfpga/cyclone5-sdram-config.h
+++ b/include/mach/socfpga/cyclone5-sdram-config.h
@@ -155,6 +155,9 @@ static inline void socfpga_sdram_mmr_init(void)
 		CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << SDR_CTRLGRP_DRAMODT_WRITE_LSB;
 	sdram_write(SDR_CTRLGRP_DRAMODT_ADDRESS, val);
 
+	val = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST;
+	writel(val, ISWGRP_HANDOFF_FPGA2SDR);
+
 	val = readl(CYCLONE5_SDR_ADDRESS + SDR_CTRLGRP_STATICCFG_ADDRESS);
 	val &= ~(SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK);
 	val |= 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB;
-- 
2.39.2