From mboxrd@z Thu Jan 1 00:00:00 1970 Delivery-date: Tue, 25 Jun 2024 10:20:37 +0200 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by lore.white.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1sM1Pp-00BvIO-0Q for lore@lore.pengutronix.de; Tue, 25 Jun 2024 10:20:37 +0200 Received: from bombadil.infradead.org ([2607:7c80:54:3::133]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1sM1Po-0000bR-6j for lore@pengutronix.de; Tue, 25 Jun 2024 10:20:37 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tk5gaAbJFMkhdXOOfx/41uqcEcqlrR9gRgjY0e+2kVc=; b=0SEUCiyJuTXZlPlU/RcxGjjjCb XCxSq1PNjACdZbpPkNM6Ggn1/Q4OzNWspvl+7VldTC33L5PXMK32ir9PaAABSC0Bobf0jh3xBtJuf gtCZ6P1seVdpvYm4Stil+rQZ9+5eRv6Gp7ZN+ISMDL/UdEwPJW572IRdS80cF0OtxDQMeFsN0JFRM G/f7GoQT7Fk1Xme8YCDErIDa6WptUug/1Hw+rsDmzhl7i0XVqDTlTI+1yyogCnMFZSwfg6Ezb7rRY gWZbZQWO4FIvJrRRhO3FADA0sAo/SnkOCsWz0iC/zW8D7+aCUf3YuSaC5x70CGuermcLAjkXVIupD oOpT+NTQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sM1PE-000000025J3-0dkD; Tue, 25 Jun 2024 08:20:00 +0000 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sM1PB-000000025If-2hpb for barebox@lists.infradead.org; Tue, 25 Jun 2024 08:19:58 +0000 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1sM1PA-0000We-Dm; Tue, 25 Jun 2024 10:19:56 +0200 Received: from [2a0a:edc0:2:b01:1d::c5] (helo=pty.whiteo.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sM1PA-004qWb-1G; Tue, 25 Jun 2024 10:19:56 +0200 Received: from mfe by pty.whiteo.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1sM1P9-00E3bs-36; Tue, 25 Jun 2024 10:19:55 +0200 Date: Tue, 25 Jun 2024 10:19:55 +0200 From: Marco Felsch To: Sascha Hauer Cc: barebox@lists.infradead.org Message-ID: <20240625081955.bheuv4xw3owosqv2@pengutronix.de> References: <20240613130659.165278-1-m.felsch@pengutronix.de> <20240613130659.165278-2-m.felsch@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240625_011957_711917_7E84EEF0 X-CRM114-Status: GOOD ( 29.07 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.2 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH v2 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) On 24-06-17, Sascha Hauer wrote: > On Thu, Jun 13, 2024 at 03:06:59PM +0200, Marco Felsch wrote: > > This ports U-Boot commit: > > > > | commit 2f3c92060dcd6bc9cfd3e2e344a3e1745ca39f09 > > | Author: Peng Fan > > | Date: Thu Jul 9 13:39:26 2020 +0800 > > | > > | imx8m: workaround ROM serror > > | > > | ROM SError happens on two cases: > > | > > | 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but > > | when ROM patch lock is fused, this write will cause SError. > > | > > | 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB > > | is field return mode, but the last 4K of ROM is still protected and cause > > | SError. > > | > > | Since ROM mask SError until ATF unmask it, so then ATF always meets the > > | exception. This patch works around the issue in SPL by enabling SPL > > | Exception vectors table and the SError exception, take the exception > > | to eret immediately to clear the SError. > > | > > | Signed-off-by: Ye Li > > | Signed-off-by: Peng Fan > > > > Other than U-Boot we don't support exceptions in PBL and therefore we > > can handle it simpler by installing an dummy exception table to handle > > the pending exception. Later on the TF-A overrides the dummy table. > > > > Signed-off-by: Marco Felsch > > --- > > v2: > > - Adapt the Makefile > > - Drop the ifdef guard from the errata.h > > - Make use of runtime_address() to apply the erratum always during soc > > lowlevel init. > > > > arch/arm/mach-imx/Makefile | 2 ++ > > arch/arm/mach-imx/cpu_init.c | 12 ++++++- > > arch/arm/mach-imx/errata.c | 24 +++++++++++++ > > arch/arm/mach-imx/imx8m_early_exceptions.S | 42 ++++++++++++++++++++++ > > include/mach/imx/errata.h | 8 +++++ > > 5 files changed, 87 insertions(+), 1 deletion(-) > > create mode 100644 arch/arm/mach-imx/errata.c > > create mode 100644 arch/arm/mach-imx/imx8m_early_exceptions.S > > create mode 100644 include/mach/imx/errata.h > > > > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > > index cfd066c69de9..22ea48a83330 100644 > > --- a/arch/arm/mach-imx/Makefile > > +++ b/arch/arm/mach-imx/Makefile > > @@ -34,6 +34,8 @@ obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o > > pbl-$(CONFIG_USB_GADGET_DRIVER_ARC_PBL) += imx-udc.o > > obj-$(CONFIG_RESET_IMX_SRC) += src.o > > lwl-y += cpu_init.o > > +lwl-y += errata.o > > +lwl-$(CONFIG_ARCH_IMX8M) += imx8m_early_exceptions.o > > pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o > > pbl-y += xload-qspi.o > > obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o > > diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c > > index c5a47d9b9154..aebbd3defaec 100644 > > --- a/arch/arm/mach-imx/cpu_init.c > > +++ b/arch/arm/mach-imx/cpu_init.c > > @@ -6,6 +6,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -75,17 +76,26 @@ void imx8mm_cpu_lowlevel_init(void) > > imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); > > > > imx8m_cpu_lowlevel_init(); > > + > > + erratum_050350_imx8m(); > > } > > > > void imx8mn_cpu_lowlevel_init(void) > > __alias(imx8mm_cpu_lowlevel_init); > > > > void imx8mp_cpu_lowlevel_init(void) > > - __alias(imx8mm_cpu_lowlevel_init); > > +{ > > + /* ungate system counter */ > > + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_SCTR); > > + > > + imx8m_cpu_lowlevel_init(); > > +} > > > > void imx8mq_cpu_lowlevel_init(void) > > { > > imx8m_cpu_lowlevel_init(); > > + > > + erratum_050350_imx8m(); > > } > > > > #define CCM_AUTHEN_TZ_NS BIT(9) > > diff --git a/arch/arm/mach-imx/errata.c b/arch/arm/mach-imx/errata.c > > new file mode 100644 > > index 000000000000..afab08667879 > > --- /dev/null > > +++ b/arch/arm/mach-imx/errata.c > > @@ -0,0 +1,24 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > + > > +#include > > +#include > > +#include > > + > > +#ifdef CONFIG_CPU_V8 > > + > > +extern char early_imx8m_vectors[]; > > + > > +void erratum_050350_imx8m(void) > > +{ > > + void *addr; > > + > > + if (current_el() != 3) > > + return; > > + > > + addr = runtime_address(early_imx8m_vectors); > > + > > + asm volatile("msr vbar_el3, %0" : : "r" (addr) : "cc"); > > + asm volatile("msr daifclr, #4;isb"); > > +} > > + > > +#endif /* CONFIG_CPU_V8 */ > > diff --git a/arch/arm/mach-imx/imx8m_early_exceptions.S b/arch/arm/mach-imx/imx8m_early_exceptions.S > > new file mode 100644 > > index 000000000000..cd91e1a07b9c > > --- /dev/null > > +++ b/arch/arm/mach-imx/imx8m_early_exceptions.S > > @@ -0,0 +1,42 @@ > > +/* > > + * (C) Copyright 2013 > > + * David Feng > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include > > + > > +#ifdef CONFIG_CPU_V8 > > This file is compiled only when CONFIG_ARCH_IMX8M is enabled. This > options selects CONFIG_CPU_V8 which makes this #ifdef unnecessary. Of course. > Dropped while applying. Thank you. Regards, Marco