[RFT PATCH master] ARM: Rockchip: call arm_cpu_lowlevel_init() in EL2/EL1

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

The TF-A blob in RKBIN seems to initialize use of NEON and the crypto
extensions for lower exception levels. Using the now available upstream
TF-A doesn't seem to do this with the result that enabling the
CONFIG_DIGEST_SHA256_ARM64_CE and CONFIG_DIGEST_SHA1_ARM64_CE options
can lead to crashes:

  Unknown/Uncategorized exception (ESR 0x02000000) at 0xbf96b7282ba34bf3
  elr: 00000000efd7da48 lr : 00000000efd7d7e0
  x0 : 00000000afdc1b10 x1 : 00000000afdc1b70
  x2 : 0000000000000000 x3 : 0000000000000020
  x4 : 0000000000000000 x5 : 00000000efff7dd8
  x6 : 00000000ca62c1d6 x7 : 0000000000000000
  x8 : 00000000afdc1b68 x9 : 0000000000000000
  x10: 0000000000000000 x11: 00000000fffffff6
  x12: 00000000fffffff6 x13: 0000000000000020
  x14: 0000000000000000 x15: 0000000000000003
  x16: 00000000efff7968 x17: 0000000000000003
  x18: 00000000efff7ef0 x19: 0000000000000001
  x20: 00000000afdc1b30 x21: 00000000afdc1b10
  x22: 00000000afdc1b30 x23: 00000000ef600000
  x24: 0000000000b35a40 x25: 0000000000080051
  x26: 0000000000106858 x27: 00000000effe0000
  x28: 0000000000000000 x29: 00000000efff7e40

  Call trace:
  [<efd7da48>] (sha1_ce_transform+0x64/0x224) from [<efd7d8b0>]
  (sha1_ce_final+0xbc/0x114)
  [<efd7d8b0>] (sha1_ce_final+0xbc/0x114) from [<efd0297c>]
  (machine_id_set_globalvar+0x7c/0x100)
  [<efd0297c>] (machine_id_set_globalvar+0x7c/0x100) from [<efd01adc>]
  (start_barebox+0x60/0x8c)
  [<efd01adc>] (start_barebox+0x60/0x8c) from [<efd7bf1c>]
  (barebox_non_pbl_start+0x11c/0x150)
  [<efd7bf1c>] (barebox_non_pbl_start+0x11c/0x150) from [<efd0000c>]
  (__bare_init_start+0x0/0x14)
  [<efd0000c>] (__bare_init_start+0x0/0x14) from [<00b01d8c>] (0xb01d8c)
  [<00b01d8c>] (0xb01d8c) from [<00b01640>] (0xb01640)
  panic: unhandled exception
  ### ERROR ### Please RESET the board ###

Fix this by calling arm_cpu_lowlevel_init() outside EL3 as well.

Link: https://lore.barebox.org/barebox/CAP1tNvS2DWF-xLSCe0y1kib_kOSrdkWPJC6bGm+7Yuv7wxJ3tA@mail.gmail.com/
Reported-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
Untested, @Alxander, can you give this a go?
---
 arch/arm/mach-rockchip/atf.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
index eaba209ff32d..bc47c64078f7 100644
--- a/arch/arm/mach-rockchip/atf.c
+++ b/arch/arm/mach-rockchip/atf.c
@@ -134,6 +134,9 @@ void __noreturn rk3588_barebox_entry(void *fdt)
                 */
                rk3588_atf_load_bl31(NULL);
                /* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
+       } else {
+	       /* TF-A may not have enabled SIMD for lower exception levels */
+	       arm_cpu_lowlevel_init();
        }
 
        barebox_arm_entry(membase, memsize, fdt);
-- 
2.39.2