[PATCH 11/12] ARM: dts: Rockchip rk3588: add HDMI node

[Sascha Hauer <s.hauer@pengutronix.de>]

Add the HDMI node locally until the node hits the upstream dts file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/rk3588-rock-5b.dts | 43 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/dts/rk3588.dtsi        | 42 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 85 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts
index 0af5442870..0abb25f098 100644
--- a/arch/arm/dts/rk3588-rock-5b.dts
+++ b/arch/arm/dts/rk3588-rock-5b.dts
@@ -6,6 +6,7 @@
 #include "rk3588.dtsi"
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 
 / {
 	aliases {
@@ -25,6 +26,17 @@ environment-sd {
 			status = "disabled";
 		};
 	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
 };
 
 &sdhci {
@@ -76,3 +88,34 @@ &usb_host1_ehci {
 	/* Does not work in barebox (missing phy driver) */
 	status = "disabled";
 };
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
index 0aef30eaff..8fed50a5df 100644
--- a/arch/arm/dts/rk3588.dtsi
+++ b/arch/arm/dts/rk3588.dtsi
@@ -4,4 +4,46 @@
 #include "rk3588s.dtsi"
 
 / {
+	hdmi0: hdmi@fde80000 {
+		compatible = "rockchip,rk3588-dw-hdmi-qp";
+		reg = <0x0 0xfde80000 0x0 0x20000>;
+		assigned-clocks = <&cru ACLK_HDCP1_ROOT>;
+		assigned-clock-parents = <&cru PLL_GPLL>;
+		clocks = <&cru PCLK_HDMITX0>,
+				<&cru CLK_HDMITX0_EARC>,
+				<&cru CLK_HDMITX0_REF>,
+				<&cru MCLK_I2S5_8CH_TX>,
+				<&cru CLK_HDMIHDP0>,
+				<&cru HCLK_VO1>;
+		clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+				<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+				<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+				<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+				<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "avp", "cec", "earc", "main", "hpd";
+		phys = <&hdptxphy_hdmi0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+				&hdmim0_tx0_scl &hdmim0_tx0_sda>;
+		power-domains = <&power RK3588_PD_VO1>;
+		resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+		reset-names = "ref", "hdp";
+		rockchip,grf = <&sys_grf>;
+		rockchip,vo-grf = <&vo1_grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hdmi0_in: port@0 {
+				reg = <0>;
+			};
+
+			hdmi0_out: port@1 {
+				reg = <1>;
+			};
+		};
+	};
 };

-- 
2.39.5