* [PATCH v2 0/6] Initial support for Allwinner A64 SoC
@ 2025-01-07 14:37 Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 1/6] clk: divider: add error code propagation Jules Maselbas
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Jules Maselbas @ 2025-01-07 14:37 UTC (permalink / raw)
To: barebox; +Cc: Jules Maselbas
This series adds an initial support for Allwinner, currently only
targetting the Pine64+ board, based on the A64 SoC.
This first series is intented as a second boot image only, that can
be started from u-boot. This series provides the bare minimal for
barebox to load the next OS from sd/mmc.
The documentation patch could be ommited as it is more about using
barebox as a first and second stage bootloader, while this series
only works as a second boot image.
The main change in this V2 series is the new "one-size fit all"
clk driver only used right for the mmc0/mmc1/mmc2 clock source
(composite with a gate, a mux, two divs plus a fixed post-div).
Jules Maselbas (6):
clk: divider: add error code propagation
clk: Add clock driver for sun50i-a64
pinctrl: Add sun50i-a64 pinctrl driver
mci: Add sunxi-mmc driver
ARM: sunxi: Introduce mach-sunxi
Documentation: sunxi: Add some documentation
Documentation/boards/sunxi.rst | 132 +++++
arch/arm/Kconfig | 12 +
arch/arm/Makefile | 1 +
arch/arm/configs/sunxi_v8_defconfig | 12 +
arch/arm/mach-sunxi/Kconfig | 12 +
arch/arm/mach-sunxi/Makefile | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-divider.c | 5 +-
drivers/clk/sunxi/Makefile | 3 +
drivers/clk/sunxi/clk-sun50i-a64.c | 295 ++++++++++
drivers/clk/sunxi/clk-sun50i-a64.h | 62 +++
drivers/clk/sunxi/clk-sunxi.c | 348 ++++++++++++
drivers/clk/sunxi/clk-sunxi.h | 79 +++
drivers/mci/Kconfig | 6 +
drivers/mci/Makefile | 2 +
drivers/mci/sunxi-mmc-common.c | 246 +++++++++
drivers/mci/sunxi-mmc-pbl.c | 81 +++
drivers/mci/sunxi-mmc.c | 177 ++++++
drivers/mci/sunxi-mmc.h | 222 ++++++++
drivers/pinctrl/Kconfig | 2 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/sunxi/Kconfig | 13 +
drivers/pinctrl/sunxi/Makefile | 3 +
drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 594 +++++++++++++++++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 369 +++++++++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 224 ++++++++
include/mach/sunxi/xload.h | 12 +
27 files changed, 2914 insertions(+), 1 deletion(-)
create mode 100644 Documentation/boards/sunxi.rst
create mode 100644 arch/arm/configs/sunxi_v8_defconfig
create mode 100644 arch/arm/mach-sunxi/Kconfig
create mode 100644 arch/arm/mach-sunxi/Makefile
create mode 100644 drivers/clk/sunxi/Makefile
create mode 100644 drivers/clk/sunxi/clk-sun50i-a64.c
create mode 100644 drivers/clk/sunxi/clk-sun50i-a64.h
create mode 100644 drivers/clk/sunxi/clk-sunxi.c
create mode 100644 drivers/clk/sunxi/clk-sunxi.h
create mode 100644 drivers/mci/sunxi-mmc-common.c
create mode 100644 drivers/mci/sunxi-mmc-pbl.c
create mode 100644 drivers/mci/sunxi-mmc.c
create mode 100644 drivers/mci/sunxi-mmc.h
create mode 100644 drivers/pinctrl/sunxi/Kconfig
create mode 100644 drivers/pinctrl/sunxi/Makefile
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.h
create mode 100644 include/mach/sunxi/xload.h
--
2.47.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/6] clk: divider: add error code propagation
2025-01-07 14:37 [PATCH v2 0/6] Initial support for Allwinner A64 SoC Jules Maselbas
@ 2025-01-07 14:37 ` Jules Maselbas
2025-01-08 14:20 ` Ahmad Fatoum
2025-01-07 14:37 ` [PATCH v2 2/6] clk: Add clock driver for sun50i-a64 Jules Maselbas
` (4 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Jules Maselbas @ 2025-01-07 14:37 UTC (permalink / raw)
To: barebox; +Cc: Jules Maselbas
divider_get_val can return a negative error code and should not be used
as a valid divider.
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
---
v1->v2:
- changed value to int and removed ret variable (Ahmad)
drivers/clk/clk-divider.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index ccab70aecc..b0df34e858 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -307,7 +307,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct clk *clk = clk_hw_to_clk(hw);
struct clk_divider *divider = to_clk_divider(hw);
- unsigned int value;
+ int value;
u32 val;
if (divider->flags & CLK_DIVIDER_READ_ONLY)
@@ -322,6 +322,8 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
value = divider_get_val(rate, parent_rate, divider->table,
divider->width, divider->flags);
+ if (value < 0)
+ return value;
val = readl(divider->reg);
val &= ~(clk_div_mask(divider->width) << divider->shift);
--
2.47.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/6] clk: Add clock driver for sun50i-a64
2025-01-07 14:37 [PATCH v2 0/6] Initial support for Allwinner A64 SoC Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 1/6] clk: divider: add error code propagation Jules Maselbas
@ 2025-01-07 14:37 ` Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 3/6] pinctrl: Add sun50i-a64 pinctrl driver Jules Maselbas
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Jules Maselbas @ 2025-01-07 14:37 UTC (permalink / raw)
To: barebox; +Cc: Jules Maselbas
Adds a "one-size fit all" clock driver to be used for complex
"composite" clock, composed of: a gate, a mux and severals dividers.
This clk driver could be used to make SoC specific drivers easier
to port from linux sources, but this is not the case yet.
The pll-cpux is set to 816MHz and pll-periph0-2x is set to 1.2GHz.
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
---
v1->v2:
- adds a new "one-size fit all" clock driver
drivers/clk/Makefile | 1 +
drivers/clk/sunxi/Makefile | 3 +
drivers/clk/sunxi/clk-sun50i-a64.c | 295 ++++++++++++++++++++++++
drivers/clk/sunxi/clk-sun50i-a64.h | 62 +++++
drivers/clk/sunxi/clk-sunxi.c | 348 +++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.h | 79 +++++++
6 files changed, 788 insertions(+)
create mode 100644 drivers/clk/sunxi/Makefile
create mode 100644 drivers/clk/sunxi/clk-sun50i-a64.c
create mode 100644 drivers/clk/sunxi/clk-sun50i-a64.h
create mode 100644 drivers/clk/sunxi/clk-sunxi.c
create mode 100644 drivers/clk/sunxi/clk-sunxi.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 764539e91e..7d459c298e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -31,3 +31,4 @@ obj-y += bcm/
obj-$(CONFIG_COMMON_CLK_SCMI) += clk-scmi.o
obj-$(CONFIG_COMMON_CLK_GPIO) += clk-gpio.o
obj-$(CONFIG_TI_SCI_CLK) += ti-sci-clk.o
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
new file mode 100644
index 0000000000..1c2214a2bc
--- /dev/null
+++ b/drivers/clk/sunxi/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += clk-sunxi.o
+obj-$(CONFIG_ARCH_SUN50I_A64) += clk-sun50i-a64.o
diff --git a/drivers/clk/sunxi/clk-sun50i-a64.c b/drivers/clk/sunxi/clk-sun50i-a64.c
new file mode 100644
index 0000000000..962f3fe671
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun50i-a64.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2022 Jules Maselbas
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include "clk-sunxi.h"
+
+#define MHZ (1000UL * 1000UL)
+
+#include "clk-sun50i-a64.h"
+
+#define CCU_PLL_CPUX 0x00
+#define CCU_PLL_PERIPH0 0x28
+#define CCU_CPUX_AXI_CFG 0x50
+
+static struct clk *clks[CLK_NUMBER];
+static struct clk_onecell_data clk_data = {
+ .clks = clks,
+ .clk_num = ARRAY_SIZE(clks),
+};
+
+static struct clk_div_table div_apb1[] = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 8 },
+ { /* Sentinel */ },
+};
+
+static const char *sel_cpux[] = {
+ "osc32k",
+ "osc24M",
+ "pll-cpux",
+};
+
+static const char *sel_ahb1[] = {
+ "osc32k",
+ "osc24M",
+ "axi",
+ "pll-periph0",
+};
+
+static const char *sel_apb2[] = {
+ "osc32k",
+ "osc24M",
+ "pll-periph0-2x",
+ "pll-periph0-2x",
+};
+
+static const char *sel_ahb2[] = {
+ "ahb1",
+ "pll-periph0",
+};
+
+static const char *sel_mmc[] = {
+ "osc24M",
+ "pll-periph0-2x",
+ "pll-periph1-2x",
+};
+
+static void sun50i_a64_resets_init(void __iomem *regs)
+{
+ u32 rst;
+
+ rst = 0 |
+ /* RST_USB_PHY0 */ BIT(0) |
+ /* RST_USB_PHY1 */ BIT(1) |
+ /* RST_USB_HSIC */ BIT(2);
+ writel(rst, regs + 0x0cc);
+
+ rst = 0 |
+ /* RST_BUS_MIPI_DSI */ BIT(1) |
+ /* RST_BUS_CE */ BIT(5) |
+ /* RST_BUS_DMA */ BIT(6) |
+ /* RST_BUS_MMC0 */ BIT(8) |
+ /* RST_BUS_MMC1 */ BIT(9) |
+ /* RST_BUS_MMC2 */ BIT(10) |
+ /* RST_BUS_NAND */ BIT(13) |
+ /* RST_BUS_DRAM */ BIT(14) |
+ /* RST_BUS_EMAC */ BIT(17) |
+ /* RST_BUS_TS */ BIT(18) |
+ /* RST_BUS_HSTIMER */ BIT(19) |
+ /* RST_BUS_SPI0 */ BIT(20) |
+ /* RST_BUS_SPI1 */ BIT(21) |
+ /* RST_BUS_OTG */ BIT(23) |
+ /* RST_BUS_EHCI0 */ BIT(24) |
+ /* RST_BUS_EHCI1 */ BIT(25) |
+ /* RST_BUS_OHCI0 */ BIT(28) |
+ /* RST_BUS_OHCI1 */ BIT(29);
+ writel(rst, regs + 0x2c0);
+
+ rst = 0 |
+ /* RST_BUS_VE */ BIT(0) |
+ /* RST_BUS_TCON0 */ BIT(3) |
+ /* RST_BUS_TCON1 */ BIT(4) |
+ /* RST_BUS_DEINTERLACE */ BIT(5) |
+ /* RST_BUS_CSI */ BIT(8) |
+ /* RST_BUS_HDMI0 */ BIT(10) |
+ /* RST_BUS_HDMI1 */ BIT(11) |
+ /* RST_BUS_DE */ BIT(12) |
+ /* RST_BUS_GPU */ BIT(20) |
+ /* RST_BUS_MSGBOX */ BIT(21) |
+ /* RST_BUS_SPINLOCK */ BIT(22) |
+ /* RST_BUS_DBG */ BIT(31);
+ writel(rst, regs + 0x2c4);
+
+ rst = /* RST_BUS_LVDS */ BIT(0);
+ writel(rst, regs + 0x2c8);
+
+ rst = 0 |
+ /* RST_BUS_CODEC */ BIT(0) |
+ /* RST_BUS_SPDIF */ BIT(1) |
+ /* RST_BUS_THS */ BIT(8) |
+ /* RST_BUS_I2S0 */ BIT(12) |
+ /* RST_BUS_I2S1 */ BIT(13) |
+ /* RST_BUS_I2S2 */ BIT(14);
+ writel(rst, regs + 0x2d0);
+
+ rst = 0 |
+ /* RST_BUS_I2C0 */ BIT(0) |
+ /* RST_BUS_I2C1 */ BIT(1) |
+ /* RST_BUS_I2C2 */ BIT(2) |
+ /* RST_BUS_SCR */ BIT(5) |
+ /* RST_BUS_UART0 */ BIT(16) |
+ /* RST_BUS_UART1 */ BIT(17) |
+ /* RST_BUS_UART2 */ BIT(18) |
+ /* RST_BUS_UART3 */ BIT(19) |
+ /* RST_BUS_UART4 */ BIT(20);
+ writel(rst, regs + 0x2d8);
+}
+
+static inline void sunxi_clk_set_pll(void __iomem *reg, u32 src, u32 freq)
+{
+ /* NOTE: using u32, max freq is 4GHz
+ * out freq: src * N * K
+ * factor N: [1->32]
+ * factor K: [1->4]
+ * from the manual: give priority to the choice of K >= 2
+ */
+ u32 mul = freq / src; /* target multiplier (N * K) */
+ u32 k, n;
+ u32 cfg = BIT(31); /* ENABLE */
+
+ for (k = 4; k > 1; k--) {
+ if ((mul % k) == 0)
+ break;
+ }
+ n = mul / k;
+
+ cfg |= (k - 1) << 4;
+ cfg |= (n - 1) << 8;
+
+ writel(cfg, reg);
+
+ /* wait for pll lock */
+ while (!(readl(reg) & BIT(28)));
+}
+
+static void sun50i_a64_clocks_init(void __iomem *regs)
+{
+ /* switch cpu clock source to osc-24M */
+ writel(0x10000, regs + CCU_CPUX_AXI_CFG);
+ /* wait 8 cycles */
+ nop_delay(8);
+ /* set pll-cpux to 816MHz */
+ sunxi_clk_set_pll(regs + CCU_PLL_CPUX, 24 * MHZ, 816 * MHZ);
+ nop_delay(10000); /* HACK: ~1ms delay */
+ /* switch cpu clock source to pll-cpux*/
+ writel( /* clk_src: 1=24Mhz 2=pll-cpux */ (2 << 16) |
+ /* apb_div: /2 */ (1 << 8) |
+ /* axi_div: /2 */ (1 << 0),
+ regs + CCU_CPUX_AXI_CFG);
+ /* wait 8 cycles */
+ nop_delay(8);
+
+ clks[CLK_PLL_CPUX] = clk_fixed("pll-cpux", 816 * MHZ);
+ clks[CLK_CPUX] = sunxi_clk_mux("cpux", sel_cpux, ARRAY_SIZE(sel_cpux), regs + CCU_CPUX_AXI_CFG, 16, 2);
+
+ /* set pll-periph0-2x to 1.2GHz, as recommended */
+ sunxi_clk_set_pll(regs + CCU_PLL_PERIPH0, 24 * MHZ, 1200 * MHZ);
+
+ clks[CLK_PLL_PERIPH0_2X] = clk_fixed("pll-periph0-2x", 1200 * MHZ);
+ clks[CLK_PLL_PERIPH0] = clk_fixed_factor("pll-periph0", "pll-periph0-2x", 1, 2, 0);
+
+ clks[CLK_AXI] = sunxi_clk_div("axi", "cpux", regs + CCU_CPUX_AXI_CFG, 0, 2);
+
+ clks[CLK_AHB1] = sunxi_clk_mux("ahb1", sel_ahb1, ARRAY_SIZE(sel_ahb1), regs + 0x054, 12, 2);
+ clks[CLK_AHB2] = sunxi_clk_mux("ahb2", sel_ahb2, ARRAY_SIZE(sel_ahb2), regs + 0x05c, 0, 1);
+
+ clks[CLK_APB1] = sunxi_clk_div_table("apb1", "ahb1", div_apb1, regs + 0x054, 8, 2);
+ clks[CLK_APB2] = sunxi_clk_mux("apb2", sel_apb2, ARRAY_SIZE(sel_apb2), regs + 0x058, 24, 2);
+
+ clks[CLK_BUS_MIPI_DSI] = sunxi_clk_gate("bus-mipi-dsi", "ahb1", regs + 0x060, 1);
+ clks[CLK_BUS_CE] = sunxi_clk_gate("bus-ce", "ahb1", regs + 0x060, 5);
+ clks[CLK_BUS_DMA] = sunxi_clk_gate("bus-dma", "ahb1", regs + 0x060, 6);
+ clks[CLK_BUS_MMC0] = sunxi_clk_gate("bus-mmc0", "ahb1", regs + 0x060, 8);
+ clks[CLK_BUS_MMC1] = sunxi_clk_gate("bus-mmc1", "ahb1", regs + 0x060, 9);
+ clks[CLK_BUS_MMC2] = sunxi_clk_gate("bus-mmc2", "ahb1", regs + 0x060, 10);
+ clks[CLK_BUS_NAND] = sunxi_clk_gate("bus-nand", "ahb1", regs + 0x060, 13);
+ clks[CLK_BUS_DRAM] = sunxi_clk_gate("bus-dram", "ahb1", regs + 0x060, 14);
+ clks[CLK_BUS_EMAC] = sunxi_clk_gate("bus-emac", "ahb2", regs + 0x060, 17);
+ clks[CLK_BUS_TS] = sunxi_clk_gate("bus-ts", "ahb1", regs + 0x060, 18);
+ clks[CLK_BUS_HSTIMER] = sunxi_clk_gate("bus-hstimer", "ahb1", regs + 0x060, 19);
+ clks[CLK_BUS_SPI0] = sunxi_clk_gate("bus-spi0", "ahb1", regs + 0x060, 20);
+ clks[CLK_BUS_SPI1] = sunxi_clk_gate("bus-spi1", "ahb1", regs + 0x060, 21);
+ clks[CLK_BUS_OTG] = sunxi_clk_gate("bus-otg", "ahb1", regs + 0x060, 23);
+ clks[CLK_BUS_EHCI0] = sunxi_clk_gate("bus-ehci0", "ahb1", regs + 0x060, 24);
+ clks[CLK_BUS_EHCI1] = sunxi_clk_gate("bus-ehci1", "ahb2", regs + 0x060, 25);
+ clks[CLK_BUS_OHCI0] = sunxi_clk_gate("bus-ohci0", "ahb1", regs + 0x060, 28);
+ clks[CLK_BUS_OHCI1] = sunxi_clk_gate("bus-ohci1", "ahb2", regs + 0x060, 29);
+
+ clks[CLK_BUS_CODEC] = sunxi_clk_gate("bus-codec", "apb1", regs + 0x068, 0);
+ clks[CLK_BUS_SPDIF] = sunxi_clk_gate("bus-spdif", "apb1", regs + 0x068, 1);
+ clks[CLK_BUS_PIO] = sunxi_clk_gate("bus-pio", "apb1", regs + 0x068, 5);
+ clks[CLK_BUS_THS] = sunxi_clk_gate("bus-ths", "apb1", regs + 0x068, 8);
+ clks[CLK_BUS_I2S0] = sunxi_clk_gate("bus-i2s0", "apb1", regs + 0x068, 12);
+ clks[CLK_BUS_I2S1] = sunxi_clk_gate("bus-i2s1", "apb1", regs + 0x068, 13);
+ clks[CLK_BUS_I2S2] = sunxi_clk_gate("bus-i2s2", "apb1", regs + 0x068, 14);
+
+ clks[CLK_BUS_UART0] = sunxi_clk_gate("bus-uart0", "apb2", regs + 0x06c, 16);
+ clks[CLK_BUS_UART1] = sunxi_clk_gate("bus-uart1", "apb2", regs + 0x06c, 17);
+ clks[CLK_BUS_UART2] = sunxi_clk_gate("bus-uart2", "apb2", regs + 0x06c, 18);
+ clks[CLK_BUS_UART3] = sunxi_clk_gate("bus-uart3", "apb2", regs + 0x06c, 19);
+ clks[CLK_BUS_UART4] = sunxi_clk_gate("bus-uart4", "apb2", regs + 0x06c, 20);
+
+ clks[CLK_MMC0] = sunxi_ccu_clk(
+ "mmc0", sel_mmc, ARRAY_SIZE(sel_mmc),
+ regs, 0x088,
+ (struct ccu_clk_mux) { .shift = 24, .width = 2 },
+ (const struct ccu_clk_div[4]) {
+ { .type = CCU_CLK_DIV_P, .shift = 16, .width = 2, .off = 0 },
+ { .type = CCU_CLK_DIV_M, .shift = 0, .width = 4, .off = 0 },
+ { .type = CCU_CLK_DIV_FIXED, .shift = 0, .width = 0, .off = 2 },
+ },
+ 3,
+ BIT(31),
+ 0);
+
+ clks[CLK_MMC1] = sunxi_ccu_clk(
+ "mmc1", sel_mmc, ARRAY_SIZE(sel_mmc),
+ regs, 0x08c,
+ (struct ccu_clk_mux) { .shift = 24, .width = 2 },
+ (const struct ccu_clk_div[4]) {
+ { .type = CCU_CLK_DIV_P, .shift = 16, .width = 2, .off = 0 },
+ { .type = CCU_CLK_DIV_M, .shift = 0, .width = 4, .off = 0 },
+ { .type = CCU_CLK_DIV_FIXED, .shift = 0, .width = 0, .off = 2 },
+ },
+ 3,
+ BIT(31),
+ 0);
+
+ clks[CLK_MMC2] = sunxi_ccu_clk(
+ "mmc2", sel_mmc, ARRAY_SIZE(sel_mmc),
+ regs, 0x090,
+ (struct ccu_clk_mux) { .shift = 24, .width = 2 },
+ (const struct ccu_clk_div[4]) {
+ { .type = CCU_CLK_DIV_P, .shift = 16, .width = 2, .off = 0 },
+ { .type = CCU_CLK_DIV_M, .shift = 0, .width = 4, .off = 0 },
+ { .type = CCU_CLK_DIV_FIXED, .shift = 0, .width = 0, .off = 2 },
+ },
+ 3,
+ BIT(31),
+ 0);
+}
+
+static int sun50i_a64_ccu_probe(struct device *dev)
+{
+ struct resource *iores;
+
+ iores = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(iores))
+ return PTR_ERR(iores);
+
+ sun50i_a64_resets_init(IOMEM(iores->start));
+ sun50i_a64_clocks_init(IOMEM(iores->start));
+
+ return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, &clk_data);
+}
+
+static __maybe_unused struct of_device_id sun50i_a64_ccu_dt_ids[] = {
+ { .compatible = "allwinner,sun50i-a64-ccu" },
+ { }
+};
+
+static struct driver sun50i_a64_ccu_driver = {
+ .probe = sun50i_a64_ccu_probe,
+ .name = "sun50i-a64-ccu",
+ .of_compatible = DRV_OF_COMPAT(sun50i_a64_ccu_dt_ids),
+};
+core_platform_driver(sun50i_a64_ccu_driver);
diff --git a/drivers/clk/sunxi/clk-sun50i-a64.h b/drivers/clk/sunxi/clk-sun50i-a64.h
new file mode 100644
index 0000000000..a4ddc39eb8
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun50i-a64.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ */
+
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
+
+#ifndef _CLK_SUN50I_A64_H_
+#define _CLK_SUN50I_A64_H_
+
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
+
+#define CLK_OSC_12M 0
+#define CLK_PLL_CPUX 1
+#define CLK_PLL_AUDIO_BASE 2
+#define CLK_PLL_AUDIO 3
+#define CLK_PLL_AUDIO_2X 4
+#define CLK_PLL_AUDIO_4X 5
+#define CLK_PLL_AUDIO_8X 6
+
+/* PLL_VIDEO0 exported for HDMI PHY */
+
+#define CLK_PLL_VIDEO0_2X 8
+#define CLK_PLL_VE 9
+#define CLK_PLL_DDR0 10
+
+/* PLL_PERIPH0 exported for PRCM */
+
+#define CLK_PLL_PERIPH0_2X 12
+#define CLK_PLL_PERIPH1 13
+#define CLK_PLL_PERIPH1_2X 14
+#define CLK_PLL_VIDEO1 15
+#define CLK_PLL_GPU 16
+#define CLK_PLL_MIPI 17
+#define CLK_PLL_HSIC 18
+#define CLK_PLL_DE 19
+#define CLK_PLL_DDR1 20
+#define CLK_AXI 22
+#define CLK_APB 23
+#define CLK_AHB1 24
+#define CLK_APB1 25
+#define CLK_APB2 26
+#define CLK_AHB2 27
+
+/* All the bus gates are exported */
+
+/* The first bunch of module clocks are exported */
+
+#define CLK_USB_OHCI0_12M 90
+
+#define CLK_USB_OHCI1_12M 92
+
+/* All the DRAM gates are exported */
+
+/* And the DSI and GPU module clock is exported */
+
+#define CLK_NUMBER (CLK_GPU + 1)
+
+#endif /* _CLK_SUN50I_A64_H_ */
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
new file mode 100644
index 0000000000..ae96d1939e
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2024 Jules Maselbas
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include "clk-sunxi.h"
+
+/* clk_hw to ccu_clk */
+#define to_ccu_clk(_hw) container_of(_hw, struct ccu_clk, hw)
+
+static void ccu_clk_gate(struct ccu_clk *clk, int enable)
+{
+ u32 val, old;
+
+ if (!clk->gate)
+ return;
+
+ old = val = readl(clk->base + clk->reg);
+ if (enable)
+ val |= clk->gate;
+ else
+ val &= ~clk->gate;
+ writel(val, clk->base + clk->reg);
+}
+
+static int ccu_clk_enable(struct clk_hw *hw)
+{
+ struct ccu_clk *clk = to_ccu_clk(hw);
+
+ ccu_clk_gate(clk, 1);
+
+ return 0;
+}
+
+static void ccu_clk_disable(struct clk_hw *hw)
+{
+ struct ccu_clk *clk = to_ccu_clk(hw);
+
+ ccu_clk_gate(clk, 0);
+}
+
+static int ccu_clk_is_enabled(struct clk_hw *hw)
+{
+ struct ccu_clk *clk = to_ccu_clk(hw);
+
+ if (clk->gate)
+ return readl(clk->base + clk->reg) & clk->gate;
+
+ return 1;
+}
+
+static int ccu_clk_get_parent(struct clk_hw *hw)
+{
+ struct ccu_clk *clk = to_ccu_clk(hw);
+ u32 reg, val;
+
+ if (!clk->mux.width)
+ return 0;
+
+ reg = readl(clk->base + clk->reg);
+ val = reg >> clk->mux.shift;
+ val &= (1 << clk->mux.width) - 1;
+
+ return clk_mux_val_to_index(hw, (u32 *)clk->mux.table, 0, val);
+}
+
+static int ccu_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct ccu_clk *clk = to_ccu_clk(hw);
+ u32 reg, val;
+
+ if (!clk->mux.width)
+ return 0;
+
+ /* index to val */
+ val = clk->mux.table ? clk->mux.table[index] : index;
+
+ reg = readl(clk->base + clk->reg);
+ reg &= ~(((1 << clk->mux.width) - 1) << clk->mux.shift);
+ reg |= val << clk->mux.shift;
+
+ writel(reg, clk->base + clk->reg);
+
+ return 0;
+}
+
+static u32 ccu_clk_get_div(struct ccu_clk_div *div, u32 val)
+{
+ u32 d;
+
+ switch (div->type) {
+ case CCU_CLK_DIV_FIXED:
+ d = div->off;
+ break;
+ case CCU_CLK_DIV_M:
+ d = val + 1 + div->off;
+ break;
+ case CCU_CLK_DIV_P:
+ d = (1 << val) + div->off;
+ break;
+ default:
+ d = 1;
+ break;
+ }
+
+ return d;
+}
+
+static u32 ccu_clk_min_div(struct ccu_clk *clk)
+{
+ u32 d = 1;
+ size_t i;
+
+ for (i = 0; i < 4; i++)
+ d *= ccu_clk_get_div(&clk->div[i], 0);
+
+ return d;
+}
+
+static u32 ccu_clk_max_div(struct ccu_clk *clk)
+{
+ u32 d = 1;
+ size_t i;
+
+ for (i = 0; i < 4; i++)
+ d *= ccu_clk_get_div(&clk->div[i], (1 << clk->div[i].width) - 1);
+
+ return d;
+}
+
+static unsigned long ccu_clk_find_best_div(struct ccu_clk *clk,
+ unsigned long rate, unsigned long prate,
+ u32 best_div[4])
+{
+ unsigned long r, best_rate = 0;
+ u32 i0, i1, i2, i3;
+ u32 m0, m1, m2, m3;
+ u32 d0, d1, d2, d3;
+
+ m0 = (1 << clk->div[0].width);
+ m1 = (1 << clk->div[1].width);
+ m2 = (1 << clk->div[2].width);
+ m3 = (1 << clk->div[3].width);
+
+ for (i3 = 0; i3 < m3; i3++) {
+ d3 = ccu_clk_get_div(&clk->div[3], i3);
+ for (i2 = 0; i2 < m2; i2++) {
+ d2 = d3 * ccu_clk_get_div(&clk->div[2], i2);
+ for (i1 = 0; i1 < m1; i1++) {
+ d1 = d2 * ccu_clk_get_div(&clk->div[1], i1);
+ for (i0 = 0; i0 < m0; i0++) {
+ d0 = d1 * ccu_clk_get_div(&clk->div[0], i0);
+ r = prate / d0;
+ if (r > rate)
+ continue;
+ if ((rate - r) < (rate - best_rate)) {
+ best_rate = r;
+ if (best_div) {
+ best_div[0] = i0;
+ best_div[1] = i1;
+ best_div[2] = i2;
+ best_div[3] = i3;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ return best_rate;
+}
+
+static struct clk *clk_get_parent_index(struct clk *clk, int num)
+{
+ if (num >= clk->num_parents)
+ return NULL;
+
+ if (clk->parents[num])
+ return clk->parents[num];
+
+ clk->parents[num] = clk_lookup(clk->parent_names[num]);
+
+ return clk->parents[num];
+}
+
+static unsigned long ccu_clk_find_best_parent(struct ccu_clk *clk, unsigned long rate, int *idx)
+{
+ u32 min_div, max_div;
+ unsigned long min_rate, max_rate;
+ size_t i;
+
+ min_div = ccu_clk_min_div(clk);
+ max_div = ccu_clk_max_div(clk);
+
+ min_rate = rate * min_div;
+ max_rate = rate * max_div;
+
+ for (i = 0; i < clk->hw.clk.num_parents; i++) {
+ struct clk *parent = clk_get_parent_index(&clk->hw.clk, i);
+ unsigned long pr;
+
+ if (IS_ERR_OR_NULL(parent))
+ continue;
+
+ pr = clk_get_rate(parent);
+ if (min_rate <= pr && pr <= max_rate) {
+ if (idx)
+ *idx = i;
+ return pr;
+ }
+ }
+
+ return 0;
+}
+
+static int ccu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct ccu_clk *clk = to_ccu_clk(hw);
+ unsigned long rrate;
+ size_t i;
+ u32 dval[4] = {};
+ u32 reg, val, msk;
+ int idx;
+
+ prate = ccu_clk_find_best_parent(clk, rate, &idx);
+ ccu_clk_set_parent(hw, idx);
+
+ rrate = ccu_clk_find_best_div(clk, rate, prate, dval);
+ val = 0;
+ msk = 0;
+ for (i = 0; i < 4; i++) {
+ val |= dval[i] << clk->div[i].shift;
+ msk |= ((1 << clk->div[i].width) - 1) << clk->div[i].shift;
+ }
+
+ reg = readl(clk->base + clk->reg);
+ reg &= ~msk;
+ reg |= val & msk;
+ writel(reg, clk->base + clk->reg);
+
+ return 0;
+}
+
+static long ccu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct ccu_clk *clk = to_ccu_clk(hw);
+
+ if (clk->mux.width)
+ *prate = ccu_clk_find_best_parent(clk, rate, NULL);
+
+ return ccu_clk_find_best_div(clk, rate, *prate, NULL);
+}
+
+static unsigned long ccu_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct ccu_clk *clk = to_ccu_clk(hw);
+ unsigned long rate = prate;
+ size_t i;
+ u32 reg, val, div;
+
+ div = 1;
+ reg = readl(clk->base + clk->reg);
+ for (i = 0; i < clk->num_div; i++) {
+ val = reg >> clk->div[i].shift;
+ val &= (1 << clk->div[i].width) - 1;
+ div *= ccu_clk_get_div(&clk->div[i], val);
+ }
+ rate = prate / div;
+
+ return rate;
+}
+
+const struct clk_ops ccu_clk_ops = {
+ /* gate */
+ .disable = ccu_clk_disable,
+ .enable = ccu_clk_enable,
+ .is_enabled = ccu_clk_is_enabled,
+ /* mux */
+ .get_parent = ccu_clk_get_parent,
+ .set_parent = ccu_clk_set_parent,
+ /* rate */
+ .round_rate = ccu_clk_round_rate,
+ .set_rate = ccu_clk_set_rate,
+ .recalc_rate = ccu_clk_recalc_rate,
+};
+
+static struct clk *sunxi_ccu_clk_alloc(const char *name,
+ const char * const *parents, u8 num_parents,
+ void __iomem *base, u32 reg,
+ struct ccu_clk_mux mux,
+ const struct ccu_clk_div *div, u8 num_div,
+ u32 gate,
+ int flags)
+{
+ struct ccu_clk *clk;
+ size_t i;
+
+ clk = xzalloc(sizeof(*clk));
+ clk->base = base;
+ clk->reg = reg;
+
+ clk->mux = mux;
+ clk->num_div = num_div > 4 ? 4 : num_div;
+ for (i = 0; i < clk->num_div; i++)
+ clk->div[i] = div[i];
+ clk->gate = gate;
+
+ clk->hw.clk.ops = &ccu_clk_ops;
+ clk->hw.clk.name = name;
+ clk->hw.clk.flags = flags;
+ clk->hw.clk.parent_names = parents;
+ clk->hw.clk.num_parents = num_parents;
+
+ return &clk->hw.clk;
+}
+
+struct clk *sunxi_ccu_clk(const char *name,
+ const char * const *parents, u8 num_parents,
+ void __iomem *base, u32 reg,
+ struct ccu_clk_mux mux,
+ const struct ccu_clk_div *div, u8 num_div,
+ u32 gate,
+ int flags)
+{
+ struct clk *c;
+ int ret;
+
+ c = sunxi_ccu_clk_alloc(name, parents, num_parents,
+ base, reg,
+ mux,
+ div, num_div,
+ gate,
+ flags);
+
+ ret = bclk_register(c);
+ if (ret) {
+ struct clk_hw *hw = clk_to_clk_hw(c);
+ free(to_ccu_clk(hw));
+ return ERR_PTR(ret);
+ }
+
+ return c;
+}
diff --git a/drivers/clk/sunxi/clk-sunxi.h b/drivers/clk/sunxi/clk-sunxi.h
new file mode 100644
index 0000000000..75e8d198ce
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sunxi.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-FileCopyrightText: 2024 Jules Maselbas */
+#include <linux/clk.h>
+
+static inline struct clk *
+sunxi_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift)
+{
+ return clk_gate(name, parent, reg, shift, 0, 0);
+}
+
+static inline struct clk *
+sunxi_clk_mux(const char *name, const char * const *parents, u8 num_parents,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_mux(name, 0, reg, shift, width, parents, num_parents, 0);
+}
+
+static inline struct clk *
+sunxi_clk_div_table(const char *name, const char *parent, struct clk_div_table *table,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_divider_table(name, parent, CLK_SET_RATE_PARENT, reg, shift,
+ width, table, 0);
+}
+
+static inline struct clk *
+sunxi_clk_div(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_divider(name, parent, CLK_SET_RATE_PARENT, reg, shift,
+ width, 0);
+}
+
+static inline void nop_delay(u32 cnt)
+{
+ while (cnt--)
+ barrier();
+}
+
+/* a "one size fit all" clk for barebox */
+
+struct ccu_clk {
+ struct clk_hw hw;
+ u32 reg;
+ void __iomem *base;
+
+ u32 gate;
+
+ struct ccu_clk_mux {
+ u8 shift;
+ u8 width;
+ const u32 *table;
+ } mux;
+
+ u8 num_div;
+ struct ccu_clk_div {
+ u8 shift;
+ u8 width;
+ u8 type;
+ u16 max;
+ u16 off;
+ } div[4];
+};
+
+enum ccu_clk_div_type {
+ CCU_CLK_DIV_FIXED = 1,
+ CCU_CLK_DIV_M,
+ CCU_CLK_DIV_P,
+};
+
+extern const struct clk_ops ccu_clk_ops;
+
+struct clk *sunxi_ccu_clk(const char *name,
+ const char * const *parents, u8 num_parents,
+ void __iomem *base, u32 reg,
+ struct ccu_clk_mux mux,
+ const struct ccu_clk_div *div, u8 num_div,
+ u32 gate,
+ int flags);
--
2.47.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/6] pinctrl: Add sun50i-a64 pinctrl driver
2025-01-07 14:37 [PATCH v2 0/6] Initial support for Allwinner A64 SoC Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 1/6] clk: divider: add error code propagation Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 2/6] clk: Add clock driver for sun50i-a64 Jules Maselbas
@ 2025-01-07 14:37 ` Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 4/6] mci: Add sunxi-mmc driver Jules Maselbas
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Jules Maselbas @ 2025-01-07 14:37 UTC (permalink / raw)
To: barebox; +Cc: Jules Maselbas
sunxi pinctrl driver, adapted from Linux, is split in two parts:
- pinctrl-sunxi.c that implements gpio, pinctrl and pinmux functions
- pinctrl-sun50i-a64.c that declare sun50i pins and their functions.
This file only require minor adaptations and be easily copied from Linux.
The pin functions are needed for uart, SD/MMC, and likely for other
controllers too.
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
---
v1->v2:
- removed `!IS_ENABLED(CONFIG_PINCTRL)` (Ahmad)
drivers/pinctrl/Kconfig | 2 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/sunxi/Kconfig | 13 +
drivers/pinctrl/sunxi/Makefile | 3 +
drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 594 +++++++++++++++++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 369 +++++++++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 224 ++++++++
7 files changed, 1206 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/Kconfig
create mode 100644 drivers/pinctrl/sunxi/Makefile
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ee15acdcdb..72ca79aa98 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -106,6 +106,8 @@ config PINCTRL_STM32
select HAVE_GPIO_PINCONF
help
Pinmux and GPIO controller found on STM32 family
+
+source "drivers/pinctrl/sunxi/Kconfig"
endif
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f1a5fa5715..3bc718d355 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
new file mode 100644
index 0000000000..38d8894a7e
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-only
+if ARCH_SUNXI
+
+config PINCTRL_SUNXI
+ bool
+ select GPIOLIB
+
+config PINCTRL_SUN50I_A64
+ bool "Support for Allwinner A64 PIO"
+ default ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
new file mode 100644
index 0000000000..db0ff5b50b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_ARCH_SUNXI) += pinctrl-sunxi.o
+obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
new file mode 100644
index 0000000000..db96cb52b9
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Allwinner A64 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 - ARM Ltd.
+ * Author: Andre Przywara <andre.przywara@arm.com>
+ *
+ * Based on pinctrl-sun7i-a20.c, which is:
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a64_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x4, "jtag"), /* MS0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x4, "jtag"), /* CK0 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x4, "jtag"), /* DO0 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "jtag"), /* DI0 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif2"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
+ SUNXI_FUNCTION(0x5, "sim"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif2"), /* BCLK */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION(0x5, "sim"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif2"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
+ SUNXI_FUNCTION(0x5, "sim"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif2"), /* DIN */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
+ SUNXI_FUNCTION(0x5, "sim"), /* DET */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* EINT9 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* CS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NRB1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS */
+ SUNXI_FUNCTION(0x5, "ccir")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x5, "ccir")), /* DE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "uart4"), /* TX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x5, "ccir")), /* HSYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "uart4"), /* RX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x5, "ccir")), /* VSYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x4, "emac"), /* ERXD3 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x4, "emac"), /* ERXD2 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ERXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ERXCTL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ENULL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
+ SUNXI_FUNCTION(0x4, "emac"), /* ETXD3 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
+ SUNXI_FUNCTION(0x4, "emac"), /* ETXD2 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
+ SUNXI_FUNCTION(0x4, "emac")), /* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
+ SUNXI_FUNCTION(0x4, "emac")), /* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ETXCTL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ECLKIN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
+ SUNXI_FUNCTION(0x4, "emac")), /* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "emac")), /* EMDIO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* PCK */
+ SUNXI_FUNCTION(0x4, "ts")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* CK */
+ SUNXI_FUNCTION(0x4, "ts")), /* ERR */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
+ SUNXI_FUNCTION(0x4, "ts")), /* SYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
+ SUNXI_FUNCTION(0x4, "ts")), /* DVLD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D0 */
+ SUNXI_FUNCTION(0x4, "ts")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D1 */
+ SUNXI_FUNCTION(0x4, "ts")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D2 */
+ SUNXI_FUNCTION(0x4, "ts")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D3 */
+ SUNXI_FUNCTION(0x4, "ts")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D4 */
+ SUNXI_FUNCTION(0x4, "ts")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D5 */
+ SUNXI_FUNCTION(0x4, "ts")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D6 */
+ SUNXI_FUNCTION(0x4, "ts")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D7 */
+ SUNXI_FUNCTION(0x4, "ts")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pll"), /* LOCK_DBG */
+ SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* MSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart0")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif3"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif3"), /* BCLK */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif3"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif3"), /* DIN */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* EINT13 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mic"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mic"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
+ .pins = a64_pins,
+ .npins = ARRAY_SIZE(a64_pins),
+};
+
+static const struct of_device_id a64_pinctrl_dt_match[] = {
+ {
+ .compatible = "allwinner,sun50i-a64-pinctrl",
+ .data = &a64_pinctrl_data
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver a64_pinctrl_driver = {
+ .name = "sun50i-a64-pinctrl",
+ .probe = sunxi_pinctrl_probe,
+ .of_compatible = DRV_OF_COMPAT(a64_pinctrl_dt_match),
+};
+core_platform_driver(a64_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
new file mode 100644
index 0000000000..0505efa9b9
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#define pr_fmt(fmt) "pinctrl-sunxi: " fmt
+
+#include <common.h>
+#include <io.h>
+#include <of.h>
+#include <of_address.h>
+#include <malloc.h>
+#include <linux/clk.h>
+
+#include "pinctrl-sunxi.h"
+
+/* This driver assumes the gpio function mux value will not change */
+#define FUNC_GPIO_IN 0
+#define FUNC_GPIO_OUT 1
+
+static struct sunxi_pinctrl *to_sunxi_pinctrl(struct pinctrl_device *pdev)
+{
+ return container_of(pdev, struct sunxi_pinctrl, pdev);
+}
+
+static void sunxi_pinctrl_set_pull(struct sunxi_pinctrl *pinctrl,
+ u16 pin, u32 pull)
+{
+ u32 reg = sunxi_pull_reg(pin);
+ u32 off = sunxi_pull_offset(pin);
+ u32 msk = MUX_PINS_MASK << off;
+ u32 val = readl(pinctrl->base + reg);
+
+ val &= ~msk;
+ val |= (pull << off) & msk;
+ writel(val, pinctrl->base + reg);
+}
+
+static void sunxi_pinctrl_set_dlevel(struct sunxi_pinctrl *pinctrl,
+ u16 pin, u32 lvl)
+{
+ u32 reg = sunxi_dlevel_reg(pin);
+ u32 off = sunxi_dlevel_offset(pin);
+ u32 msk = MUX_PINS_MASK << off;
+ u32 val = readl(pinctrl->base + reg);
+
+ val &= ~msk;
+ val |= (lvl << off) & msk;
+ writel(val, pinctrl->base + reg);
+}
+
+static void sunxi_pinctrl_set_mux(struct sunxi_pinctrl *pinctrl,
+ u16 pin, u8 mux)
+{
+ u32 reg = sunxi_mux_reg(pin);
+ u32 off = sunxi_mux_offset(pin);
+ u32 msk = MUX_PINS_MASK << off;
+ u32 val = readl(pinctrl->base + reg);
+
+ val &= ~msk;
+ val |= (mux << off) & msk;
+ writel(val, pinctrl->base + reg);
+}
+
+static u8 sunxi_pinctrl_get_mux(struct sunxi_pinctrl *pinctrl, u16 pin)
+{
+ u32 reg = sunxi_mux_reg(pin);
+ u32 off = sunxi_mux_offset(pin);
+ u32 val = readl(pinctrl->base + reg);
+
+ return (val >> off) & MUX_PINS_MASK;
+}
+
+static void sunxi_pinctrl_set_conf(struct sunxi_pinctrl *pinctrl,
+ u16 pin, struct device_node *node)
+{
+ u32 val;
+
+ if (of_find_property(node, "bias-pull-up", NULL))
+ sunxi_pinctrl_set_pull(pinctrl, pin, 1);
+ if (of_find_property(node, "bias-pull-down", NULL))
+ sunxi_pinctrl_set_pull(pinctrl, pin, 2);
+ if (of_find_property(node, "bias-disable", NULL))
+ sunxi_pinctrl_set_pull(pinctrl, pin, 0);
+
+ if (!of_property_read_u32(node, "drive-strength", &val)) {
+ val = rounddown(val, 10) / 10 - 1;
+ sunxi_pinctrl_set_dlevel(pinctrl, pin, val);
+ }
+}
+
+static const char *sunxi_pinctrl_parse_function_prop(struct device_node *node)
+{
+ const char *function;
+ int ret;
+
+ /* Try the generic binding */
+ ret = of_property_read_string(node, "function", &function);
+ if (!ret)
+ return function;
+
+ /* And fall back to our legacy one */
+ ret = of_property_read_string(node, "allwinner,function", &function);
+ if (!ret)
+ return function;
+
+ return NULL;
+}
+
+static struct property *sunxi_pinctrl_find_pins_prop(struct device_node *node)
+{
+ struct property *prop;
+
+ /* Try the generic binding */
+ prop = of_find_property(node, "pins", NULL);
+ if (prop)
+ return prop;
+
+ /* And fall back to our legacy one */
+ prop = of_find_property(node, "allwinner,pins", NULL);
+ if (prop)
+ return prop;
+
+ return NULL;
+}
+
+#define sunxi_pinctrl_of_pins_for_each_string(np, prop, s) \
+ for (prop = sunxi_pinctrl_find_pins_prop(np), \
+ s = of_prop_next_string(prop, NULL); \
+ s; \
+ s = of_prop_next_string(prop, s))
+
+
+static const struct sunxi_desc_pin *
+sunxi_pinctrl_find_pin(struct sunxi_pinctrl *pinctrl, const char *pin_name)
+{
+ const struct sunxi_desc_pin *pin;
+ int i;
+
+ for (i = 0; i < pinctrl->desc->npins; i++) {
+ pin = &pinctrl->desc->pins[i];
+ if (!strcmp(pin->pin.name, pin_name))
+ return pin;
+ }
+
+ return NULL;
+}
+
+static const struct sunxi_desc_function *
+sunxi_pinctrl_find_func(struct sunxi_pinctrl *pinctrl,
+ const char *pin_name, const char *func_name)
+{
+ const struct sunxi_desc_pin *pin;
+ const struct sunxi_desc_function *func;
+
+ pin = sunxi_pinctrl_find_pin(pinctrl, pin_name);
+ if (!pin)
+ return NULL;
+
+ for (func = pin->functions; func->name; func++)
+ if (!strcmp(func->name, func_name))
+ return func;
+
+ return NULL;
+}
+
+static int sunxi_pinctrl_set_func(struct sunxi_pinctrl *pinctrl,
+ struct device_node *np,
+ const char *pin_name, const char *func_name)
+{
+ struct device *dev = pinctrl->pdev.dev;
+ const struct sunxi_desc_pin *pin;
+ const struct sunxi_desc_function *func;
+
+ dev_dbg(dev, "setfunc %s @ %s\n", func_name, pin_name);
+
+ pin = sunxi_pinctrl_find_pin(pinctrl, pin_name);
+ if (!pin) {
+ dev_err(dev, "pin %s not found\n", pin_name);
+ return -EINVAL;
+ }
+
+ func = sunxi_pinctrl_find_func(pinctrl, pin_name, func_name);
+ if (!func) {
+ dev_err(dev, "func %s not found\n", func_name);
+ return -EINVAL;
+ }
+
+ sunxi_pinctrl_set_mux(pinctrl, pin->pin.number, func->muxval);
+ sunxi_pinctrl_set_conf(pinctrl, pin->pin.number, np);
+
+ return 0;
+}
+
+static int sunxi_pinctrl_set_state(struct pinctrl_device *pdev, struct device_node *np)
+{
+ struct sunxi_pinctrl *pinctrl = to_sunxi_pinctrl(pdev);
+ struct device *dev = pinctrl->pdev.dev;
+ struct property *prop;
+ const char *func_name;
+ const char *pin_name;
+
+ func_name = sunxi_pinctrl_parse_function_prop(np);
+ if (!func_name) {
+ dev_err(dev, "%s: missing 'function' property\n", np->full_name);
+ return -EINVAL;
+ }
+
+ sunxi_pinctrl_of_pins_for_each_string(np, prop, pin_name) {
+ sunxi_pinctrl_set_func(pinctrl, np, pin_name, func_name);
+ }
+
+ return 0;
+}
+
+static int sunxi_pinctrl_set_direction(struct pinctrl_device *pdev, unsigned int gpio, bool in)
+{
+ struct sunxi_pinctrl *pinctrl = to_sunxi_pinctrl(pdev);
+ u32 func = in ? FUNC_GPIO_IN : FUNC_GPIO_OUT;
+
+ sunxi_pinctrl_set_mux(pinctrl, gpio, func);
+
+ return 0;
+}
+
+static int sunxi_gpio_get(struct gpio_chip *chip, unsigned gpio)
+{
+ struct sunxi_pinctrl *pinctrl = chip->dev->priv;
+ u32 reg = sunxi_data_reg(gpio);
+ u32 bit = sunxi_data_offset(gpio);
+ u32 val = readl(pinctrl->base + reg);
+
+ return val & BIT(bit);
+}
+
+static void sunxi_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
+{
+ struct sunxi_pinctrl *pinctrl = chip->dev->priv;
+ u32 reg = sunxi_data_reg(gpio);
+ u32 bit = sunxi_data_offset(gpio);
+ u32 val = readl(pinctrl->base + reg);
+
+ if (value)
+ val |= BIT(bit);
+ else
+ val &= ~BIT(bit);
+ writel(val, pinctrl->base + reg);
+}
+
+static int sunxi_gpio_direction_output(struct gpio_chip *chip,
+ unsigned gpio, int value)
+{
+ struct sunxi_pinctrl *pinctrl = chip->dev->priv;
+
+ sunxi_gpio_set(chip, gpio, value);
+ sunxi_pinctrl_set_mux(pinctrl, gpio, FUNC_GPIO_OUT);
+
+ return 0;
+}
+
+static int sunxi_gpio_direction_input(struct gpio_chip *chip,
+ unsigned gpio)
+{
+ struct sunxi_pinctrl *pinctrl = chip->dev->priv;
+
+ sunxi_pinctrl_set_mux(pinctrl, gpio, FUNC_GPIO_IN);
+
+ return 0;
+}
+
+static int sunxi_gpio_get_direction(struct gpio_chip *chip, unsigned gpio)
+{
+ struct sunxi_pinctrl *pinctrl = chip->dev->priv;
+ u32 func = sunxi_pinctrl_get_mux(pinctrl, gpio);
+
+ if (func == FUNC_GPIO_IN)
+ return GPIOF_DIR_IN;
+ if (func == FUNC_GPIO_OUT)
+ return GPIOF_DIR_OUT;
+ return -EINVAL;
+}
+
+static int sunxi_gpio_of_xlate(struct gpio_chip *chip,
+ const struct of_phandle_args *gpiospec,
+ u32 *flags)
+{
+ int pin, base;
+
+ if (gpiospec->args_count != 3)
+ return -EINVAL;
+
+ base = PINS_PER_BANK * gpiospec->args[0];
+ pin = base + gpiospec->args[1];
+
+ if (pin > chip->ngpio)
+ return -EINVAL;
+
+ if (flags)
+ *flags = gpiospec->args[2];
+
+ return pin;
+}
+
+static struct pinctrl_ops sunxi_pinctrl_ops = {
+ .set_state = sunxi_pinctrl_set_state,
+ .set_direction = sunxi_pinctrl_set_direction,
+};
+
+static struct gpio_ops sunxi_gpio_ops = {
+ .request = sunxi_gpio_direction_input, /* switch to input function */
+ .direction_input = sunxi_gpio_direction_input,
+ .direction_output = sunxi_gpio_direction_output,
+ .get_direction = sunxi_gpio_get_direction,
+ .get = sunxi_gpio_get,
+ .set = sunxi_gpio_set,
+ .of_xlate = sunxi_gpio_of_xlate,
+};
+
+int sunxi_pinctrl_probe(struct device *dev)
+{
+ const struct sunxi_pinctrl_desc *desc;
+ struct sunxi_pinctrl *pinctrl;
+ struct resource *iores;
+ int ret;
+
+ desc = device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ iores = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(iores))
+ return PTR_ERR(iores);
+
+ pinctrl = xzalloc(sizeof(*pinctrl));
+ dev->priv = pinctrl;
+ pinctrl->base = IOMEM(iores->start);
+
+ pinctrl->desc = desc;
+ pinctrl->pdev.dev = dev;
+ pinctrl->pdev.ops = &sunxi_pinctrl_ops;
+
+ ret = pinctrl_register(&pinctrl->pdev);
+ if (ret) {
+ dev_err(dev, "couldn't register %s driver\n", "pinctrl");
+ goto err;
+ }
+ dev_dbg(dev, "sunxi %s registered\n", "pinctrl");
+
+ pinctrl->chip.dev = dev;
+ pinctrl->chip.ops = &sunxi_gpio_ops;
+ /* only the first 8 bank are supported */
+ pinctrl->chip.base = 0;
+ pinctrl->chip.ngpio = 8 * PINS_PER_BANK;
+ pinctrl->chip.of_gpio_n_cells = 3;
+
+ if (of_property_read_bool(dev->of_node, "gpio-controller")) {
+ ret = gpiochip_add(&pinctrl->chip);
+ if (ret) {
+ dev_err(dev, "couldn't register %s driver\n", "gpio-chip");
+ goto pinctrl_unregister;
+ }
+ dev_dbg(dev, "sunxi %s registered\n", "gpio-chip");
+ }
+ return 0;
+
+pinctrl_unregister:
+ pinctrl_unregister(&pinctrl->pdev);
+err:
+ release_region(iores);
+ free(pinctrl);
+ return ret;
+}
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
new file mode 100644
index 0000000000..630f1ef98e
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -0,0 +1,224 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Allwinner A1X SoCs pinctrl driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PINCTRL_SUNXI_H
+#define __PINCTRL_SUNXI_H
+
+#include <pinctrl.h>
+#include <gpio.h>
+
+#define PA_BASE 0
+#define PB_BASE 32
+#define PC_BASE 64
+#define PD_BASE 96
+#define PE_BASE 128
+#define PF_BASE 160
+#define PG_BASE 192
+#define PH_BASE 224
+#define PI_BASE 256
+#define PL_BASE 352
+#define PM_BASE 384
+#define PN_BASE 416
+
+#define SUNXI_PIN_NAME_MAX_LEN 5
+
+#define BANK_MEM_SIZE 0x24
+#define MUX_REGS_OFFSET 0x0
+#define DATA_REGS_OFFSET 0x10
+#define DLEVEL_REGS_OFFSET 0x14
+#define PULL_REGS_OFFSET 0x1c
+
+#define PINS_PER_BANK 32
+#define MUX_PINS_PER_REG 8
+#define MUX_PINS_BITS 4
+#define MUX_PINS_MASK 0x0f
+#define DATA_PINS_PER_REG 32
+#define DATA_PINS_BITS 1
+#define DATA_PINS_MASK 0x01
+#define DLEVEL_PINS_PER_REG 16
+#define DLEVEL_PINS_BITS 2
+#define DLEVEL_PINS_MASK 0x03
+#define PULL_PINS_PER_REG 16
+#define PULL_PINS_BITS 2
+#define PULL_PINS_MASK 0x03
+
+#define GRP_CFG_REG 0x300
+
+#define IO_BIAS_MASK GENMASK(3, 0)
+
+#define SUN4I_FUNC_INPUT 0
+#define SUN4I_FUNC_IRQ 6
+
+#define PINCTRL_SUN5I_A10S BIT(1)
+#define PINCTRL_SUN5I_A13 BIT(2)
+#define PINCTRL_SUN5I_GR8 BIT(3)
+#define PINCTRL_SUN6I_A31 BIT(4)
+#define PINCTRL_SUN6I_A31S BIT(5)
+#define PINCTRL_SUN4I_A10 BIT(6)
+#define PINCTRL_SUN7I_A20 BIT(7)
+#define PINCTRL_SUN8I_R40 BIT(8)
+#define PINCTRL_SUN8I_V3 BIT(9)
+#define PINCTRL_SUN8I_V3S BIT(10)
+
+#define PIO_POW_MOD_SEL_REG 0x340
+
+enum sunxi_desc_bias_voltage {
+ BIAS_VOLTAGE_NONE,
+ /*
+ * Bias voltage configuration is done through
+ * Pn_GRP_CONFIG registers, as seen on A80 SoC.
+ */
+ BIAS_VOLTAGE_GRP_CONFIG,
+ /*
+ * Bias voltage is set through PIO_POW_MOD_SEL_REG
+ * register, as seen on H6 SoC, for example.
+ */
+ BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+};
+
+struct sunxi_desc_function {
+ const char *name;
+ u8 muxval;
+};
+
+struct sunxi_desc_pin {
+ struct {
+ const char name[6];
+ u16 number;
+ } pin;
+ const struct sunxi_desc_function *functions;
+};
+
+struct sunxi_pinctrl_desc {
+ const struct sunxi_desc_pin *pins;
+ size_t npins;
+ unsigned pin_base;
+ bool disable_strict_mode;
+ enum sunxi_desc_bias_voltage io_bias_cfg_variant;
+};
+
+struct sunxi_pinctrl {
+ void __iomem *base;
+ struct gpio_chip chip;
+ struct pinctrl_device pdev;
+ const struct sunxi_pinctrl_desc *desc;
+};
+
+#define SUNXI_PIN(_pin, ...) \
+ { \
+ .pin = _pin, \
+ .functions = (struct sunxi_desc_function[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define SUNXI_PINCTRL_PIN(bank, pin) \
+ { \
+ .name = "P" #bank #pin, \
+ .number = P ## bank ## _BASE + (pin) \
+ }
+
+#define SUNXI_FUNCTION(_val, _name) \
+ { \
+ .name = _name, \
+ .muxval = _val, \
+ }
+
+#define SUNXI_FUNCTION_IRQ_BANK(...) {}
+
+/*
+ * The sunXi PIO registers are organized as is:
+ * 0x00 - 0x0c Muxing values.
+ * 8 pins per register, each pin having a 4bits value
+ * 0x10 Pin values
+ * 32 bits per register, each pin corresponding to one bit
+ * 0x14 - 0x18 Drive level
+ * 16 pins per register, each pin having a 2bits value
+ * 0x1c - 0x20 Pull-Up values
+ * 16 pins per register, each pin having a 2bits value
+ *
+ * This is for the first bank. Each bank will have the same layout,
+ * with an offset being a multiple of 0x24.
+ *
+ * The following functions calculate from the pin number the register
+ * and the bit offset that we should access.
+ */
+static inline u32 sunxi_mux_reg(u16 pin)
+{
+ u8 bank = pin / PINS_PER_BANK;
+ u32 offset = bank * BANK_MEM_SIZE;
+ offset += MUX_REGS_OFFSET;
+ offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
+ return round_down(offset, 4);
+}
+
+static inline u32 sunxi_mux_offset(u16 pin)
+{
+ u32 pin_num = pin % MUX_PINS_PER_REG;
+ return pin_num * MUX_PINS_BITS;
+}
+
+static inline u32 sunxi_data_reg(u16 pin)
+{
+ u8 bank = pin / PINS_PER_BANK;
+ u32 offset = bank * BANK_MEM_SIZE;
+ offset += DATA_REGS_OFFSET;
+ offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
+ return round_down(offset, 4);
+}
+
+static inline u32 sunxi_data_offset(u16 pin)
+{
+ u32 pin_num = pin % DATA_PINS_PER_REG;
+ return pin_num * DATA_PINS_BITS;
+}
+
+static inline u32 sunxi_dlevel_reg(u16 pin)
+{
+ u8 bank = pin / PINS_PER_BANK;
+ u32 offset = bank * BANK_MEM_SIZE;
+ offset += DLEVEL_REGS_OFFSET;
+ offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
+ return round_down(offset, 4);
+}
+
+static inline u32 sunxi_dlevel_offset(u16 pin)
+{
+ u32 pin_num = pin % DLEVEL_PINS_PER_REG;
+ return pin_num * DLEVEL_PINS_BITS;
+}
+
+static inline u32 sunxi_pull_reg(u16 pin)
+{
+ u8 bank = pin / PINS_PER_BANK;
+ u32 offset = bank * BANK_MEM_SIZE;
+ offset += PULL_REGS_OFFSET;
+ offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
+ return round_down(offset, 4);
+}
+
+static inline u32 sunxi_pull_offset(u16 pin)
+{
+ u32 pin_num = pin % PULL_PINS_PER_REG;
+ return pin_num * PULL_PINS_BITS;
+}
+
+static inline u32 sunxi_grp_config_reg(u16 pin)
+{
+ u8 bank = pin / PINS_PER_BANK;
+
+ return GRP_CFG_REG + bank * 0x4;
+}
+
+int sunxi_pinctrl_probe(struct device *dev);
+
+#endif /* __PINCTRL_SUNXI_H */
--
2.47.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/6] mci: Add sunxi-mmc driver
2025-01-07 14:37 [PATCH v2 0/6] Initial support for Allwinner A64 SoC Jules Maselbas
` (2 preceding siblings ...)
2025-01-07 14:37 ` [PATCH v2 3/6] pinctrl: Add sun50i-a64 pinctrl driver Jules Maselbas
@ 2025-01-07 14:37 ` Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 5/6] ARM: sunxi: Introduce mach-sunxi Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 6/6] Documentation: sunxi: Add some documentation Jules Maselbas
5 siblings, 0 replies; 8+ messages in thread
From: Jules Maselbas @ 2025-01-07 14:37 UTC (permalink / raw)
To: barebox; +Cc: Jules Maselbas
This driver is adapted from different sources: Linux, u-boot and p-boot.
The latter, p-boot (forked from u-boot), is a bootloader for pinephones.
It currently only support PIO xfer but could be further improved to also
support DMA xfer. This driver is split in three files so it can be used
by the PBL and barebox proper.
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
---
v1->v2:
- removed the /2 on the clk source (this is in fact done by the clk source)
- convert to gpiod (Ahmad)
drivers/mci/Kconfig | 6 +
drivers/mci/Makefile | 2 +
drivers/mci/sunxi-mmc-common.c | 246 +++++++++++++++++++++++++++++++++
drivers/mci/sunxi-mmc-pbl.c | 81 +++++++++++
drivers/mci/sunxi-mmc.c | 176 +++++++++++++++++++++++
drivers/mci/sunxi-mmc.h | 222 +++++++++++++++++++++++++++++
include/mach/sunxi/xload.h | 12 ++
7 files changed, 745 insertions(+)
create mode 100644 drivers/mci/sunxi-mmc-common.c
create mode 100644 drivers/mci/sunxi-mmc-pbl.c
create mode 100644 drivers/mci/sunxi-mmc.c
create mode 100644 drivers/mci/sunxi-mmc.h
create mode 100644 include/mach/sunxi/xload.h
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index f760614725..4641e9cdcd 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -92,6 +92,12 @@ config MCI_DW_PIO
help
Use PIO mode (instead of IDMAC) in DW MMC driver.
+config MCI_SUNXI_SMHC
+ bool "Allwinner SD-MMC Memory Card Host Controller"
+ help
+ Enable support for the Allwinner SD-MMC Memory Card Host Controller,
+ this provides host support for SD and MMC interfaces, in PIO mode.
+
config MCI_MXS
bool "i.MX23/i.MX28"
depends on ARCH_MXS
diff --git a/drivers/mci/Makefile b/drivers/mci/Makefile
index d8d7818a48..5e951d695f 100644
--- a/drivers/mci/Makefile
+++ b/drivers/mci/Makefile
@@ -22,4 +22,6 @@ obj-$(CONFIG_MCI_DW) += dw_mmc.o
obj-$(CONFIG_MCI_DWC_MSHC) += dwcmshc-sdhci.o
obj-$(CONFIG_MCI_MMCI) += mmci.o
obj-$(CONFIG_MCI_STM32_SDMMC2) += stm32_sdmmc2.o
+obj-$(CONFIG_MCI_SUNXI_SMHC) += sunxi-mmc.o
+pbl-$(CONFIG_MCI_SUNXI_SMHC) += sunxi-mmc-pbl.o
obj-pbl-$(CONFIG_MCI_SDHCI) += sdhci.o
diff --git a/drivers/mci/sunxi-mmc-common.c b/drivers/mci/sunxi-mmc-common.c
new file mode 100644
index 0000000000..cfb6df8cd5
--- /dev/null
+++ b/drivers/mci/sunxi-mmc-common.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2024 Jules Maselbas
+#include "sunxi-mmc.h"
+
+static int sdxc_read_data_pio(struct sunxi_mmc_host *host, struct mci_data *data)
+{
+ size_t i, len = (data->blocks * data->blocksize) / sizeof(u32);
+ u32 *dst = (u32 *)data->dest;
+
+ sdxc_writel(host, SDXC_REG_GCTRL, SDXC_GCTRL_ACCESS_BY_AHB);
+
+ for (i = 0; i < len; i++) {
+ if (wait_on_timeout(2000 * MSECOND, !sdxc_is_fifo_empty(host)))
+ return -ETIMEDOUT;
+ dst[i] = sdxc_readl(host, SDXC_REG_FIFO);
+ }
+
+ return 0;
+}
+
+static int sdxc_write_data_pio(struct sunxi_mmc_host *host, struct mci_data *data)
+{
+ size_t i, len = (data->blocks * data->blocksize) / sizeof(u32);
+ u32 *src = (u32 *)data->src;
+
+ sdxc_writel(host, SDXC_REG_GCTRL, SDXC_GCTRL_ACCESS_BY_AHB);
+
+ for (i = 0; i < len; i++) {
+ if (wait_on_timeout(2000 * MSECOND, !sdxc_is_fifo_full(host)))
+ return -ETIMEDOUT;
+ sdxc_writel(host, SDXC_REG_FIFO, src[i]);
+ }
+
+ return 0;
+}
+
+static int sunxi_mmc_send_cmd(struct sunxi_mmc_host *host, struct mci_cmd *cmd,
+ struct mci_data *data, const char **why)
+{
+ const char *err_why = "";
+ u32 cmdval = SDXC_CMD_START;
+ int ret;
+
+ if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
+ return -EINVAL;
+
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ return 0; /* using ACMD12 */
+ if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
+ cmdval |= SDXC_CMD_SEND_INIT_SEQ;
+
+ if (cmd->resp_type & MMC_RSP_PRESENT)
+ cmdval |= SDXC_CMD_RESP_EXPIRE;
+ if (cmd->resp_type & MMC_RSP_136)
+ cmdval |= SDXC_CMD_LONG_RESPONSE;
+ if (cmd->resp_type & MMC_RSP_CRC)
+ cmdval |= SDXC_CMD_CHK_RESPONSE_CRC;
+
+ /* clear interrupts */
+ sdxc_writel(host, SDXC_REG_RINTR, 0xffffffff);
+
+ if (data) {
+ u32 blksiz = data->blocksize;
+ u32 bytcnt = data->blocks * data->blocksize;
+
+ cmdval |= SDXC_CMD_DATA_EXPIRE;
+ cmdval |= SDXC_CMD_WAIT_PRE_OVER;
+ if (data->flags & MMC_DATA_WRITE)
+ cmdval |= SDXC_CMD_WRITE;
+ if (data->blocks > 1)
+ cmdval |= SDXC_CMD_AUTO_STOP;
+
+ sdxc_writel(host, SDXC_REG_TMOUT, 0xFFFFFF40);
+ sdxc_writel(host, SDXC_REG_BLKSZ, blksiz);
+ sdxc_writel(host, SDXC_REG_BCNTR, bytcnt);
+ }
+
+ sdxc_writel(host, SDXC_REG_CARG, cmd->cmdarg);
+ sdxc_writel(host, SDXC_REG_CMDR, cmdval | cmd->cmdidx);
+ if (data) {
+ if (data->flags & MMC_DATA_WRITE)
+ ret = sdxc_write_data_pio(host, data);
+ else
+ ret = sdxc_read_data_pio(host, data);
+ if (ret < 0) {
+ err_why = "pio error";
+ goto err;
+ }
+ }
+
+ ret = sdxc_xfer_complete(host, 1000 * MSECOND, SDXC_INT_COMMAND_DONE);
+ if (ret) {
+ err_why = "cmd timeout";
+ goto err;
+ }
+
+ if (data) {
+ ret = sdxc_xfer_complete(host, 1000 * MSECOND, data->blocks > 1 ?
+ SDXC_INT_AUTO_COMMAND_DONE :
+ SDXC_INT_DATA_OVER);
+ if (ret) {
+ err_why = "data timeout";
+ goto err;
+ }
+ }
+
+ if (cmd->resp_type & MMC_RSP_BUSY) {
+ u32 status;
+ u64 start;
+ start = get_time_ns();
+ do {
+ status = sdxc_readl(host, SDXC_REG_STAS);
+ if (is_timeout(start, 2000 * MSECOND)) {
+ err_why = "resp timeout";
+ ret = -ETIMEDOUT;
+ goto err;
+ }
+ } while (status & SDXC_STATUS_BUSY);
+ }
+
+ if (wait_on_timeout(1000 * MSECOND, !sdxc_is_card_busy(host))) {
+ err_why = "card busy timeout";
+ ret = -ETIMEDOUT;
+ goto err;
+ }
+
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[0] = sdxc_readl(host, SDXC_REG_RESP3);
+ cmd->response[1] = sdxc_readl(host, SDXC_REG_RESP2);
+ cmd->response[2] = sdxc_readl(host, SDXC_REG_RESP1);
+ cmd->response[3] = sdxc_readl(host, SDXC_REG_RESP0);
+ } else if (cmd->resp_type & MMC_RSP_PRESENT) {
+ cmd->response[0] = sdxc_readl(host, SDXC_REG_RESP0);
+ }
+
+err:
+ if (why)
+ *why = err_why;
+ sdxc_writel(host, SDXC_REG_GCTRL, SDXC_GCTRL_FIFO_RESET);
+ return ret;
+}
+
+static int sunxi_mmc_update_clk(struct sunxi_mmc_host *host)
+{
+ u32 cmdval;
+
+ cmdval = SDXC_CMD_START |
+ SDXC_CMD_UPCLK_ONLY |
+ SDXC_CMD_WAIT_PRE_OVER;
+
+ sdxc_writel(host, SDXC_REG_CARG, 0);
+ sdxc_writel(host, SDXC_REG_CMDR, cmdval);
+
+ if (wait_on_timeout(2000 * MSECOND, !(sdxc_readl(host, SDXC_REG_CMDR) & SDXC_CMD_START)))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int sunxi_mmc_setup_clk(struct sunxi_mmc_host *host, u32 freq)
+{
+ u32 val, div, sclk;
+ int ret;
+
+ sclk = host->clkrate;
+ if (sclk == 0)
+ return -EINVAL;
+
+ /* disable card clock */
+ val = sdxc_readl(host, SDXC_REG_CLKCR);
+ val &= ~(SDXC_CLK_ENABLE | SDXC_CLK_LOW_POWER_ON);
+ val |= SDXC_CLK_MASK_DATA0;
+ sdxc_writel(host, SDXC_REG_CLKCR, val);
+
+ ret = sunxi_mmc_update_clk(host);
+ if (ret)
+ return ret;
+
+ /*
+ * Configure the controller to use the new timing mode if needed.
+ * On controllers that only support the new timing mode, such as
+ * the eMMC controller on the A64, this register does not exist,
+ * and any writes to it are ignored.
+ */
+ if (host->cfg->needs_new_timings) {
+ /* Don't touch the delay bits */
+ val = sdxc_readl(host, SDXC_REG_NTSR);
+ val |= SDXC_NTSR_2X_TIMING_MODE;
+ sdxc_writel(host, SDXC_REG_NTSR, val);
+ }
+
+ /* setup clock rate */
+ div = DIV_ROUND_UP(sclk, freq);
+ div /= 2; /* divisor is multiplied by 2 */
+ if (div > 255)
+ div = 255;
+
+ /* set internal divider */
+ val = sdxc_readl(host, SDXC_REG_CLKCR);
+ val &= ~SDXC_CLK_DIVIDER_MASK;
+ val |= div;
+ sdxc_writel(host, SDXC_REG_CLKCR, val);
+
+ /* enable card clock */
+ val = sdxc_readl(host, SDXC_REG_CLKCR);
+ val |= SDXC_CLK_ENABLE;
+ val &= ~SDXC_CLK_MASK_DATA0;
+ sdxc_writel(host, SDXC_REG_CLKCR, val);
+
+ return sunxi_mmc_update_clk(host);
+}
+
+static int sunxi_mmc_set_ios(struct sunxi_mmc_host *host, struct mci_ios *ios)
+{
+ int ret = 0;
+ u32 width;
+
+ switch (ios->bus_width) {
+ case MMC_BUS_WIDTH_8:
+ width = SDXC_WIDTH_8BIT;
+ break;
+ case MMC_BUS_WIDTH_4:
+ width = SDXC_WIDTH_4BIT;
+ break;
+ default:
+ width = SDXC_WIDTH_1BIT;
+ break;
+ }
+ sdxc_writel(host, SDXC_REG_WIDTH, width);
+
+ if (ios->clock)
+ ret = sunxi_mmc_setup_clk(host, ios->clock);
+ return ret;
+}
+
+static void sunxi_mmc_init(struct sunxi_mmc_host *host)
+{
+ /* Reset controller */
+ sdxc_writel(host, SDXC_REG_GCTRL, SDXC_GCTRL_RESET);
+ udelay(1000);
+
+ sdxc_writel(host, SDXC_REG_RINTR, 0xffffffff);
+ sdxc_writel(host, SDXC_REG_IMASK, 0);
+
+ sdxc_writel(host, SDXC_REG_TMOUT, 0xffffff40);
+}
diff --git a/drivers/mci/sunxi-mmc-pbl.c b/drivers/mci/sunxi-mmc-pbl.c
new file mode 100644
index 0000000000..09044bb2df
--- /dev/null
+++ b/drivers/mci/sunxi-mmc-pbl.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2024 Jules Maselbas
+#include <common.h>
+
+#include <mach/sunxi/xload.h>
+#include "sunxi-mmc.h"
+#include "sunxi-mmc-common.c"
+
+#define SECTOR_SIZE 512
+#define SUPPORT_MAX_BLOCKS 16U
+
+static int sunxi_mmc_read_block(struct sunxi_mmc_host *host,
+ void *dst, unsigned int blocknum,
+ unsigned int blocks)
+{
+ struct mci_data data;
+ struct mci_cmd cmd = {
+ .cmdidx = (blocks > 1) ? MMC_CMD_READ_MULTIPLE_BLOCK : MMC_CMD_READ_SINGLE_BLOCK,
+ /* mci->high_capacity ? blocknum : blocknum * mci->read_bl_len, */
+ /* TODO: detect if card is high-capacity */
+ .cmdarg = blocknum,
+ .resp_type = MMC_RSP_R1,
+ };
+ int ret;
+
+ data.dest = dst;
+ data.blocks = blocks;
+ data.blocksize = SECTOR_SIZE; /* compat with MMC/SD */
+ data.flags = MMC_DATA_READ;
+
+ ret = sunxi_mmc_send_cmd(host, &cmd, &data, NULL);
+
+ if (ret || blocks > 1) {
+ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1b;
+ sunxi_mmc_send_cmd(host, &cmd, NULL, NULL);
+ }
+
+ return ret;
+}
+
+static int sunxi_mmc_bio_read(struct pbl_bio *bio, off_t start,
+ void *buf, unsigned int nblocks)
+{
+ struct sunxi_mmc_host *host = bio->priv;
+ unsigned int count = 0;
+ unsigned int block_len = SECTOR_SIZE;
+ int ret;
+
+ while (count < nblocks) {
+ unsigned int n = min_t(unsigned int, nblocks - count, SUPPORT_MAX_BLOCKS);
+
+ ret = sunxi_mmc_read_block(host, buf, start, n);
+ if (ret < 0)
+ return ret;
+
+ count += n;
+ start += n;
+ buf += n * block_len;
+ }
+
+ return count;
+}
+
+int sunxi_mmc_bio_init(struct pbl_bio *bio, void __iomem *base,
+ unsigned int clock, unsigned int slot)
+{
+ static struct sunxi_mmc_host host;
+ struct mci_ios ios = { .bus_width = MMC_BUS_WIDTH_4, .clock = 400000 };
+
+ host.base = base;
+ host.clkrate = clock;
+ bio->priv = &host;
+ bio->read = sunxi_mmc_bio_read;
+
+ sunxi_mmc_init(&host);
+ sunxi_mmc_set_ios(&host, &ios);
+
+ return 0;
+}
diff --git a/drivers/mci/sunxi-mmc.c b/drivers/mci/sunxi-mmc.c
new file mode 100644
index 0000000000..c7d9928c83
--- /dev/null
+++ b/drivers/mci/sunxi-mmc.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2024 Jules Maselbas
+// derived from: linux/drivers/mmc/host/sunxi-mmc.c
+#define pr_fmt(fmt) "sunxi-mmc: " fmt
+
+#include <common.h>
+#include <driver.h>
+#include <malloc.h>
+#include <init.h>
+#include <mci.h>
+
+#include <gpio.h>
+#include <of_gpio.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <errno.h>
+#include <dma.h>
+
+#include "sunxi-mmc.h"
+#include "sunxi-mmc-common.c"
+
+static int sdxc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
+{
+ struct sunxi_mmc_host *host = to_sunxi_mmc_host(mci);
+ struct device *dev = mci->hw_dev;
+ const char *why;
+ int ret;
+
+ ret = sunxi_mmc_send_cmd(host, cmd, data, &why);
+ if (ret && ret != -ETIMEDOUT)
+ dev_err(dev, "error %s CMD%d (%d)\n", why, cmd->cmdidx, ret);
+ if (ret == -ETIMEDOUT)
+ mdelay(1);
+
+ return ret;
+}
+
+static void sdxc_set_ios(struct mci_host *mci, struct mci_ios *ios)
+{
+ struct sunxi_mmc_host *host = to_sunxi_mmc_host(mci);
+ struct device *dev = mci->hw_dev;
+
+ dev_dbg(dev, "buswidth: %d clock: %d\n", 1 << ios->bus_width, ios->clock);
+ sunxi_mmc_set_ios(host, ios);
+}
+
+static int sdxc_card_present(struct mci_host *mci)
+{
+ struct sunxi_mmc_host *host = to_sunxi_mmc_host(mci);
+
+ /* No gpio, assume card is present */
+ if (IS_ERR_OR_NULL(host->gpio_cd))
+ return 1;
+
+ return gpiod_get_value(host->gpio_cd);
+}
+
+static int sdxc_init(struct mci_host *mci, struct device *dev)
+{
+ struct sunxi_mmc_host *host = to_sunxi_mmc_host(mci);
+
+ sunxi_mmc_init(host);
+
+ return 0;
+}
+
+static const struct mci_ops sdxc_mmc_ops = {
+ .send_cmd = sdxc_send_cmd,
+ .set_ios = sdxc_set_ios,
+ .init = sdxc_init,
+ .card_present = sdxc_card_present,
+};
+
+static int sunxi_mmc_probe(struct device *dev)
+{
+ struct resource *iores;
+ struct sunxi_mmc_host *host;
+ unsigned int f_min, f_max;
+ int ret;
+
+ iores = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(iores))
+ return PTR_ERR(iores);
+ host = xzalloc(sizeof(*host));
+ host->base = IOMEM(iores->start);
+ dma_set_mask(dev, DMA_BIT_MASK(32));
+ host->cfg = device_get_match_data(dev);
+
+ host->gpio_cd = gpiod_get_optional(dev, "cd", GPIOD_IN);
+
+ host->clk_ahb = clk_get(dev, "ahb");
+ if (IS_ERR(host->clk_ahb)) {
+ ret = PTR_ERR(host->clk_ahb);
+ goto err;
+ }
+
+ host->clk_mmc = clk_get(dev, "mmc");
+ if (IS_ERR(host->clk_mmc)) {
+ ret = PTR_ERR(host->clk_mmc);
+ goto err;
+ }
+
+ clk_enable(host->clk_ahb);
+ clk_enable(host->clk_mmc);
+
+ host->mci.hw_dev = dev;
+ host->mci.ops = sdxc_mmc_ops;
+ host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ host->mci.host_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA
+ | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED
+ | MMC_CAP_MMC_HIGHSPEED_52MHZ;
+
+ host->clkrate = clk_get_rate(host->clk_mmc);
+ f_min = host->clkrate / 510;
+ f_max = host->clkrate;
+ /* clock must at least support freq as low as 400K, and reach 52M */
+ if (400000 < f_min || f_max < 52000000) {
+ /* if not, try to get a better clock, clk_set_rate never sets
+ * a frequence above the requested one, thus we try to set a
+ * clk rate close or below 2 * 52MHz (260 * 400KHz).
+ */
+ clk_set_rate(host->clk_mmc, 260 * 400000);
+ host->clkrate = clk_get_rate(host->clk_mmc);
+ f_min = host->clkrate / 510;
+ f_max = host->clkrate;
+ }
+ dev_dbg(dev, "freq: min %d max %d\n", f_min, f_max);
+ mci_of_parse(&host->mci);
+ host->mci.host_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA
+ | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED
+ | MMC_CAP_MMC_HIGHSPEED_52MHZ;
+
+ f_min = min_t(unsigned int, 400000, f_min);
+ f_max = min_t(unsigned int, 52000000, f_max);
+ host->mci.f_min = max_t(unsigned int, host->mci.f_min, f_min);
+ host->mci.f_max = min_t(unsigned int, host->mci.f_max, f_max);
+
+ return mci_register(&host->mci);
+err:
+ if (host->clk_mmc)
+ clk_put(host->clk_mmc);
+ if (host->clk_ahb)
+ clk_put(host->clk_ahb);
+ free(host);
+ release_region(iores);
+ return ret;
+}
+
+static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
+ .idma_des_size_bits = 16,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .mask_data0 = true,
+ .needs_new_timings = true,
+};
+
+static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
+ .idma_des_size_bits = 13,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .needs_new_timings = true,
+};
+
+static __maybe_unused struct of_device_id sunxi_mmc_compatible[] = {
+ { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
+ { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
+ { /* sentinel */ }
+};
+
+static struct driver sunxi_mmc_driver = {
+ .name = "sunxi-mmc",
+ .probe = sunxi_mmc_probe,
+ .of_compatible = DRV_OF_COMPAT(sunxi_mmc_compatible),
+};
+device_platform_driver(sunxi_mmc_driver);
diff --git a/drivers/mci/sunxi-mmc.h b/drivers/mci/sunxi-mmc.h
new file mode 100644
index 0000000000..0668aaf334
--- /dev/null
+++ b/drivers/mci/sunxi-mmc.h
@@ -0,0 +1,222 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-FileCopyrightText: 2024 Jules Maselbas */
+/* derived from: linux/drivers/mmc/host/sunxi-mmc.c */
+
+#ifndef SUNXI_MMC_H
+#define SUNXI_MMC_H
+
+#include <io.h>
+#include <linux/bitops.h>
+#include <linux/gpio/consumer.h>
+#include <clock.h>
+#include <mci.h>
+
+#define SDXC_REG_GCTRL (0x00) /* Global Control */
+#define SDXC_REG_CLKCR (0x04) /* Clock Control */
+#define SDXC_REG_TMOUT (0x08) /* Time Out */
+#define SDXC_REG_WIDTH (0x0C) /* Bus Width */
+#define SDXC_REG_BLKSZ (0x10) /* Block Size */
+#define SDXC_REG_BCNTR (0x14) /* Byte Count */
+#define SDXC_REG_CMDR (0x18) /* Command */
+#define SDXC_REG_CARG (0x1C) /* Argument */
+#define SDXC_REG_RESP0 (0x20) /* Response 0 */
+#define SDXC_REG_RESP1 (0x24) /* Response 1 */
+#define SDXC_REG_RESP2 (0x28) /* Response 2 */
+#define SDXC_REG_RESP3 (0x2C) /* Response 3 */
+#define SDXC_REG_IMASK (0x30) /* Interrupt Mask */
+#define SDXC_REG_MISTA (0x34) /* Masked Interrupt Status */
+#define SDXC_REG_RINTR (0x38) /* Raw Interrupt Status */
+#define SDXC_REG_STAS (0x3C) /* Status */
+#define SDXC_REG_FTRGL (0x40) /* FIFO Threshold Watermark */
+#define SDXC_REG_FUNS (0x44) /* Function Select */
+#define SDXC_REG_CBCR (0x48) /* CIU Byte Count */
+#define SDXC_REG_BBCR (0x4C) /* BIU Byte Count */
+#define SDXC_REG_DBGC (0x50) /* Debug Enable */
+#define SDXC_REG_A12A (0x58) /* Auto Command 12 Argument */
+#define SDXC_REG_NTSR (0x5C) /* SMC New Timing Set Register */
+#define SDXC_REG_HWRST (0x78) /* Card Hardware Reset */
+#define SDXC_REG_DMAC (0x80) /* IDMAC Control */
+#define SDXC_REG_DLBA (0x84) /* IDMAC Descriptor List Base Addresse */
+#define SDXC_REG_IDST (0x88) /* IDMAC Status */
+#define SDXC_REG_IDIE (0x8C) /* IDMAC Interrupt Enable */
+#define SDXC_REG_CHDA (0x90)
+#define SDXC_REG_CBDA (0x94)
+
+#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
+#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
+#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
+
+#define SDXC_REG_FIFO (0x200) /* FIFO */
+
+#define SDXC_GCTRL_SOFT_RESET BIT(0)
+#define SDXC_GCTRL_FIFO_RESET BIT(1)
+#define SDXC_GCTRL_DMA_RESET BIT(2)
+#define SDXC_GCTRL_RESET \
+ (SDXC_GCTRL_SOFT_RESET | SDXC_GCTRL_FIFO_RESET | SDXC_GCTRL_DMA_RESET)
+#define SDXC_GCTRL_DMA_ENABLE BIT(5)
+#define SDXC_GCTRL_ACCESS_BY_AHB BIT(31)
+
+#define SDXC_CMD_RESP_EXPIRE BIT(6)
+#define SDXC_CMD_LONG_RESPONSE BIT(7)
+#define SDXC_CMD_CHK_RESPONSE_CRC BIT(8)
+#define SDXC_CMD_DATA_EXPIRE BIT(9)
+#define SDXC_CMD_WRITE BIT(10)
+#define SDXC_CMD_AUTO_STOP BIT(12)
+#define SDXC_CMD_WAIT_PRE_OVER BIT(13)
+#define SDXC_CMD_ABORT_STOP BIT(14)
+#define SDXC_CMD_SEND_INIT_SEQ BIT(15)
+#define SDXC_CMD_UPCLK_ONLY BIT(21)
+#define SDXC_CMD_START BIT(31)
+
+#define SDXC_NTSR_2X_TIMING_MODE BIT(31)
+
+/* clock control bits */
+#define SDXC_CLK_MASK_DATA0 BIT(31)
+#define SDXC_CLK_LOW_POWER_ON BIT(17)
+#define SDXC_CLK_ENABLE BIT(16)
+#define SDXC_CLK_DIVIDER_MASK (0xff)
+
+/* bus width */
+#define SDXC_WIDTH_1BIT 0
+#define SDXC_WIDTH_4BIT BIT(0)
+#define SDXC_WIDTH_8BIT BIT(1)
+
+/* interrupt bits */
+#define SDXC_INT_RESP_ERROR BIT(1)
+#define SDXC_INT_COMMAND_DONE BIT(2)
+#define SDXC_INT_DATA_OVER BIT(3)
+#define SDXC_INT_TX_DATA_REQUEST BIT(4)
+#define SDXC_INT_RX_DATA_REQUEST BIT(5)
+#define SDXC_INT_RESP_CRC_ERROR BIT(6)
+#define SDXC_INT_DATA_CRC_ERROR BIT(7)
+#define SDXC_INT_RESP_TIMEOUT BIT(8)
+#define SDXC_INT_DATA_TIMEOUT BIT(9)
+#define SDXC_INT_VOLTAGE_CHANGE_DONE BIT(10)
+#define SDXC_INT_FIFO_RUN_ERROR BIT(11)
+#define SDXC_INT_HARD_WARE_LOCKED BIT(12)
+#define SDXC_INT_START_BIT_ERROR BIT(13)
+#define SDXC_INT_AUTO_COMMAND_DONE BIT(14)
+#define SDXC_INT_END_BIT_ERROR BIT(15)
+#define SDXC_INT_SDIO_INTERRUPT BIT(16)
+#define SDXC_INT_CARD_INSERT BIT(30)
+#define SDXC_INT_CARD_REMOVE BIT(31)
+#define SDXC_INTERRUPT_ERROR_BIT \
+ (SDXC_INT_RESP_ERROR | \
+ SDXC_INT_RESP_CRC_ERROR | \
+ SDXC_INT_DATA_CRC_ERROR | \
+ SDXC_INT_RESP_TIMEOUT | \
+ SDXC_INT_DATA_TIMEOUT | \
+ SDXC_INT_HARD_WARE_LOCKED | \
+ SDXC_INT_START_BIT_ERROR | \
+ SDXC_INT_END_BIT_ERROR)
+
+#define SDXC_INTERRUPT_DONE_BIT \
+ (SDXC_INT_AUTO_COMMAND_DONE | \
+ SDXC_INT_DATA_OVER | \
+ SDXC_INT_COMMAND_DONE | \
+ SDXC_INT_VOLTAGE_CHANGE_DONE)
+
+/* status */
+#define SDXC_STATUS_FIFO_EMPTY BIT(2)
+#define SDXC_STATUS_FIFO_FULL BIT(3)
+#define SDXC_STATUS_CARD_PRESENT BIT(8)
+#define SDXC_STATUS_BUSY BIT(9)
+
+struct sunxi_mmc_clk_delay {
+ u32 output;
+ u32 sample;
+};
+
+struct sunxi_mmc_cfg {
+ u32 idma_des_size_bits;
+ u32 idma_des_shift;
+ const struct sunxi_mmc_clk_delay *clk_delays;
+
+ /* does the IP block support autocalibration? */
+ bool can_calibrate;
+
+ /* Does DATA0 needs to be masked while the clock is updated */
+ bool mask_data0;
+
+ /*
+ * hardware only supports new timing mode, either due to lack of
+ * a mode switch in the clock controller, or the mmc controller
+ * is permanently configured in the new timing mode, without the
+ * NTSR mode switch.
+ */
+ bool needs_new_timings;
+
+ /* clock hardware can switch between old and new timing modes */
+ bool ccu_has_timings_switch;
+};
+
+struct sunxi_mmc_host {
+ struct mci_host mci;
+ struct device *dev;
+ struct clk *clk_ahb, *clk_mmc;
+ void __iomem *base;
+ struct gpio_desc *gpio_cd;
+
+ const struct sunxi_mmc_cfg *cfg;
+ u32 clkrate;
+};
+
+static inline struct sunxi_mmc_host *to_sunxi_mmc_host(struct mci_host *mci)
+{
+ return container_of(mci, struct sunxi_mmc_host, mci);
+}
+
+static inline u32 sdxc_readl(struct sunxi_mmc_host *host, u32 reg)
+{
+ return readl(host->base + reg);
+}
+
+static inline void sdxc_writel(struct sunxi_mmc_host *host, u32 reg, u32 val)
+{
+ writel(val, host->base + reg);
+}
+
+static inline int sdxc_is_fifo_empty(struct sunxi_mmc_host *host)
+{
+ return sdxc_readl(host, SDXC_REG_STAS) & SDXC_STATUS_FIFO_EMPTY;
+}
+
+static inline int sdxc_is_fifo_full(struct sunxi_mmc_host *host)
+{
+ return sdxc_readl(host, SDXC_REG_STAS) & SDXC_STATUS_FIFO_FULL;
+}
+
+static inline int sdxc_is_card_busy(struct sunxi_mmc_host *host)
+{
+ return sdxc_readl(host, SDXC_REG_STAS) & SDXC_STATUS_BUSY;
+}
+
+#ifdef __PBL__
+/*
+ * Stubs to make timeout logic below work in PBL
+ */
+#define get_time_ns() 0
+/*
+ * Use time in us as a busy counter timeout value
+ */
+#define is_timeout(s, t) ((s)++ > ((t) / 1000))
+#endif
+
+static inline int sdxc_xfer_complete(struct sunxi_mmc_host *host, u64 timeout, u32 flags)
+{
+ u64 start;
+ u32 rint;
+
+ start = get_time_ns();
+ do {
+ rint = sdxc_readl(host, SDXC_REG_RINTR);
+ if (rint & SDXC_INTERRUPT_ERROR_BIT)
+ break;
+ if (rint & flags)
+ return 0;
+ } while (!is_timeout(start, timeout));
+
+ return -ETIMEDOUT;
+}
+
+#endif
diff --git a/include/mach/sunxi/xload.h b/include/mach/sunxi/xload.h
new file mode 100644
index 0000000000..f978db4951
--- /dev/null
+++ b/include/mach/sunxi/xload.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MACH_XLOAD_H
+#define __MACH_XLOAD_H
+
+#include <linux/compiler.h>
+#include <pbl/bio.h>
+
+int sunxi_mmc_bio_init(struct pbl_bio *bio, void __iomem *base,
+ unsigned int clock, unsigned int slot);
+
+#endif
--
2.47.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 5/6] ARM: sunxi: Introduce mach-sunxi
2025-01-07 14:37 [PATCH v2 0/6] Initial support for Allwinner A64 SoC Jules Maselbas
` (3 preceding siblings ...)
2025-01-07 14:37 ` [PATCH v2 4/6] mci: Add sunxi-mmc driver Jules Maselbas
@ 2025-01-07 14:37 ` Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 6/6] Documentation: sunxi: Add some documentation Jules Maselbas
5 siblings, 0 replies; 8+ messages in thread
From: Jules Maselbas @ 2025-01-07 14:37 UTC (permalink / raw)
To: barebox; +Cc: Jules Maselbas
Add some boilerplate, Makefiles, Kbuild.
A generic barebox-dt-2nd.img image can be build for A64 SoC using
the sunxi_v8_defconfig.
This image can be booted from u-boot and has been tested on Pine64+,
it should work on other A64 SoC such as the pinephone, and other Pine64
boards, it might also work on H6 SoC which uses the same sd/mmc controler.
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
---
v1->v2:
- removed RELOCATABLE and HAVE_PBL_MULTI_IMAGES from Kconfig (Ahmad)
- used __dummy__.o insead of an empty file (Ahmad)
- removed include/mach/sunxi/barebox-arm.h (Ahmad)
arch/arm/Kconfig | 12 ++++++++++++
arch/arm/Makefile | 1 +
arch/arm/configs/sunxi_v8_defconfig | 12 ++++++++++++
arch/arm/mach-sunxi/Kconfig | 12 ++++++++++++
arch/arm/mach-sunxi/Makefile | 1 +
5 files changed, 38 insertions(+)
create mode 100644 arch/arm/configs/sunxi_v8_defconfig
create mode 100644 arch/arm/mach-sunxi/Kconfig
create mode 100644 arch/arm/mach-sunxi/Makefile
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0251f2dcef..83adfaddf7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -109,6 +109,17 @@ config ARCH_SOCFPGA
select CPU_V7
select COMMON_CLK
+config ARCH_SUNXI
+ bool "Allwinner SoCs"
+ depends on 64BIT
+ select CLKDEV_LOOKUP
+ select COMMON_CLK
+ select COMMON_CLK_OF_PROVIDER
+ select GPIOLIB
+ select OFDEVICE
+ select OFTREE
+ select PINCTRL
+
config ARCH_TEGRA
bool "NVIDIA Tegra"
depends on 32BIT
@@ -256,6 +267,7 @@ source "arch/arm/mach-omap/Kconfig"
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
+source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-stm32mp/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 270f5dfdc1..e4041cf715 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -102,6 +102,7 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_SAMSUNG) += samsung
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STM32MP) += stm32mp
+machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
machine-$(CONFIG_ARCH_TEGRA) += tegra
diff --git a/arch/arm/configs/sunxi_v8_defconfig b/arch/arm/configs/sunxi_v8_defconfig
new file mode 100644
index 0000000000..ebadd1c950
--- /dev/null
+++ b/arch/arm/configs/sunxi_v8_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARCH_SUNXI=y
+CONFIG_64BIT=y
+CONFIG_BOARD_ARM_GENERIC_DT=y
+CONFIG_ARCH_SUN50I_A64=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_MCI=y
+CONFIG_MCI_SUNXI_SMHC=y
+CONFIG_CMD_DMESG=y
+CONFIG_MCI_STARTUP=y
+CONFIG_FS_FAT=y
+CONFIG_IMAGE_COMPRESSION_XZKERN=y
+CONFIG_MMU=y
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
new file mode 100644
index 0000000000..e8d23772c2
--- /dev/null
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -0,0 +1,12 @@
+if ARCH_SUNXI
+
+config ARCH_SUN50I_A64
+ bool "Allwinner A64 SoC"
+ select CPU_V8
+ select CPU_SUPPORTS_64BIT_KERNEL
+ select CLOCKSOURCE_ARM_ARCHITECTED_TIMER
+ select PINCTRL_SUN50I_A64
+ help
+ Allwinner A64 (sun50iw1) SoC
+
+endif
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
new file mode 100644
index 0000000000..16a218658a
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile
@@ -0,0 +1 @@
+obj- := __dummy__.o
--
2.47.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 6/6] Documentation: sunxi: Add some documentation
2025-01-07 14:37 [PATCH v2 0/6] Initial support for Allwinner A64 SoC Jules Maselbas
` (4 preceding siblings ...)
2025-01-07 14:37 ` [PATCH v2 5/6] ARM: sunxi: Introduce mach-sunxi Jules Maselbas
@ 2025-01-07 14:37 ` Jules Maselbas
5 siblings, 0 replies; 8+ messages in thread
From: Jules Maselbas @ 2025-01-07 14:37 UTC (permalink / raw)
To: barebox; +Cc: Jules Maselbas
Add some informations about Allwinner sunxi boardsupport: the general
boot process, how to use sunxi-fel tool, and how to create a bootable
image disk.
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
---
Documentation/boards/sunxi.rst | 132 +++++++++++++++++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/boards/sunxi.rst
diff --git a/Documentation/boards/sunxi.rst b/Documentation/boards/sunxi.rst
new file mode 100644
index 0000000000..46832559c9
--- /dev/null
+++ b/Documentation/boards/sunxi.rst
@@ -0,0 +1,132 @@
+..
+ SPDX-License-Identifier: GPL-2.0+
+
+ Copyright (C) 2022, Jules Maselbas
+
+Allwinner sunxi
+===============
+
+Because of size constraints Barebox proper cannot boot directly, the uses
+of :doc:`PBL` allows to compress the Barebox image and it's device-tree.
+However this is not enough, and two images are acctually needed. The first
+image is suffixed *_xload* and it only consist of the PBL with a special
+entry point that looks for ``barebox.bin`` the root of a FAT partition.
+Only the SD card is currently searched, but this could also be in eMMC.
+The second image is your standard Barebox plus PBL image (suffixed ``.pblb``).
+
+Boot process
+------------
+
+On power-up Allwinner SoC starts in boot ROM, aka BROM, which will search
+for an eGON image: first from the SD card, then from eMMC. If no image is
+found then the BROM will enter into FEL mode that can be used for initial
+programming and recovery of devices using USB.
+
+Some board may have a button to enter FEL mode at startup. If not, another
+way to enter FEL mode is to not have a valid image eGON image, this can be
+achived by erasing existing eGON image headers.
+
+eGON header
+-----------
+
+The eGON header structure is described in the file ``include/mach/sunxi/egon.h``.
+This is also documented on https://linux-sunxi.org/EGON .
+
+The eGON header, followed by the actual image, must be located at the fixed
+offset of 8192 bytes (8KB) from the start of the disk (sector 16), either
+from SD card; or from eMMC.
+
+.. code-block:: sh
+
+ # copy the "pine64_xload" eGON image into disk sdX
+ dd if=images/start_pine64_pine64_xload.pblb.egonimg of=/dev/sdX bs=512 seek=16
+
+The above will write the entire "pine64_xload" Barebox PBL plus the eGON
+header into the disk "/dev/sdX".
+
+The boot ROM will load, at most, the first 32KB of the image into SRAM,
+including the header itself! The eGON header starts with a jump instruction
+to jump over the header, this jump instruction needs to be patched accordingly
+with the header size.
+
+.. note::
+
+ On sunxi platforms the boot ROM loads the entire image **including**
+ the eGON header. The actual base address will be offset by the eGON header
+ (currently 96 bytes), this bad because arm instructions used for relocation
+ expect the base address to be aligned on 4K boundary.
+ As a workaround, a eGON header is included and linked into the Barebox
+ PBL image, this dummy header will be filled later by egon_mkimage.
+
+
+Board images are defined in ``images/Makefile.sunxi``, here is an example::
+
+.. code-block:: none
+
+ pblb-$(CONFIG_MACH_PINE64_PINE64) += start_pine64_pine64_xload
+ MAX_PBL_IMAGE_SIZE_start_pine64_pine64_xload = 0x8000
+ FILE_barebox-pine64-pine64_xload.img = start_pine64_pine64_xload.pblb.egonimg
+ image-$(CONFIG_MACH_PINE64_PINE64) += barebox-pine64-pine64_xload.img
+
+
+RMR aarch64 switch
+------------------
+
+Aarch64 capable SoC (A64/sun50i) boot by default in 32-bit mode. A special header
+is added to the start of the PBL image in order to switch to aarch64 mode as soon
+as possible. This must be done very early in the boot process since both ISA are
+not compatible. The code to switch mode is already assembled (mostly arm 32bit)
+and is documented in the header file ``include/mach/sunxi/rmr_switch.h``.
+
+FEL
+---
+
+The ``sunxi-fel`` tool is used to interact, through USB, with sunxi devices
+in FEL mode. ``sunxi-fel`` is part of the sunxi-tools_.
+
+.. _sunxi-tools: https://github.com/linux-sunxi/sunxi-tools
+
+More documentation about FEL_ and how to use the sunxi-fel tool can be
+found on https://linux-sunxi.org/FEL/USBBoot .
+
+.. note::
+
+ ``sunxi-fel`` has a commands dedicated to boot u-boot images but theses
+ commands require a valid eGON header, if not more. This can be easily bypassed.
+
+The ``sunxi-fel`` tool can be used to load any arbitrary image at a given address
+and can also request the processor to jump and start executing at any address.
+This can be achieved by the following two commands::
+
+.. code-block:: sh
+
+ sunxi-fel write-with-progress 0x00018000 images/start_pine64_pinephone.pblb
+ sunxi-fel exe 0x00018000
+
+These two commands allows the use of a different and bigger SRAM than the
+default 32KB used by the boot ROM.
+
+The ``sunxi-fel`` tool might require additional permissions to acces the USB device,
+this can be fixed by using a udev rule to add the most appropriated group to the device,
+as an exemple adding the device to the dialout group can be done with the following rule::
+
+ SUBSYSTEMS=="usb", ATTRS{idVendor}=="1f3a", ATTRS{idProduct}=="efe8", GROUP+="dialout"
+
+
+Arm Trusted Firmware (TF-A)
+---------------------------
+
+Boards using a 64-bit Soc (A64, H5, H6, H616, R329) require the BL31 stage of
+the `Arm Trusted Firmware-A`_ firmware. This provides the reference
+implementation of secure software for Armv8-A, offering PSCI and SMCCC
+services. Allwinner support is fully mainlined. To build bl31.bin::
+
+.. code-block:: sh
+
+ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ cd trusted-firmware-a
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1
+ cp build/sun50i_a64/debug/bl31.bin ${barebox_dir}/firmware/sun50i-a64-bl31.bin
+
+The target platform (``PLAT=``) for A64 and H5 SoCs is sun50i_a64, for the H6
+sun50i_h6, for the H616 sun50i_h616, and for the R329 sun50i_r329.
--
2.47.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/6] clk: divider: add error code propagation
2025-01-07 14:37 ` [PATCH v2 1/6] clk: divider: add error code propagation Jules Maselbas
@ 2025-01-08 14:20 ` Ahmad Fatoum
0 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2025-01-08 14:20 UTC (permalink / raw)
To: Jules Maselbas, barebox
On 07.01.25 15:37, Jules Maselbas wrote:
> divider_get_val can return a negative error code and should not be used
> as a valid divider.
>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> v1->v2:
> - changed value to int and removed ret variable (Ahmad)
>
> drivers/clk/clk-divider.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index ccab70aecc..b0df34e858 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -307,7 +307,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
> {
> struct clk *clk = clk_hw_to_clk(hw);
> struct clk_divider *divider = to_clk_divider(hw);
> - unsigned int value;
> + int value;
> u32 val;
>
> if (divider->flags & CLK_DIVIDER_READ_ONLY)
> @@ -322,6 +322,8 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
>
> value = divider_get_val(rate, parent_rate, divider->table,
> divider->width, divider->flags);
> + if (value < 0)
> + return value;
>
> val = readl(divider->reg);
> val &= ~(clk_div_mask(divider->width) << divider->shift);
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-01-08 14:20 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-01-07 14:37 [PATCH v2 0/6] Initial support for Allwinner A64 SoC Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 1/6] clk: divider: add error code propagation Jules Maselbas
2025-01-08 14:20 ` Ahmad Fatoum
2025-01-07 14:37 ` [PATCH v2 2/6] clk: Add clock driver for sun50i-a64 Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 3/6] pinctrl: Add sun50i-a64 pinctrl driver Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 4/6] mci: Add sunxi-mmc driver Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 5/6] ARM: sunxi: Introduce mach-sunxi Jules Maselbas
2025-01-07 14:37 ` [PATCH v2 6/6] Documentation: sunxi: Add some documentation Jules Maselbas
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