[PATCH 0/5] SoCFPGA: Arria10: sdram: cleanup and fix DDR driver

[PATCH 0/5] SoCFPGA: Arria10: sdram: cleanup and fix DDR driver

[Steffen Trumtrar]

When the L4WD0 is left enabled on startup, depending on handoff files
and its PLL settings, the DDR code might hang while waiting for the
calibration to be successful. Rework this code and cleanup the rest of
the driver a little bit while we are at it.

Tested on an Enclustra PE1 board.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Steffen Trumtrar (5):
      ARM: SoCFPGA: move wait_on_timeout to generic
      ARM: SoCFPGA: arria10-sdram: cleanup emif_clear
      ARM: SoCFPGA: arria10-sdram: cleanup emif_reset
      ARM: SoCFPGA: arria10-sdram: remove workaround
      ARM: SoCFPGA: arria10-sdram: cleanup ddr_setup

 arch/arm/mach-socfpga/arria10-sdram.c | 196 ++++++----------------------------
 arch/arm/mach-socfpga/arria10-xload.c |  16 ---
 include/mach/socfpga/generic.h        |  16 +++
 3 files changed, 46 insertions(+), 182 deletions(-)
---
base-commit: 2afd1a809f1a41f1dd42b95c2bc0ae74853b475b
change-id: 20250303-v2025-02-0-topic-socfpga-arria10-bf2ce013ebcb

Best regards,
-- 
Steffen Trumtrar <s.trumtrar@pengutronix.de>

[PATCH 1/5] ARM: SoCFPGA: move wait_on_timeout to generic

[Steffen Trumtrar]

To be able to use the __wait_on_timeout macro in more places, move it to
the generic socfpga header.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 arch/arm/mach-socfpga/arria10-xload.c | 16 ----------------
 include/mach/socfpga/generic.h        | 16 ++++++++++++++++
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index afec55c33a278f7aa7c13d16557881a5e13f38f9..fb87135ca94a1fd12992bc8e7fb9d1725831aad6 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -16,22 +16,6 @@
 #include <mach/socfpga/generic.h>
 #include <linux/sizes.h>
 
-#define __wait_on_timeout(timeout, condition) \
-({								\
-	int __ret = 0;						\
-	int __timeout = timeout;				\
-								\
-	while ((condition)) {					\
-		if (__timeout-- < 0) {				\
-			__ret = -ETIMEDOUT;			\
-			break;					\
-		}						\
-		arria10_kick_l4wd0();                           \
-                __udelay(1);                                    \
-	}							\
-	__ret;							\
-})
-
 int a10_update_bits(unsigned int reg, unsigned int mask,
 		    unsigned int val)
 {
diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h
index 40224897c1d2e05b934cd49963ac4ddeaeb28a25..9891dbe4fe1016ce0732d635fdd06ae7add16ac3 100644
--- a/include/mach/socfpga/generic.h
+++ b/include/mach/socfpga/generic.h
@@ -106,6 +106,22 @@ static inline void __udelay(unsigned us)
 	for (i = 0; i < us * 3; i++);
 }
 
+#define __wait_on_timeout(timeout, condition) \
+({								\
+	int __ret = 0;						\
+	int __timeout = timeout;				\
+								\
+	while ((condition)) {					\
+		if (__timeout-- < 0) {				\
+			__ret = -ETIMEDOUT;			\
+			break;					\
+		}						\
+		arria10_kick_l4wd0();                           \
+		__udelay(1);                                    \
+	}							\
+	__ret;							\
+})
+
 struct socfpga_barebox_part {
 	unsigned int nor_offset;
 	unsigned int nor_size;

-- 
2.45.2

Re: [PATCH 1/5] ARM: SoCFPGA: move wait_on_timeout to generic

[Ahmad Fatoum]

Hello Steffen,

On 03.03.25 09:59, Steffen Trumtrar wrote:
> To be able to use the __wait_on_timeout macro in more places, move it to
> the generic socfpga header.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
>  arch/arm/mach-socfpga/arria10-xload.c | 16 ----------------
>  include/mach/socfpga/generic.h        | 16 ++++++++++++++++
>  2 files changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
> index afec55c33a278f7aa7c13d16557881a5e13f38f9..fb87135ca94a1fd12992bc8e7fb9d1725831aad6 100644
> --- a/arch/arm/mach-socfpga/arria10-xload.c
> +++ b/arch/arm/mach-socfpga/arria10-xload.c
> @@ -16,22 +16,6 @@
>  #include <mach/socfpga/generic.h>
>  #include <linux/sizes.h>
>  
> -#define __wait_on_timeout(timeout, condition) \
> -({								\
> -	int __ret = 0;						\
> -	int __timeout = timeout;				\
> -								\
> -	while ((condition)) {					\
> -		if (__timeout-- < 0) {				\
> -			__ret = -ETIMEDOUT;			\
> -			break;					\
> -		}						\
> -		arria10_kick_l4wd0();                           \
> -                __udelay(1);                                    \

Unrelated to your patch. But feeding the watchdog every 1us is
a bit excessive, isn't it?

Cheers,
Ahmad

> -	}							\
> -	__ret;							\
> -})
> -
>  int a10_update_bits(unsigned int reg, unsigned int mask,
>  		    unsigned int val)
>  {
> diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h
> index 40224897c1d2e05b934cd49963ac4ddeaeb28a25..9891dbe4fe1016ce0732d635fdd06ae7add16ac3 100644
> --- a/include/mach/socfpga/generic.h
> +++ b/include/mach/socfpga/generic.h
> @@ -106,6 +106,22 @@ static inline void __udelay(unsigned us)
>  	for (i = 0; i < us * 3; i++);
>  }
>  
> +#define __wait_on_timeout(timeout, condition) \
> +({								\
> +	int __ret = 0;						\
> +	int __timeout = timeout;				\
> +								\
> +	while ((condition)) {					\
> +		if (__timeout-- < 0) {				\
> +			__ret = -ETIMEDOUT;			\
> +			break;					\
> +		}						\
> +		arria10_kick_l4wd0();                           \
> +		__udelay(1);                                    \
> +	}							\
> +	__ret;							\
> +})
> +
>  struct socfpga_barebox_part {
>  	unsigned int nor_offset;
>  	unsigned int nor_size;
> 


-- 
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Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 1/5] ARM: SoCFPGA: move wait_on_timeout to generic

[Steffen Trumtrar]

Hi Ahmad,

On 2025-03-03 at 10:12 +01, Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:

> Hello Steffen,
>
> On 03.03.25 09:59, Steffen Trumtrar wrote:
> > To be able to use the __wait_on_timeout macro in more places, move it to
> > the generic socfpga header.
> >
> > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> > ---
> >  arch/arm/mach-socfpga/arria10-xload.c | 16 ----------------
> >  include/mach/socfpga/generic.h        | 16 ++++++++++++++++
> >  2 files changed, 16 insertions(+), 16 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
> > index afec55c33a278f7aa7c13d16557881a5e13f38f9..fb87135ca94a1fd12992bc8e7fb9d1725831aad6 100644
> > --- a/arch/arm/mach-socfpga/arria10-xload.c
> > +++ b/arch/arm/mach-socfpga/arria10-xload.c
> > @@ -16,22 +16,6 @@
> >  #include <mach/socfpga/generic.h>
> >  #include <linux/sizes.h>
> >
> > -#define __wait_on_timeout(timeout, condition) \
> > -({								\
> > -	int __ret = 0;						\
> > -	int __timeout = timeout;				\
> > -								\
> > -	while ((condition)) {					\
> > -		if (__timeout-- < 0) {				\
> > -			__ret = -ETIMEDOUT;			\
> > -			break;					\
> > -		}						\
> > -		arria10_kick_l4wd0();                           \
> > -                __udelay(1);                                    \
>
> Unrelated to your patch. But feeding the watchdog every 1us is
> a bit excessive, isn't it?
>

uuh, yes. That should not be necessary.


Thanks,
Steffen


--
Pengutronix e.K.                | Dipl.-Inform. Steffen Trumtrar |
Steuerwalder Str. 21            | https://www.pengutronix.de/    |
31137 Hildesheim, Germany       | Phone: +49-5121-206917-0       |
Amtsgericht Hildesheim, HRA 2686| Fax:   +49-5121-206917-5555    |

[PATCH 2/5] ARM: SoCFPGA: arria10-sdram: cleanup emif_clear

[Steffen Trumtrar]

Cleanup the emif_clear() function.

Use __wait_on_timeout to kick the watchdog and make the code more readable.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 arch/arm/mach-socfpga/arria10-sdram.c | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
index 70d4edd9736c786729ba59e7ecad7eb7cfe7f77e..da7d3ea685e238c8c9abda84976a1161edfc4b03 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -216,20 +216,14 @@ static int ddr_calibration_es_workaround(void)
 
 static int emif_clear(void)
 {
-	uint32_t s2c;
-	uint32_t i = DDR_MAX_TRIES;
-
 	writel(0, DDR_REG_CORE2SEQ);
-	do {
-		ddr_delay(50);
-		s2c = readl(DDR_REG_SEQ2CORE);
-	} while ((s2c & SEQ2CORE_MASK) && (--i > 0));
 
-	return !i;
+	return __wait_on_timeout(1000, readl(DDR_REG_SEQ2CORE) & SEQ2CORE_MASK);
 }
 static int emif_reset(void)
 {
 	uint32_t c2s, s2c;
+	int ret;
 
 	c2s = readl(DDR_REG_CORE2SEQ);
 	s2c = readl(DDR_REG_SEQ2CORE);
@@ -240,9 +234,12 @@ static int emif_reset(void)
 		readl(IO48_MMR_NIOS2_RESERVE2),
 		readl(IO48_MMR_DRAMSTS));
 
-	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
-		printf("failed emif_clear()\n");
-		return -1;
+	if (s2c & SEQ2CORE_MASK) {
+		ret = emif_clear();
+		if (ret) {
+			printf("failed emif_clear()\n");
+			return -1;
+		}
 	}
 
 	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
@@ -254,7 +251,8 @@ static int emif_reset(void)
 		printf("emif_reset interrupt acknowledged\n");
 	}
 
-	if (emif_clear()) {
+	ret = emif_clear();
+	if (ret) {
 		printf("emif_clear() failed\n");
 		return -3;
 	}

-- 
2.45.2

[PATCH 3/5] ARM: SoCFPGA: arria10-sdram: cleanup emif_reset

[Steffen Trumtrar]

Use the __wait_on_timeout code to poll for EMIF reset.

Be sure to clear EMIF if reset fails before trying again.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 arch/arm/mach-socfpga/arria10-sdram.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
index da7d3ea685e238c8c9abda84976a1161edfc4b03..c28cf50eb55fb97c2dfe52acfbc360784ca3e36b 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -244,13 +244,16 @@ static int emif_reset(void)
 
 	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 
-	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+	ret = __wait_on_timeout(1000000, readl(DDR_REG_SEQ2CORE) &
+				SEQ2CORE_INT_RESP_BIT);
+	if (ret) {
 		printf("emif_reset failed to see interrupt acknowledge\n");
+		emif_clear();
 		return -2;
-	} else {
-		printf("emif_reset interrupt acknowledged\n");
 	}
 
+	__udelay(1000);
+
 	ret = emif_clear();
 	if (ret) {
 		printf("emif_clear() failed\n");

-- 
2.45.2

[PATCH 4/5] ARM: SoCFPGA: arria10-sdram: remove workaround

[Steffen Trumtrar]

Early engineering sample silicon needed a workaround for DDR setup. No
supported board has this early silicion, Altera doesn't have this
workaround in their u-boot. Just get rid of this old code.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 arch/arm/mach-socfpga/arria10-sdram.c | 125 +---------------------------------
 1 file changed, 2 insertions(+), 123 deletions(-)

diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
index c28cf50eb55fb97c2dfe52acfbc360784ca3e36b..c6a86f821473c9990f88906bbe4d52ff8987207c 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -23,9 +23,6 @@
 #define ARRIA10_NIOS_OCT_DONE	BIT(7)
 #define ARRIA10_NIOS_OCT_ACK	7
 
-/* Engineering sample silicon */
-#define ARRIA10_ES_SILICON_VER	0x00010001
-
 #define DDR_REG_SEQ2CORE        0xFFD0507C
 #define DDR_REG_CORE2SEQ        0xFFD05078
 #define DDR_REG_GPOUT           0xFFD03010
@@ -100,27 +97,6 @@ static int is_sdram_cal_success(void)
 	return readl(ARRIA10_ECC_HMC_OCP_DDRCALSTAT);
 }
 
-static unsigned char ddr_get_bit(uint32_t ereg, unsigned char bit)
-{
-	unsigned int reg = readl(ereg);
-
-	return (reg & (1 << bit)) ? 1 : 0;
-}
-
-static unsigned char ddr_wait_bit(uint32_t ereg, uint32_t bit,
-				  uint32_t expected, uint32_t timeout_usec)
-{
-	unsigned int tmr;
-
-	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
-		__udelay(100);
-		if (ddr_get_bit(ereg, bit) == expected)
-			return 0;
-	}
-
-	return 1;
-}
-
 static void ddr_delay(uint32_t delay)
 {
 	int tmr;
@@ -129,91 +105,6 @@ static void ddr_delay(uint32_t delay)
 		__udelay(1000);
 }
 
-/*
- * Diagram of OCT Workaround:
- *
- * EMIF Core                     HPS Processor              OCT FSM
- * =================================================================
- *
- * seq2core      ==============>
- * [0x?????????]   OCT Request   [0xFFD0507C]
- *
- * core2seq
- * [0x?????????] <==============
- *                 OCT Ready     [0xFFD05078]
- *
- *                               [0xFFD03010] ============> Request
- *                                             OCT Request
- *
- *                               [0xFFD03014] <============ Ready
- *                                              OCT Ready
- * Signal definitions:
- *
- * seq2core[7] - OCT calibration request (act-high)
- * core2seq[7] - Signals OCT FSM is ready (active high)
- * gpout[31]   - EMIF Reset override (active low)
- * gpout[30]   - OCT calibration request (act-high)
- * gpin[31]    - OCT calibration ready (act-high)
- */
-
-static int ddr_calibration_es_workaround(void)
-{
-	ddr_delay(500);
-	/* Step 1 - Initiating Reset Sequence */
-	clrbits_le32(DDR_REG_GPOUT, ARRIA10_EMIF_RST);
-	ddr_delay(10);
-
-	/* Step 2 - Clearing registers to EMIF core */
-	writel(0, DDR_REG_CORE2SEQ);	/*Clear the HPS->NIOS COM reg.*/
-
-	/* Step 3 - Clearing registers to OCT core */
-	clrbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ);
-	ddr_delay(5);
-
-	/* Step 4 - Taking EMIF out of reset */
-	setbits_le32(DDR_REG_GPOUT, ARRIA10_EMIF_RST);
-	ddr_delay(10);
-
-	/* Step 5 - Waiting for OCT circuitry to come out of reset */
-	if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 1, 1000000))
-		return -1;
-
-	/* Step 6 - Allowing EMIF to proceed with OCT calibration */
-	setbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
-
-	/* Step 7 - Waiting for EMIF request */
-	if (ddr_wait_bit(DDR_REG_SEQ2CORE, ARRIA10_NIOS_OCT_ACK, 1, 2000000))
-		return -2;
-
-	/* Step 8 - Acknowledging EMIF OCT request */
-	clrbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
-
-	/* Step 9 - Waiting for EMIF response */
-	if (ddr_wait_bit(DDR_REG_SEQ2CORE, ARRIA10_NIOS_OCT_ACK, 0, 2000000))
-		return -3;
-
-	/* Step 10 - Triggering OCT Calibration */
-	setbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ);
-
-	/* Step 11 - Waiting for OCT response */
-	if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 0, 1000))
-		return -4;
-
-	/* Step 12 - Clearing OCT Request bit */
-	clrbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ);
-
-	/* Step 13 - Waiting for OCT Engine */
-	if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 1, 200000))
-		return -5;
-
-	/* Step 14 - Proceeding with EMIF calibration */
-	setbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
-
-	ddr_delay(100);
-
-	return 0;
-}
-
 static int emif_clear(void)
 {
 	writel(0, DDR_REG_CORE2SEQ);
@@ -271,30 +162,18 @@ static int emif_reset(void)
 
 static int arria10_ddr_setup(void)
 {
-	int i, j, retcode, ddr_setup_complete = 0;
-	int chip_version = readl(ARRIA10_SYSMGR_SILICONID1);
+	int i, j, ddr_setup_complete = 0;
 
 	/* Try 3 times to do a calibration */
 	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
-		/* Only engineering sample needs calibration workaround */
-		if (ARRIA10_ES_SILICON_VER == chip_version) {
-			retcode = ddr_calibration_es_workaround();
-			if (retcode) {
-				printf("DDRCAL: Failure: %d\n", retcode);
-				continue;
-			}
-		}
-
 		/* A delay to wait for calibration bit to set */
 		for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
 			ddr_delay(500);
 			ddr_setup_complete = is_sdram_cal_success();
 		}
 
-		if (!ddr_setup_complete &&
-			(ARRIA10_ES_SILICON_VER != chip_version)) {
+		if (!ddr_setup_complete)
 			emif_reset();
-		}
 	}
 
 	if (!ddr_setup_complete) {

-- 
2.45.2

[PATCH 5/5] ARM: SoCFPGA: arria10-sdram: cleanup ddr_setup

[Steffen Trumtrar]

Replace the convoluted loop-in-loop code with ad-hoc polling with
__wait_on_timeout. This makes the code more readable and ensures, that
the L4WD0 is kicked as necessary.

If a calibration fails, restart the EMIF, wait for 500ms for the
calibration to complete and check again. Try this for 32 times.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 arch/arm/mach-socfpga/arria10-sdram.c | 44 +++++++++++------------------------
 1 file changed, 14 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
index c6a86f821473c9990f88906bbe4d52ff8987207c..eeb94277039dae0394aed180f970a9baa1098229 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -91,20 +91,6 @@ static int match_ddr_conf(uint32_t ddr_conf)
 	return 0;
 }
 
-/* Check whether SDRAM is successfully Calibrated */
-static int is_sdram_cal_success(void)
-{
-	return readl(ARRIA10_ECC_HMC_OCP_DDRCALSTAT);
-}
-
-static void ddr_delay(uint32_t delay)
-{
-	int tmr;
-
-	for (tmr = 0; tmr < delay; tmr++)
-		__udelay(1000);
-}
-
 static int emif_clear(void)
 {
 	writel(0, DDR_REG_CORE2SEQ);
@@ -162,26 +148,24 @@ static int emif_reset(void)
 
 static int arria10_ddr_setup(void)
 {
-	int i, j, ddr_setup_complete = 0;
-
-	/* Try 3 times to do a calibration */
-	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
-		/* A delay to wait for calibration bit to set */
-		for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
-			ddr_delay(500);
-			ddr_setup_complete = is_sdram_cal_success();
-		}
+	int i, ret = 0;
 
-		if (!ddr_setup_complete)
-			emif_reset();
-	}
+	/* Try 32 times to do a calibration */
+	for (i = 0; i < 32; i++) {
+		ret = __wait_on_timeout(1000,
+				!(readl(ARRIA10_ECC_HMC_OCP_DDRCALSTAT)	&
+					BIT(0)));
+		if (!ret)
+			return 0;
 
-	if (!ddr_setup_complete) {
-		puts_ll("Error: Could Not Calibrate SDRAM\n");
-		return -1;
+		ret = emif_reset();
+		if (ret)
+			puts_ll("Error: arria10_ddr_setup: Failed to reset EMIF\n");
+
+		__udelay(500000);
 	}
 
-	return 0;
+	return -ETIMEDOUT;
 }
 
 /* Function to startup the SDRAM*/

-- 
2.45.2

Re: [PATCH 0/5] SoCFPGA: Arria10: sdram: cleanup and fix DDR driver

[Sascha Hauer]

On Mon, 03 Mar 2025 09:59:16 +0100, Steffen Trumtrar wrote:
> When the L4WD0 is left enabled on startup, depending on handoff files
> and its PLL settings, the DDR code might hang while waiting for the
> calibration to be successful. Rework this code and cleanup the rest of
> the driver a little bit while we are at it.
> 
> Tested on an Enclustra PE1 board.
> 
> [...]

Applied, thanks!

[1/5] ARM: SoCFPGA: move wait_on_timeout to generic
      https://git.pengutronix.de/cgit/barebox/commit/?id=5080f1eae33d (link may not be stable)
[2/5] ARM: SoCFPGA: arria10-sdram: cleanup emif_clear
      https://git.pengutronix.de/cgit/barebox/commit/?id=7d639315b48c (link may not be stable)
[3/5] ARM: SoCFPGA: arria10-sdram: cleanup emif_reset
      https://git.pengutronix.de/cgit/barebox/commit/?id=41ec8cbd8bfb (link may not be stable)
[4/5] ARM: SoCFPGA: arria10-sdram: remove workaround
      https://git.pengutronix.de/cgit/barebox/commit/?id=da158a7fd07b (link may not be stable)
[5/5] ARM: SoCFPGA: arria10-sdram: cleanup ddr_setup
      https://git.pengutronix.de/cgit/barebox/commit/?id=c97ef53a7eae (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>