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Thu, 20 Mar 2025 02:14:38 -0700 (PDT) Received: from localhost.localdomain ([188.243.23.53]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30c3f0d1bb2sm25999691fa.4.2025.03.20.02.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 02:14:37 -0700 (PDT) From: Alexander Shiyan To: barebox@lists.infradead.org Cc: Alexander Shiyan Date: Thu, 20 Mar 2025 12:14:19 +0300 Message-Id: <20250320091419.42095-7-eagle.alexander923@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250320091419.42095-1-eagle.alexander923@gmail.com> References: <20250320091419.42095-1-eagle.alexander923@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_021440_542157_ADDFC867 X-CRM114-Status: GOOD ( 15.32 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.6 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 7/7] ARM: at91: xload: Add QSPI boot support for SAMA5D2 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) This adds QSPI NOR boot support for sama5d2 CPUs. One first-stage (after ROMboot) xload image can now boot from both MMC and QSPI. Signed-off-by: Alexander Shiyan --- arch/arm/mach-at91/xload.c | 84 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm/mach-at91/xload.c b/arch/arm/mach-at91/xload.c index d3bc6f2dc9..5d8105f07f 100644 --- a/arch/arm/mach-at91/xload.c +++ b/arch/arm/mach-at91/xload.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only #include +#include #include #include #include @@ -96,12 +97,95 @@ static void __noreturn sama5d2_sdhci_start_image(u32 r4) panic("FAT chainloading failed\n"); } +static const struct xload_instance sama5d2_qspi_ioset1_instances[] = { + [0] = { + .base = SAMA5D2_BASE_QSPI0, + .id = SAMA5D2_ID_QSPI0, + .periph = AT91_MUX_PERIPH_B, + .pins = { + AT91_PIN_PA0, AT91_PIN_PA1, AT91_PIN_PA2, + AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, -1 + } + }, + [1] = { + .base = SAMA5D2_BASE_QSPI1, + .id = SAMA5D2_ID_QSPI1, + .periph = AT91_MUX_PERIPH_B, + .pins = { + AT91_PIN_PA6, AT91_PIN_PA7, AT91_PIN_PA8, + AT91_PIN_PA9, AT91_PIN_PA10, AT91_PIN_PA11, -1 + } + }, +}; + +/** + * sama5d2_qspi_start_image - Start an image from QSPI NOR flash + * @r4: value of r4 passed by BootROM + */ +static void __noreturn sama5d2_qspi_start_image(u32 r4) +{ + void __iomem *mem, *dest = IOMEM(SAMA5_DDRCS); + const struct xload_instance *instance; + const s8 *pin; + u32 offs; + int ret; + + ret = sama5_bootsource_instance(r4); + if (ret == 0) + mem = SAMA5D2_BASE_QSPI0_MEM; + else if (ret == 1) + mem = SAMA5D2_BASE_QSPI1_MEM; + else + panic("Couldn't determine boot QSPI instance\n"); + + instance = &sama5d2_qspi_ioset1_instances[ret]; + + sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOA); + for (pin = instance->pins; *pin >= 0; pin++) + at91_mux_pio4_set_periph(SAMA5D2_BASE_PIOA, + BIT(*pin), instance->periph); + + sama5d2_pmc_enable_periph_clock(instance->id); + + /* + * Since we booted from QSPI, we expect the QSPI registers to be + * properly initialized already. + * Let's just read the memory-mapped data. + */ + + /* Find barebox pattern first */ + for (offs = SZ_128K; offs <= SZ_1M; offs += SZ_128K) { + /* Fix cache coherency issue by reading each sector only once */ + memcpy(dest, mem + offs, SZ_128K); + + if (is_barebox_arm_head(dest)) { + u32 size = readl(dest + ARM_HEAD_SIZE_OFFSET); + + pr_info("Image found at 0x%08x, size %u\n", offs, size); + + /* Copy remaining barebox code */ + if (size > SZ_128K) + memcpy(dest + SZ_128K, mem + offs + SZ_128K, + size - SZ_128K); + + sync_caches_for_execution(); + + sama5_boot_xload(dest, r4); + } + } + + panic("No barebox image found!\n"); +} + void __noreturn sama5d2_start_image(u32 r4) { switch (sama5_bootsource(r4)) { case BOOTSOURCE_MMC: sama5d2_sdhci_start_image(r4); break; + case BOOTSOURCE_SPI: + sama5d2_qspi_start_image(r4); + break; default: break; } -- 2.39.1