* [PATCH 2/7] clk: mux: replace width member with mask as in Linux
2025-04-22 7:56 [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Ahmad Fatoum
@ 2025-04-22 7:56 ` Ahmad Fatoum
2025-04-22 7:56 ` [PATCH 3/7] clk: mux: fix mask/width confusion in clk_hw_register_mux Ahmad Fatoum
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2025-04-22 7:56 UTC (permalink / raw)
To: barebox
From: Ahmad Fatoum <a.fatoum@barebox.org>
Linux currently has a mask member in struct clk_mux, whereas barebox has
a width member and we have had bugs due to this already.
Let's switch to what Linux uses for better API compatibility.
No functional change intended.
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
drivers/clk/clk-mux.c | 18 ++++++++++--------
drivers/clk/clk-stm32f4.c | 2 +-
drivers/clk/clk-stm32mp1.c | 8 ++++----
drivers/clk/imx/clk-composite-8m.c | 6 +++---
drivers/clk/imx/clk-composite-93.c | 4 ++--
drivers/clk/rockchip/clk-pll.c | 8 ++++----
drivers/clk/rockchip/clk.c | 4 ++--
include/linux/clk.h | 26 ++++++++++++++++++++++++--
8 files changed, 50 insertions(+), 26 deletions(-)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 1d94e0916732..cb29e3591f4b 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -37,7 +37,10 @@ EXPORT_SYMBOL_GPL(clk_mux_index_to_val);
static int clk_mux_get_parent(struct clk_hw *hw)
{
struct clk_mux *m = to_clk_mux(hw);
- int idx = readl(m->reg) >> m->shift & ((1 << m->width) - 1);
+ u32 idx;
+
+ idx = readl(m->reg) >> m->shift;
+ idx &= m->mask;
return clk_mux_val_to_index(hw, m->table, m->flags, idx);
}
@@ -57,11 +60,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 idx)
idx = clk_mux_index_to_val(m->table, m->flags, idx);
val = readl(m->reg);
- val &= ~(((1 << m->width) - 1) << m->shift);
+ val &= ~(m->mask << m->shift);
val |= idx << m->shift;
if (m->flags & CLK_MUX_HIWORD_MASK)
- val |= ((1 << m->width) - 1) << (m->shift + 16);
+ val |= m->mask << (m->shift + 16);
writel(val, m->reg);
return 0;
@@ -165,7 +168,7 @@ struct clk *clk_mux_alloc(const char *name, unsigned clk_flags, void __iomem *re
m->reg = reg;
m->shift = shift;
- m->width = width;
+ m->mask = (1 << width) - 1;
m->flags = mux_flags;
m->hw.clk.ops = &clk_mux_ops;
m->hw.clk.name = name;
@@ -225,12 +228,11 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev,
struct clk_mux *mux;
struct clk_hw *hw;
struct clk_init_data init = {};
- u8 width = 0;
int ret = -EINVAL;
- width = fls(mask) - ffs(mask) + 1;
-
if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
+ u8 width = fls(mask) - ffs(mask) + 1;
+
if (width + shift > 16) {
pr_err("mux value exceeds LOWORD field\n");
return ERR_PTR(-EINVAL);
@@ -254,7 +256,7 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev,
/* struct clk_mux assignments */
mux->reg = reg;
mux->shift = shift;
- mux->width = width;
+ mux->mask = mask;
mux->flags = clk_mux_flags;
mux->lock = lock;
mux->table = table;
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index d6ccfa6d151e..22c47656c411 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -1081,7 +1081,7 @@ static struct clk_hw *stm32_register_cclk(struct device *dev,
mux->reg = reg;
mux->shift = shift;
- mux->width = 2;
+ mux->mask = 3;
mux->flags = 0;
hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 9ea4c0b83041..bd0badd5899b 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -487,7 +487,7 @@ static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
mmux->mux.reg = cfg->mux->reg_off + base;
mmux->mux.shift = cfg->mux->shift;
- mmux->mux.width = cfg->mux->width;
+ mmux->mux.mask = (1 << cfg->mux->width) - 1;
mmux->mux.flags = cfg->mux->mux_flags;
mmux->mux.table = cfg->mux->table;
mmux->mux.lock = lock;
@@ -502,7 +502,7 @@ static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
mux->reg = cfg->mux->reg_off + base;
mux->shift = cfg->mux->shift;
- mux->width = cfg->mux->width;
+ mux->mask = (1 << cfg->mux->width) - 1;
mux->flags = cfg->mux->mux_flags;
mux->table = cfg->mux->table;
mux->lock = lock;
@@ -735,7 +735,7 @@ struct stm32_pll_obj {
#define FRAC_SHIFT 3
#define FRACLE BIT(16)
#define PLL_MUX_SHIFT 0
-#define PLL_MUX_WIDTH 2
+#define PLL_MUX_MASK 3
static int __pll_is_enabled(struct clk_hw *hw)
{
@@ -878,7 +878,7 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
element->mux.lock = lock;
element->mux.reg = mux_reg;
element->mux.shift = PLL_MUX_SHIFT;
- element->mux.width = PLL_MUX_WIDTH;
+ element->mux.mask = PLL_MUX_MASK;
element->mux.flags = CLK_MUX_READ_ONLY;
element->mux.reg = mux_reg;
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 04d83d208b07..4870aac81265 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -20,7 +20,7 @@
#define PCG_DIV_MAX 64
#define PCG_PCS_SHIFT 24
-#define PCG_PCS_WIDTH 3
+#define PCG_PCS_MASK 0x7
#define PCG_CGC_SHIFT 28
@@ -126,7 +126,7 @@ static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
u32 val;
val = readl(m->reg);
- val &= ~(((1 << m->width) - 1) << m->shift);
+ val &= ~(m->mask << m->shift);
val |= index << m->shift;
/*
@@ -173,7 +173,7 @@ struct clk *imx8m_clk_composite_flags(const char *name,
mux_hw = &mux->hw;
mux->reg = reg;
mux->shift = PCG_PCS_SHIFT;
- mux->width = PCG_PCS_WIDTH;
+ mux->mask = PCG_PCS_MASK;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c
index 2b3753d56937..6ac912fbbb31 100644
--- a/drivers/clk/imx/clk-composite-93.c
+++ b/drivers/clk/imx/clk-composite-93.c
@@ -131,7 +131,7 @@ static int imx93_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
int ret;
reg = readl(mux->reg);
- reg &= ~(((1 << mux->width) - 1) << mux->shift);
+ reg &= ~(mux->mask << mux->shift);
val = val << mux->shift;
reg |= val;
writel(reg, mux->reg);
@@ -165,7 +165,7 @@ struct clk *imx93_clk_composite_flags(const char *name, const char * const *pare
mux_hw = &mux->hw;
mux->reg = reg;
mux->shift = CCM_MUX_SHIFT;
- mux->width = 2;
+ mux->mask = CCM_MUX_MASK;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index b4152b03b19f..64f9e0dc5ea6 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -20,11 +20,11 @@
#include <linux/regmap.h>
#include <linux/iopoll.h>
-#define PLL_MODE_WIDTH 2
+#define PLL_MODE_MASK 0x3
#define PLL_MODE_SLOW 0x0
#define PLL_MODE_NORM 0x1
#define PLL_MODE_DEEP 0x2
-#define PLL_RK3328_MODE_WIDTH 1
+#define PLL_RK3328_MODE_MASK 0x1
struct rockchip_clk_pll {
struct clk_hw hw;
@@ -1086,9 +1086,9 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
pll_mux->reg = ctx->reg_base + mode_offset;
pll_mux->shift = mode_shift;
if (pll_type == pll_rk3328)
- pll_mux->width = PLL_RK3328_MODE_WIDTH;
+ pll_mux->mask = PLL_RK3328_MODE_MASK;
else
- pll_mux->width = PLL_MODE_WIDTH;
+ pll_mux->mask = PLL_MODE_MASK;
pll_mux->flags = 0;
pll_mux->lock = &ctx->lock;
pll_mux->hw.init = &init;
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 180f38e532ba..c833f0961136 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -56,7 +56,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
mux->reg = base + muxdiv_offset;
mux->shift = mux_shift;
- mux->width = mux_width;
+ mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
mux->lock = lock;
mux->hw.clk.name = basprintf("%s.mux", name);
@@ -223,7 +223,7 @@ static struct clk *rockchip_clk_register_frac_branch(
frac_mux->reg = base + child->muxdiv_offset;
frac_mux->shift = child->mux_shift;
- frac_mux->width = child->mux_width;
+ frac_mux->mask = BIT(child->mux_width) - 1;
frac_mux->flags = child->mux_flags;
frac_mux->lock = lock;
frac_mux->hw.init = &init;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 6bedc5204cca..883b1a314688 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -602,11 +602,33 @@ struct clk_fractional_divider {
#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
#define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
+/**
+ * struct clk_mux - multiplexer clock
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register controlling multiplexer
+ * @mask: mask of mutliplexer bit field
+ * @shift: shift to multiplexer bit field
+ * @flags: hardware-specific flags
+ * @table: array of register values corresponding to the parent index
+ * @lock: register lock
+ *
+ * Clock with multiple selectable parents. Implements .get_parent, .set_parent
+ * and .recalc_rate
+ *
+ * Flags:
+ * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
+ * register, and mask of mux bits are in higher 16-bit of this register.
+ * While setting the mux bits, higher 16-bit should also be updated to
+ * indicate changing mux bits.
+ * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
+ * .get_parent clk_op.
+ */
struct clk_mux {
struct clk_hw hw;
void __iomem *reg;
- int shift;
- int width;
+ u32 mask;
+ u8 shift;
unsigned flags;
u32 *table;
spinlock_t *lock;
--
2.39.5
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 3/7] clk: mux: fix mask/width confusion in clk_hw_register_mux
2025-04-22 7:56 [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Ahmad Fatoum
2025-04-22 7:56 ` [PATCH 2/7] clk: mux: replace width member with mask as in Linux Ahmad Fatoum
@ 2025-04-22 7:56 ` Ahmad Fatoum
2025-04-22 7:56 ` [PATCH 4/7] clk: gate: underscore-prefix barebox-specific parent member Ahmad Fatoum
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2025-04-22 7:56 UTC (permalink / raw)
To: barebox
From: Ahmad Fatoum <a.fatoum@barebox.org>
In Linux __clk_hw_register_mux takes a mask argument, while
clk_hw_register_mux expects a width.
Align barebox with this API to fix the bugs in the STM32MP1 and STM32F4
clock drivers, which are the only two making use of this macro so far.
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
include/linux/clk.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 883b1a314688..74802fde4572 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -662,11 +662,12 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev,
spinlock_t *lock);
#define clk_hw_register_mux(dev, name, parent_names, \
- num_parents, flags, reg, shift, mask, \
+ num_parents, flags, reg, shift, width, \
clk_mux_flags, lock) \
__clk_hw_register_mux((dev), (name), (num_parents), \
(parent_names), \
- (flags), (reg), (shift), (mask), \
+ (flags), (reg), \
+ (shift), BIT((width)) - 1, \
(clk_mux_flags), NULL, (lock))
#define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
--
2.39.5
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 4/7] clk: gate: underscore-prefix barebox-specific parent member
2025-04-22 7:56 [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Ahmad Fatoum
2025-04-22 7:56 ` [PATCH 2/7] clk: mux: replace width member with mask as in Linux Ahmad Fatoum
2025-04-22 7:56 ` [PATCH 3/7] clk: mux: fix mask/width confusion in clk_hw_register_mux Ahmad Fatoum
@ 2025-04-22 7:56 ` Ahmad Fatoum
2025-04-22 7:56 ` [PATCH 5/7] clk: gate: add bit_idx member as in Linux Ahmad Fatoum
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2025-04-22 7:56 UTC (permalink / raw)
To: barebox
From: Ahmad Fatoum <a.fatoum@barebox.org>
The parent member is barebox-specific and is set internally on
registration, so make this clearer by making it "private".
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
drivers/clk/clk-gate.c | 4 ++--
include/linux/clk.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index d31920fd0bfe..1de9791499d9 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -72,13 +72,13 @@ struct clk *clk_gate_alloc(const char *name, const char *parent,
{
struct clk_gate *g = xzalloc(sizeof(*g));
- g->parent = parent;
+ g->_parent = parent;
g->reg = reg;
g->shift = shift;
g->hw.clk.ops = &clk_gate_ops;
g->hw.clk.name = name;
g->hw.clk.flags = flags;
- g->hw.clk.parent_names = &g->parent;
+ g->hw.clk.parent_names = &g->_parent;
g->hw.clk.num_parents = 1;
g->flags = clk_gate_flags;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 74802fde4572..9f4e97d37a3a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -689,9 +689,9 @@ struct clk_gate {
struct clk_hw hw;
void __iomem *reg;
int shift;
- const char *parent;
unsigned flags;
spinlock_t *lock;
+ const char *_parent;
};
int clk_gate_is_enabled(struct clk_hw *hw);
--
2.39.5
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 5/7] clk: gate: add bit_idx member as in Linux
2025-04-22 7:56 [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Ahmad Fatoum
` (2 preceding siblings ...)
2025-04-22 7:56 ` [PATCH 4/7] clk: gate: underscore-prefix barebox-specific parent member Ahmad Fatoum
@ 2025-04-22 7:56 ` Ahmad Fatoum
2025-04-22 7:56 ` [PATCH 6/7] clk: composite: change mux/rate/gate members to clk_hw Ahmad Fatoum
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2025-04-22 7:56 UTC (permalink / raw)
To: barebox
From: Ahmad Fatoum <a.fatoum@barebox.org>
Linux calls our shift bit_idx, but they are otherwise identical. Alias
them inside a union to make code a little bit easier to port.
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
include/linux/clk.h | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 9f4e97d37a3a..7ae4c48ca27f 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -685,10 +685,35 @@ unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
long clk_mux_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate);
+/**
+ * struct clk_gate - gating clock
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register controlling gate
+ * @bit_idx: single bit controlling gate
+ * @shift: Alias for @shift
+ * @flags: hardware-specific flags
+ * @lock: register lock
+ * @_parent: for barebox-internal use
+ *
+ * Clock which can gate its output. Implements .enable & .disable
+ *
+ * Flags:
+ * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
+ * enable the clock. Setting this flag does the opposite: setting the bit
+ * disable the clock and clearing it enables the clock
+ * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
+ * of this register, and mask of gate bits are in higher 16-bit of this
+ * register. While setting the gate bits, higher 16-bit should also be
+ * updated to indicate changing gate bits.
+ */
struct clk_gate {
struct clk_hw hw;
void __iomem *reg;
- int shift;
+ union {
+ u8 bit_idx;
+ u8 shift;
+ };
unsigned flags;
spinlock_t *lock;
const char *_parent;
--
2.39.5
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 6/7] clk: composite: change mux/rate/gate members to clk_hw
2025-04-22 7:56 [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Ahmad Fatoum
` (3 preceding siblings ...)
2025-04-22 7:56 ` [PATCH 5/7] clk: gate: add bit_idx member as in Linux Ahmad Fatoum
@ 2025-04-22 7:56 ` Ahmad Fatoum
2025-04-22 7:56 ` [PATCH 7/7] clk: move struct clk_composite definition to header Ahmad Fatoum
2025-04-22 9:18 ` [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2025-04-22 7:56 UTC (permalink / raw)
To: barebox
From: Ahmad Fatoum <a.fatoum@barebox.org>
In preparation for struct clk_composite being public API, change the
members to struct clk_hw type for compatibility with Linux.
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
drivers/clk/clk-composite.c | 86 +++++++++++++++++--------------------
1 file changed, 39 insertions(+), 47 deletions(-)
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index fdf53ce75e62..f69d90e72b4f 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -14,9 +14,9 @@
struct clk_composite {
struct clk_hw hw;
- struct clk *mux_clk;
- struct clk *rate_clk;
- struct clk *gate_clk;
+ struct clk_hw *mux_hw;
+ struct clk_hw *rate_hw;
+ struct clk_hw *gate_hw;
};
#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
@@ -24,30 +24,27 @@ struct clk_composite {
static int clk_composite_get_parent(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
- struct clk *mux_clk = composite->mux_clk;
- struct clk_hw *mux_hw = clk_to_clk_hw(mux_clk);
+ struct clk_hw *mux_hw = composite->mux_hw;
- return mux_clk ? mux_clk->ops->get_parent(mux_hw) : 0;
+ return mux_hw ? mux_hw->clk.ops->get_parent(mux_hw) : 0;
}
static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_composite *composite = to_clk_composite(hw);
- struct clk *mux_clk = composite->mux_clk;
- struct clk_hw *mux_hw = clk_to_clk_hw(mux_clk);
+ struct clk_hw *mux_hw = composite->mux_hw;
- return mux_clk ? mux_clk->ops->set_parent(mux_hw, index) : 0;
+ return mux_hw ? mux_hw->clk.ops->set_parent(mux_hw, index) : 0;
}
static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_composite *composite = to_clk_composite(hw);
- struct clk *rate_clk = composite->rate_clk;
- struct clk_hw *rate_hw = clk_to_clk_hw(rate_clk);
+ struct clk_hw *rate_hw = composite->rate_hw;
- if (rate_clk)
- return rate_clk->ops->recalc_rate(rate_hw, parent_rate);
+ if (rate_hw)
+ return rate_hw->clk.ops->recalc_rate(rate_hw, parent_rate);
return parent_rate;
}
@@ -56,17 +53,16 @@ static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_composite *composite = to_clk_composite(hw);
- struct clk *rate_clk = composite->rate_clk;
- struct clk *mux_clk = composite->mux_clk;
- struct clk_hw *rate_hw = clk_to_clk_hw(rate_clk);
+ struct clk_hw *rate_hw = composite->rate_hw;
+ struct clk_hw *mux_hw = composite->mux_hw;
- if (rate_clk)
- return rate_clk->ops->round_rate(rate_hw, rate, prate);
+ if (rate_hw)
+ return rate_hw->clk.ops->round_rate(rate_hw, rate, prate);
if (!(hw->clk.flags & CLK_SET_RATE_NO_REPARENT) &&
- mux_clk &&
- mux_clk->ops->round_rate)
- return mux_clk->ops->round_rate(clk_to_clk_hw(mux_clk), rate, prate);
+ mux_hw &&
+ mux_hw->clk.ops->round_rate)
+ return mux_hw->clk.ops->round_rate(mux_hw, rate, prate);
return *prate;
}
@@ -75,29 +71,28 @@ static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_composite *composite = to_clk_composite(hw);
- struct clk *rate_clk = composite->rate_clk;
- struct clk *mux_clk = composite->mux_clk;
- struct clk_hw *rate_hw = clk_to_clk_hw(rate_clk);
+ struct clk_hw *rate_hw = composite->rate_hw;
+ struct clk_hw *mux_hw = composite->mux_hw;
/*
* When the rate clock is present use that to set the rate,
* otherwise try the mux clock. We currently do not support
* to find the best rate using a combination of both.
*/
- if (rate_clk)
- return rate_clk->ops->set_rate(rate_hw, rate, parent_rate);
+ if (rate_hw)
+ return rate_hw->clk.ops->set_rate(rate_hw, rate, parent_rate);
if (!(hw->clk.flags & CLK_SET_RATE_NO_REPARENT) &&
- mux_clk &&
- mux_clk->ops->set_rate) {
+ mux_hw &&
+ mux_hw->clk.ops->set_rate) {
/*
* We'll call set_rate on the mux clk which in turn results
* in reparenting the mux clk. Make sure the enable count
* (which is stored in the composite clk, not the mux clk)
* is transferred correctly.
*/
- mux_clk->enable_count = hw->clk.enable_count;
- return mux_clk->ops->set_rate(clk_to_clk_hw(mux_clk), rate, parent_rate);
+ mux_hw->clk.enable_count = hw->clk.enable_count;
+ return mux_hw->clk.ops->set_rate(mux_hw, rate, parent_rate);
}
return 0;
@@ -106,29 +101,26 @@ static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
static int clk_composite_is_enabled(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
- struct clk *gate_clk = composite->gate_clk;
- struct clk_hw *gate_hw = clk_to_clk_hw(gate_clk);
+ struct clk_hw *gate_hw = composite->gate_hw;
- return gate_clk ? gate_clk->ops->is_enabled(gate_hw) : 0;
+ return gate_hw ? gate_hw->clk.ops->is_enabled(gate_hw) : 0;
}
static int clk_composite_enable(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
- struct clk *gate_clk = composite->gate_clk;
- struct clk_hw *gate_hw = clk_to_clk_hw(gate_clk);
+ struct clk_hw *gate_hw = composite->gate_hw;
- return gate_clk ? gate_clk->ops->enable(gate_hw) : 0;
+ return gate_hw ? gate_hw->clk.ops->enable(gate_hw) : 0;
}
static void clk_composite_disable(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
- struct clk *gate_clk = composite->gate_clk;
- struct clk_hw *gate_hw = clk_to_clk_hw(gate_clk);
+ struct clk_hw *gate_hw = composite->gate_hw;
- if (gate_clk)
- gate_clk->ops->disable(gate_hw);
+ if (gate_hw)
+ gate_hw->clk.ops->disable(gate_hw);
}
static struct clk_ops clk_composite_ops = {
@@ -159,18 +151,18 @@ struct clk *clk_register_composite(const char *name,
composite->hw.clk.flags = flags;
composite->hw.clk.parent_names = parent_names;
composite->hw.clk.num_parents = num_parents;
- composite->mux_clk = mux_clk;
- composite->rate_clk = rate_clk;
- composite->gate_clk = gate_clk;
+ composite->mux_hw = clk_to_clk_hw(mux_clk);
+ composite->rate_hw = clk_to_clk_hw(rate_clk);
+ composite->gate_hw = clk_to_clk_hw(gate_clk);
ret = bclk_register(&composite->hw.clk);
if (ret)
goto err;
- if (composite->mux_clk) {
- composite->mux_clk->parents = composite->hw.clk.parents;
- composite->mux_clk->parent_names = composite->hw.clk.parent_names;
- composite->mux_clk->num_parents = composite->hw.clk.num_parents;
+ if (composite->mux_hw) {
+ composite->mux_hw->clk.parents = composite->hw.clk.parents;
+ composite->mux_hw->clk.parent_names = composite->hw.clk.parent_names;
+ composite->mux_hw->clk.num_parents = composite->hw.clk.num_parents;
}
return &composite->hw.clk;
--
2.39.5
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 7/7] clk: move struct clk_composite definition to header
2025-04-22 7:56 [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Ahmad Fatoum
` (4 preceding siblings ...)
2025-04-22 7:56 ` [PATCH 6/7] clk: composite: change mux/rate/gate members to clk_hw Ahmad Fatoum
@ 2025-04-22 7:56 ` Ahmad Fatoum
2025-04-22 9:18 ` [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2025-04-22 7:56 UTC (permalink / raw)
To: barebox
From: Ahmad Fatoum <a.fatoum@barebox.org>
Linux defines struct clk_composite in a header, so clock drivers can
make direct use of it. Do the same for barebox.
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
drivers/clk/clk-composite.c | 12 +-----------
include/linux/clk-provider.h | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index f69d90e72b4f..e8f1fa7a7250 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -8,19 +8,9 @@
#include <common.h>
#include <io.h>
#include <malloc.h>
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/err.h>
-struct clk_composite {
- struct clk_hw hw;
-
- struct clk_hw *mux_hw;
- struct clk_hw *rate_hw;
- struct clk_hw *gate_hw;
-};
-
-#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
-
static int clk_composite_get_parent(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 602e772a54bb..07ccf1d67515 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -31,6 +31,24 @@ static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
val);
}
+/***
+ * struct clk_composite - aggregate clock of mux, divider and gate clocks
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @mux_hw: handle between composite and hardware-specific mux clock
+ * @rate_hw: handle between composite and hardware-specific rate clock
+ * @gate_hw: handle between composite and hardware-specific gate clock
+ */
+struct clk_composite {
+ struct clk_hw hw;
+
+ struct clk_hw *mux_hw;
+ struct clk_hw *rate_hw;
+ struct clk_hw *gate_hw;
+};
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
/**
* struct clk_rate_request - Structure encoding the clk constraints that
* a clock user might require.
--
2.39.5
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared
2025-04-22 7:56 [PATCH 1/7] clk: add compatibility for prepare/unprepare/is_prepared Ahmad Fatoum
` (5 preceding siblings ...)
2025-04-22 7:56 ` [PATCH 7/7] clk: move struct clk_composite definition to header Ahmad Fatoum
@ 2025-04-22 9:18 ` Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2025-04-22 9:18 UTC (permalink / raw)
To: barebox, Ahmad Fatoum
On Tue, 22 Apr 2025 09:56:31 +0200, Ahmad Fatoum wrote:
> Instead of having to mechanically rename prepare/unprepare operations to
> enable/disable, let's just alias them in a union.
>
> This risks code porters missing to merge both operations when they
> exist, but this can be fixed via enforcing -Woverride-init as default
> warning, which will be added separately.
>
> [...]
Applied, thanks!
[1/7] clk: add compatibility for prepare/unprepare/is_prepared
https://git.pengutronix.de/cgit/barebox/commit/?id=6fea0ca457aa (link may not be stable)
[2/7] clk: mux: replace width member with mask as in Linux
https://git.pengutronix.de/cgit/barebox/commit/?id=6f5ac1a7d794 (link may not be stable)
[3/7] clk: mux: fix mask/width confusion in clk_hw_register_mux
https://git.pengutronix.de/cgit/barebox/commit/?id=2d649ed18181 (link may not be stable)
[4/7] clk: gate: underscore-prefix barebox-specific parent member
https://git.pengutronix.de/cgit/barebox/commit/?id=76d9b8462bba (link may not be stable)
[5/7] clk: gate: add bit_idx member as in Linux
https://git.pengutronix.de/cgit/barebox/commit/?id=8a8c08dd1d30 (link may not be stable)
[6/7] clk: composite: change mux/rate/gate members to clk_hw
https://git.pengutronix.de/cgit/barebox/commit/?id=88c47e010a65 (link may not be stable)
[7/7] clk: move struct clk_composite definition to header
https://git.pengutronix.de/cgit/barebox/commit/?id=e7fe93bd5fe2 (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply [flat|nested] 8+ messages in thread