[PATCH] clk: rockchip: Fix CPLL setup on RK3588

[Alexander Shiyan <eagle.alexander923@gmail.com>]

This patch fixes the CPLL clock setup issue on RK3588 SoCs by temporarily
disabling the PLL source during PLL configuration. The fix is ported from
Rockchip's U-Boot implementation [1].

The issue occurs because CPLL requires its source to be disabled during
configuration. We temporarily set the corresponding bit in the CRU
register before PLL setup and restore it afterwards [2].

References:
[1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81
[2] https://github.com/rockchip-linux/u-boot/commit/7560cacdd3a68bb475f23b4249a98025c89064d4

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 drivers/clk/rockchip/clk-pll.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 904d70d5d4..8ac052ee07 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -923,6 +923,7 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
 	struct clk_mux *pll_mux = &pll->pll_mux;
 	struct rockchip_pll_rate_table cur;
 	int rate_change_remuxed = 0;
+	bool is_cpll = false;
 	int cur_parent;
 	int ret;
 
@@ -938,6 +939,17 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
 			pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 			rate_change_remuxed = 1;
 		}
+
+		/*
+		 * CPLL on RK3588 requires the PLL source to be disabled during
+		 * configuration. We temporarily disable it here and restore
+		 * the original state after PLL setup.
+		 */
+		is_cpll = (pll->reg_base - pll->ctx->reg_base == 0x1a0);
+		if (is_cpll) {
+			writel(HIWORD_UPDATE(BIT(1), BIT(1), 0),
+			       pll->ctx->reg_base + 0x84c);
+		}
 	}
 
 	/* set pll power down */
@@ -971,6 +983,17 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
 	if ((pll->type == pll_rk3588) && rate_change_remuxed)
 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 
+	if (is_cpll) {
+		/*
+		 * Restore CPLL source clock setting after PLL configuration.
+		 * This ensures the clock source returns to its original state
+		 * now that the PLL is properly configured and can maintain
+		 * stability without the temporary disablement.
+		 */
+		writel(HIWORD_UPDATE(0, BIT(1), 0),
+		       pll->ctx->reg_base + 0x84c);
+	}
+
 	return ret;
 }
 
-- 
2.38.2