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Mon, 29 Sep 2025 05:32:50 -0700 (PDT) Received: from localhost.localdomain ([95.161.221.172]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-36fb4772c97sm27311421fa.6.2025.09.29.05.32.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 05:32:50 -0700 (PDT) From: Alexander Shiyan To: barebox@lists.infradead.org Cc: Alexander Shiyan Date: Mon, 29 Sep 2025 15:32:39 +0300 Message-Id: <20250929123239.838390-1-eagle.alexander923@gmail.com> X-Mailer: git-send-email 2.38.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250929_053253_819735_37CC16FE X-CRM114-Status: GOOD ( 14.41 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.4 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH] clk: rockchip: Fix CPLL setup on RK3588 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) This patch fixes the CPLL clock setup issue on RK3588 SoCs by temporarily disabling the PLL source during PLL configuration. The fix is ported from Rockchip's U-Boot implementation [1]. The issue occurs because CPLL requires its source to be disabled during configuration. We temporarily set the corresponding bit in the CRU register before PLL setup and restore it afterwards [2]. References: [1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81 [2] https://github.com/rockchip-linux/u-boot/commit/7560cacdd3a68bb475f23b4249a98025c89064d4 Signed-off-by: Alexander Shiyan --- drivers/clk/rockchip/clk-pll.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 904d70d5d4..8ac052ee07 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -923,6 +923,7 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, struct clk_mux *pll_mux = &pll->pll_mux; struct rockchip_pll_rate_table cur; int rate_change_remuxed = 0; + bool is_cpll = false; int cur_parent; int ret; @@ -938,6 +939,17 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); rate_change_remuxed = 1; } + + /* + * CPLL on RK3588 requires the PLL source to be disabled during + * configuration. We temporarily disable it here and restore + * the original state after PLL setup. + */ + is_cpll = (pll->reg_base - pll->ctx->reg_base == 0x1a0); + if (is_cpll) { + writel(HIWORD_UPDATE(BIT(1), BIT(1), 0), + pll->ctx->reg_base + 0x84c); + } } /* set pll power down */ @@ -971,6 +983,17 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, if ((pll->type == pll_rk3588) && rate_change_remuxed) pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + if (is_cpll) { + /* + * Restore CPLL source clock setting after PLL configuration. + * This ensures the clock source returns to its original state + * now that the PLL is properly configured and can maintain + * stability without the temporary disablement. + */ + writel(HIWORD_UPDATE(0, BIT(1), 0), + pll->ctx->reg_base + 0x84c); + } + return ret; } -- 2.38.2