From: Alexander Shiyan <eagle.alexander923@gmail.com>
To: barebox@lists.infradead.org
Cc: Alexander Shiyan <eagle.alexander923@gmail.com>
Subject: [PATCH 2/2] ARM: dts: rockchip: Set CPLL frequency for RK3588
Date: Mon, 29 Sep 2025 16:58:57 +0300 [thread overview]
Message-ID: <20250929135857.965181-2-eagle.alexander923@gmail.com> (raw)
In-Reply-To: <20250929135857.965181-1-eagle.alexander923@gmail.com>
Explicitly configure CPLL frequency to 1500 MHz to ensure system
stability and reliable operation.
The change aligns with Rockchip's recommended practices for clock
configuration in embedded systems using RK3588 SoCs.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
arch/arm/dts/rk3588.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
index 416700cf0e..42d692a9bd 100644
--- a/arch/arm/dts/rk3588.dtsi
+++ b/arch/arm/dts/rk3588.dtsi
@@ -1,6 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/ {
+ assigned-clocks = <&cru PLL_CPLL>;
+ assigned-clock-rates = <1500000000>;
+
dmc: memory-controller {
compatible = "rockchip,rk3588-dmc";
rockchip,pmu = <&pmu1grf>;
--
2.38.2
next prev parent reply other threads:[~2025-09-29 13:59 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-29 13:58 [PATCH 1/2] ARM: dts: rockchip: Set initial CPU frequencies " Alexander Shiyan
2025-09-29 13:58 ` Alexander Shiyan [this message]
2025-10-01 14:06 ` [PATCH 2/2] ARM: dts: rockchip: Set CPLL frequency " Michael Tretter
2025-10-06 11:50 ` Alexander Shiyan
2025-09-30 5:56 ` [PATCH 1/2] ARM: dts: rockchip: Set initial CPU frequencies " Sascha Hauer
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