[PATCH 3/4] arm: socfpga: mailbox_s10: add error messages for QSPI

[Michael Tretter <m.tretter@pengutronix.de>]

The mailbox commands may fail. For example, the SDM may prevent direct
access from the HPS to the QSPI.

Print error messages to help the developer in debugging these issues.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/mailbox_s10.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index f6aacd5551f2..ff2f261014b2 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -311,22 +311,29 @@ int socfpga_mailbox_s10_qspi_open(void)
 		socfpga_mailbox_s10_qspi_close();
 		goto retry;
 	}
-	if (ret)
+	if (ret) {
+		pr_err("QSPI: QSPI_OPEN failed: 0x%x\n", ret);
 		return ret;
+	}
 
 	/* HPS will directly control the QSPI controller, no longer mailbox */
 	ret = mbox_send_cmd(MBOX_ID_BAREBOX, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
 			    0, NULL, 0, &resp_buf_len, resp_buf);
-	if (ret)
+	if (ret) {
+		pr_err("QSPI: QSPI_DIRECT failed: 0x%x\n", ret);
 		goto error;
+	}
 
 	/* Get the QSPI clock from SDM response and save for later use */
 	clk_khz = resp_buf[0];
-	if (clk_khz < 1000)
+	if (clk_khz < 1000) {
+		pr_err("QSPI: Unexpected reference clock rate: %d kHz\n",
+		       clk_khz);
 		return -EINVAL;
+	}
 
 	clk_khz /= 1000;
-	pr_info("QSPI: reference clock at %d kHZ\n", clk_khz);
+	pr_info("QSPI: reference clock at %d kHz\n", clk_khz);
 
 	reg = (readl(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
 			~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);

-- 
2.47.3