From: Sascha Hauer <s.hauer@pengutronix.de>
To: BAREBOX <barebox@lists.infradead.org>
Subject: [PATCH 5/6] ARM: rockchip: separate physical DRAM start from usable start
Date: Fri, 20 Mar 2026 09:31:21 +0100 [thread overview]
Message-ID: <20260320-compressed-firmware-rockchip-v1-5-7d03c7e39d2f@pengutronix.de> (raw)
In-Reply-To: <20260320-compressed-firmware-rockchip-v1-0-7d03c7e39d2f@pengutronix.de>
The RK3xxx_DRAM_BOTTOM macros define the first usable DRAM address, that
is the physical DRAM start plus the offset occupied by the TF-A. With
upcoming PBL mmu support we need both addresses, so separate them.
We use RK3xxx_DRAM_START for the physical start and add
ROCKCHIP_DRAM_TFA_CARVE_OUT where needed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-rockchip/dmc.c | 24 ++++++++++++------------
include/mach/rockchip/atf.h | 24 +++++++++++++-----------
2 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
index 318e99d8ba..9218f794f9 100644
--- a/arch/arm/mach-rockchip/dmc.c
+++ b/arch/arm/mach-rockchip/dmc.c
@@ -160,13 +160,13 @@ static size_t rockchip_ram(phys_addr_t membase, resource_size_t memsize,
* RK3576 has internal registers below the DRAM start and thus
* doesn't need any gaps in the DRAM space.
*/
- base[0] = membase;
+ base[0] = membase + ROCKCHIP_DRAM_TFA_CARVE_OUT;
size[0] = memsize;
return 1;
}
- base[i] = membase;
+ base[i] = membase + ROCKCHIP_DRAM_TFA_CARVE_OUT;
size[i] = min_t(resource_size_t, RK3588_INT_REG_START, memsize) - membase;
i++;
@@ -202,7 +202,7 @@ size_t rk3399_ram_sizes(phys_addr_t *base, resource_size_t *size, size_t n)
pr_debug("%s() = %llu\n", __func__, (u64)size);
- return rockchip_ram(RK3399_DRAM_BOTTOM, memsize, RK3399_INT_REG_START, base, size, n);
+ return rockchip_ram(RK3399_DRAM_START, memsize, RK3399_INT_REG_START, base, size, n);
}
size_t rk3562_ram_sizes(phys_addr_t *base, resource_size_t *size, size_t n)
@@ -218,7 +218,7 @@ size_t rk3562_ram_sizes(phys_addr_t *base, resource_size_t *size, size_t n)
pr_debug("%s() = %llu\n", __func__, (u64)memsize);
- return rockchip_ram(RK3562_DRAM_BOTTOM, memsize, RK3562_INT_REG_START, base, size, n);
+ return rockchip_ram(RK3562_DRAM_START, memsize, RK3562_INT_REG_START, base, size, n);
}
size_t rk3568_ram_sizes(phys_addr_t *base, resource_size_t *size, size_t n)
@@ -234,7 +234,7 @@ size_t rk3568_ram_sizes(phys_addr_t *base, resource_size_t *size, size_t n)
pr_debug("%s() = %llu\n", __func__, (u64)memsize);
- return rockchip_ram(RK3568_DRAM_BOTTOM, memsize, RK3568_INT_REG_START, base, size, n);
+ return rockchip_ram(RK3568_DRAM_START, memsize, RK3568_INT_REG_START, base, size, n);
}
size_t rk3576_ram_sizes(phys_addr_t *base, resource_size_t *size, size_t n)
@@ -250,7 +250,7 @@ size_t rk3576_ram_sizes(phys_addr_t *base, resource_size_t *size, size_t n)
pr_debug("%s() = %llu\n", __func__, (u64)size);
- return rockchip_ram(RK3576_DRAM_BOTTOM, memsize, RK3576_INT_REG_START, base, size, n);
+ return rockchip_ram(RK3576_DRAM_START, memsize, RK3576_INT_REG_START, base, size, n);
}
#define RK3588_PMUGRF_BASE 0xfd58a000
@@ -277,7 +277,7 @@ size_t rk3588_ram_sizes(phys_addr_t *base, resource_size_t *size, size_t n)
memsize = size1 + size2;
- return rockchip_ram(RK3588_DRAM_BOTTOM, memsize, RK3588_INT_REG_START, base, size, n);
+ return rockchip_ram(RK3588_DRAM_START, memsize, RK3588_INT_REG_START, base, size, n);
}
static int rockchip_dmc_probe(struct device *dev)
@@ -335,28 +335,28 @@ static const struct rockchip_dmc_drvdata rk3399_drvdata = {
.os_reg2 = RK3399_PMUGRF_OS_REG2,
.os_reg3 = RK3399_PMUGRF_OS_REG3,
.internal_registers_start = RK3399_INT_REG_START,
- .membase = RK3399_DRAM_BOTTOM,
+ .membase = RK3399_DRAM_START,
};
static const struct rockchip_dmc_drvdata rk3562_drvdata = {
.os_reg2 = RK3562_PMUGRF_OS_REG2,
.os_reg3 = RK3562_PMUGRF_OS_REG3,
.internal_registers_start = RK3562_INT_REG_START,
- .membase = RK3562_DRAM_BOTTOM,
+ .membase = RK3562_DRAM_START,
};
static const struct rockchip_dmc_drvdata rk3568_drvdata = {
.os_reg2 = RK3568_PMUGRF_OS_REG2,
.os_reg3 = RK3568_PMUGRF_OS_REG3,
.internal_registers_start = RK3568_INT_REG_START,
- .membase = RK3568_DRAM_BOTTOM,
+ .membase = RK3568_DRAM_START,
};
static const struct rockchip_dmc_drvdata rk3576_drvdata = {
.os_reg2 = RK3576_PMUGRF_OS_REG2,
.os_reg3 = RK3576_PMUGRF_OS_REG3,
.internal_registers_start = RK3576_INT_REG_START,
- .membase = RK3576_DRAM_BOTTOM,
+ .membase = RK3576_DRAM_START,
};
static const struct rockchip_dmc_drvdata rk3588_drvdata = {
@@ -365,7 +365,7 @@ static const struct rockchip_dmc_drvdata rk3588_drvdata = {
.os_reg4 = RK3588_PMUGRF_OS_REG4,
.os_reg5 = RK3588_PMUGRF_OS_REG5,
.internal_registers_start = RK3588_INT_REG_START,
- .membase = RK3588_DRAM_BOTTOM,
+ .membase = RK3588_DRAM_START,
};
static struct of_device_id rockchip_dmc_dt_ids[] = {
diff --git a/include/mach/rockchip/atf.h b/include/mach/rockchip/atf.h
index 5454d394a1..c2daaa662c 100644
--- a/include/mach/rockchip/atf.h
+++ b/include/mach/rockchip/atf.h
@@ -3,12 +3,14 @@
#ifndef __MACH_ATF_H
#define __MACH_ATF_H
-/* First usable DRAM address. Lower mem is used for ATF and OP-TEE */
-#define RK3399_DRAM_BOTTOM 0xa00000
-#define RK3562_DRAM_BOTTOM 0xa00000
-#define RK3568_DRAM_BOTTOM 0xa00000
-#define RK3576_DRAM_BOTTOM 0x40a00000
-#define RK3588_DRAM_BOTTOM 0xa00000
+/* The first 10MiB of DRAM are used by the TF-A */
+#define ROCKCHIP_DRAM_TFA_CARVE_OUT 0xa00000
+
+#define RK3399_DRAM_START 0x0
+#define RK3562_DRAM_START 0x0
+#define RK3568_DRAM_START 0x0
+#define RK3576_DRAM_START 0x40000000
+#define RK3588_DRAM_START 0x0
/*
* The tee.bin image has an OP-TEE specific header that describes the
@@ -36,11 +38,11 @@
* board lowlevel code should relocate barebox here. This is where
* OP-TEE jumps to after initialization.
*/
-#define RK3399_BAREBOX_LOAD_ADDRESS (RK3399_DRAM_BOTTOM + 1024*1024)
-#define RK3562_BAREBOX_LOAD_ADDRESS (RK3562_DRAM_BOTTOM + 1024*1024)
-#define RK3568_BAREBOX_LOAD_ADDRESS (RK3568_DRAM_BOTTOM + 1024*1024)
-#define RK3576_BAREBOX_LOAD_ADDRESS (RK3576_DRAM_BOTTOM + 1024*1024)
-#define RK3588_BAREBOX_LOAD_ADDRESS (RK3588_DRAM_BOTTOM + 1024*1024)
+#define RK3399_BAREBOX_LOAD_ADDRESS (RK3399_DRAM_START + ROCKCHIP_DRAM_TFA_CARVE_OUT + 1024*1024)
+#define RK3562_BAREBOX_LOAD_ADDRESS (RK3562_DRAM_START + ROCKCHIP_DRAM_TFA_CARVE_OUT + 1024*1024)
+#define RK3568_BAREBOX_LOAD_ADDRESS (RK3568_DRAM_START + ROCKCHIP_DRAM_TFA_CARVE_OUT + 1024*1024)
+#define RK3576_BAREBOX_LOAD_ADDRESS (RK3576_DRAM_START + ROCKCHIP_DRAM_TFA_CARVE_OUT + 1024*1024)
+#define RK3588_BAREBOX_LOAD_ADDRESS (RK3588_DRAM_START + ROCKCHIP_DRAM_TFA_CARVE_OUT + 1024*1024)
void __noreturn rk3562_barebox_entry(void *fdt);
void __noreturn rk3568_barebox_entry(void *fdt);
--
2.47.3
next prev parent reply other threads:[~2026-03-20 8:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-20 8:31 [PATCH 0/6] Rockchip: Enable MMU before uncompressing TF-A and OP-TEE Sascha Hauer
2026-03-20 8:31 ` [PATCH 1/6] ARM: rockchip: dmc: rework DRAM functions Sascha Hauer
2026-03-20 8:31 ` [PATCH 2/6] ARM: rockchip: atf: make all memory banks available Sascha Hauer
2026-03-20 8:31 ` [PATCH 3/6] ARM: rockchip: atf: add OP-TEE fdt creation function for all SoCs Sascha Hauer
2026-03-20 8:31 ` [PATCH 4/6] ARM: Rockchip: Drop rk3xxx_atf_load_bl31() Sascha Hauer
2026-03-20 8:31 ` Sascha Hauer [this message]
2026-03-20 8:31 ` [PATCH 6/6] ARM: rockchip: atf: enable MMU in PBL Sascha Hauer
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