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This series wires up the controller's ADMA2 engine, adds HS400/HS400ES, and lets the PBL loader use DMA, with a Kconfig choice (PIO/SDMA/ADMA2) for both barebox-proper and the PBL so the existing behaviour stays the default. The series is in three parts: - Three preparatory fixes (1-3), each independently useful and safe to apply on their own: a NULL-safe dma_mapping_error() (a 2-line guard in include/dma.h matching the existing cpu_to_dma()/dma_to_cpu() helpers -- the PBL SDHCI path calls it with no struct device), aborting the SDHCI transfer wait on error instead of spinning to the timeout (affects all SDHCI controllers; strict improvement), and the SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC / NO_ENDATTR_IN_NOPDESC quirks for the shared ADMA2 table builder (no-op until a host opts in, mirroring Linux). Patch 1 is the only non-mci/ change; it is a prerequisite for the PBL DMA path but stands alone. - The i.MX opt-in + HS400 (4-5): the uSDHC marks the two ADMA2 descriptor quirks, and HS400/HS400ES is implemented (strobe DLL, timing path, caps). - ADMA2 enablement (6-7): a transfer-mode choice that wires sdhci_setup_adma() into probe, and DMA support in the i.MX8M/8MP PBL eMMC loader. One non-obvious detail worth flagging: on i.MX8MP the PBL loader issues a PIO EXT_CSD read (to pick the active boot partition) before the bulk transfer, and a PIO transfer immediately preceding the first ADMA transfer wedges the uSDHC ADMA engine (hard hang, no completion or error IRQ). The PBL loader therefore sets up DMA before that read so it also goes through ADMA. i.MX8MM is not affected -- its loader has no such pre-read, so ADMA is its first transfer. Measurements ------------ Time to load the ~1.6 MiB next-stage barebox image in the PBL, and to read the FIT in barebox-proper. "DMA" is ADMA2; SDMA is indistinguishable from ADMA2 (the transfer is bus-bound) -- on i.MX8MP the proper-stage FIT read is 387 ms with SDMA vs 391 ms with ADMA2. i.MX8MM (gs05): PBL next-stage load: PIO 559 ms -> DMA 21 ms proper FIT read: PIO 738 ms -> DMA 321 ms (HS400) i.MX8MP (ts20): PBL next-stage load: PIO 278 ms -> DMA 85 ms proper FIT read: SDMA 387 ms ~= ADMA2 391 ms (HS400) The PBL transfers the card at whatever speed the BootROM left it, so the absolute PBL numbers differ between boards (same ~1.6 MiB payload); DMA beats PIO on both. In barebox-proper SDMA and ADMA2 are equivalent, as the i.MX8MP figures show -- so SDMA remains a fine default and ADMA2 is opt-in. Testing ------- Boot-tested with PBL=ADMA2 and proper=ADMA2 (and the SDMA/PIO fallbacks) on: - i.MX8MM eMMC board (HS400ES) - i.MX8MP eMMC board (HS400) Large reads verified against known checksums; the PBL loader falls back to PIO if a DMA attempt fails, so a misconfigured board still boots. Johannes Schneider (7): dma: make dma_mapping_error() NULL-safe mci: sdhci: bail out on ADMA/transfer errors instead of hanging mci: sdhci: honor BROKEN_ADMA_ZEROLEN_DESC / NO_ENDATTR_IN_NOPDESC quirks mci: imx-esdhc: mark the uSDHC ADMA2 descriptor quirks mci: imx-esdhc: support HS400 and HS400ES on i.MX8M mci: imx-esdhc: make the transfer mode selectable (PIO/SDMA/ADMA2) mci: imx-esdhc: support DMA in the i.MX8M PBL eMMC loader drivers/mci/Kconfig | 40 +++++++++++++++-- drivers/mci/imx-esdhc-common.c | 28 +++++++++--- drivers/mci/imx-esdhc-pbl.c | 68 ++++++++++++++++++++++++++--- drivers/mci/imx-esdhc.c | 98 ++++++++++++++++++++++++++++++++++++++++-- drivers/mci/imx-esdhc.h | 14 ++++++ drivers/mci/sdhci.c | 43 +++++++++++++----- drivers/mci/sdhci.h | 5 +++ include/dma.h | 2 +- 8 files changed, 268 insertions(+), 30 deletions(-) -- 2.43.0