* imx7d enable second core
@ 2019-10-15 11:29 Giorgio Dal Molin
2019-10-15 11:37 ` Ahmad Fatoum
0 siblings, 1 reply; 14+ messages in thread
From: Giorgio Dal Molin @ 2019-10-15 11:29 UTC (permalink / raw)
To: barebox
Hi,
can anyone please confirm that a recent barebox version (v2019.10 or v2019.09)
is able to boot a linux kernel so that it can enable the second cpu core ?
It actually used to work in the past but now I only get one core running:
Loading ARM Linux zImage '/mnt/boot/kernel.img'
Loading devicetree from '/mnt/boot/devtree.dtb'
commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0:armgdm:eth0: root=PARTUUID=abd2f9f6-88e5-4657-a5fb-aeb2cc6fde7e rootwait video=HDMI-A-1:1024x768M@60 console=tty1
Starting kernel in nonsecure mode
[ 0.000000] 000: Booting Linux on physical CPU 0x0
[ 0.000000] 000: Linux version 5.2.19-rt11-00268-g0308d71d8410-dirty (giorgio@BVblfs) (gcc version 9.2.1 20190813 (OSELAS.Toolchain 9.2.1)) #1 SMP PREEMPT RT Thu Oct 10 07:50:01 CEST 2019
[ 0.000000] 000: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
[ 0.000000] 000: CPU: div instructions available: patching division code
[ 0.000000] 000: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] 000: OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
[ 0.000000] 000: Memory policy: Data cache writealloc
[ 0.000000] 000: cma: Reserved 64 MiB at 0xac000000
[ 0.000000] 000: percpu: Embedded 10 pages/cpu s19296 r0 d21664 u40960
[ 0.000000] 000: Built 1 zonelists, mobility grouping on. Total pages: 260608
[ 0.000000] 000: Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0:armgdm:eth0: root=PARTUUID=abd2f9f6-88e5-4657-a5fb-aeb2cc6fde7e rootwait video=HDMI-A-1:1024x768M@60 console=tty1
[ 0.000000] 000: Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
[ 0.000000] 000: Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] 000: Memory: 958252K/1048576K available (9216K kernel code, 403K rwdata, 2308K rodata, 1024K init, 719K bss, 24788K reserved, 65536K cma-reserved, 261700K highmem)
[ 0.000000] 000: SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[ 0.000000] 000: rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] 000: rcu: RCU priority boosting: priority 1 delay 500 ms.
[ 0.000000] 000: rcu: RCU_SOFTIRQ processing moved to rcuc kthreads.
[ 0.000000] 000: No expedited grace period (rcu_normal_after_boot).
[ 0.000000] 000: Tasks RCU enabled.
[ 0.000000] 000: rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[ 0.000000] 000: NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] 000: rcu: Offload RCU callbacks from CPUs: (none).
[ 0.000000] 000: arch_timer: cp15 timer(s) running at 8.00MHz (virt).
[ 0.000000] 000: clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
[ 0.000001] 000: sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
[ 0.000012] 000: Switching to timer-based delay loop, resolution 125ns
[ 0.000433] 000: Switching to timer-based delay loop, resolution 41ns
[ 0.000445] 000: sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
[ 0.000456] 000: clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[ 0.001625] 000: Console: colour dummy device 80x30
[ 0.001638] 000: printk: console [tty1] enabled
[ 0.001673] 000: Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
[ 0.001680] 000: pid_max: default: 32768 minimum: 301
[ 0.001816] 000: Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.001833] 000: Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.002543] 000: CPU: Testing write buffer coherency: ok
[ 0.002896] 000: CPU0: update cpu_capacity 1024
[ 0.002908] 000: CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.060000] 000: Setting up static identity map for 0x80100000 - 0x8010003c
[ 0.079971] 000: rcu: Hierarchical SRCU implementation.
[ 0.160105] 000: smp: Bringing up secondary CPUs ...
[ 0.280352] 000: smp: Brought up 1 node, 1 CPU
[ 0.280362] 000: SMP: Total of 1 processors activated (48.00 BogoMIPS).
[ 0.280370] 000: CPU: All CPU(s) started in SVC mode.
[ 0.281280] 000: devtmpfs: initialized
giorgio
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: imx7d enable second core
2019-10-15 11:29 imx7d enable second core Giorgio Dal Molin
@ 2019-10-15 11:37 ` Ahmad Fatoum
2019-10-15 11:51 ` Ahmad Fatoum
2019-10-15 12:11 ` Giorgio Dal Molin
0 siblings, 2 replies; 14+ messages in thread
From: Ahmad Fatoum @ 2019-10-15 11:37 UTC (permalink / raw)
To: barebox
On 10/15/19 1:29 PM, Giorgio Dal Molin wrote:
> Hi,
>
> can anyone please confirm that a recent barebox version (v2019.10 or v2019.09)
> is able to boot a linux kernel so that it can enable the second cpu core ?
If you #define DEBUG in arch/arm/cpu/psci.c, a smc command is enabled that can
be used to test ARM_PSCI_0_2_CPU_ON. This might aid you in your debug effort.
Cheers
Ahmad
> It actually used to work in the past but now I only get one core running:
>
> Loading ARM Linux zImage '/mnt/boot/kernel.img'
> Loading devicetree from '/mnt/boot/devtree.dtb'
> commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0:armgdm:eth0: root=PARTUUID=abd2f9f6-88e5-4657-a5fb-aeb2cc6fde7e rootwait video=HDMI-A-1:1024x768M@60 console=tty1
> Starting kernel in nonsecure mode
> [ 0.000000] 000: Booting Linux on physical CPU 0x0
> [ 0.000000] 000: Linux version 5.2.19-rt11-00268-g0308d71d8410-dirty (giorgio@BVblfs) (gcc version 9.2.1 20190813 (OSELAS.Toolchain 9.2.1)) #1 SMP PREEMPT RT Thu Oct 10 07:50:01 CEST 2019
> [ 0.000000] 000: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
> [ 0.000000] 000: CPU: div instructions available: patching division code
> [ 0.000000] 000: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
> [ 0.000000] 000: OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
> [ 0.000000] 000: Memory policy: Data cache writealloc
> [ 0.000000] 000: cma: Reserved 64 MiB at 0xac000000
> [ 0.000000] 000: percpu: Embedded 10 pages/cpu s19296 r0 d21664 u40960
> [ 0.000000] 000: Built 1 zonelists, mobility grouping on. Total pages: 260608
> [ 0.000000] 000: Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0:armgdm:eth0: root=PARTUUID=abd2f9f6-88e5-4657-a5fb-aeb2cc6fde7e rootwait video=HDMI-A-1:1024x768M@60 console=tty1
> [ 0.000000] 000: Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
> [ 0.000000] 000: Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
> [ 0.000000] 000: Memory: 958252K/1048576K available (9216K kernel code, 403K rwdata, 2308K rodata, 1024K init, 719K bss, 24788K reserved, 65536K cma-reserved, 261700K highmem)
> [ 0.000000] 000: SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> [ 0.000000] 000: rcu: Preemptible hierarchical RCU implementation.
> [ 0.000000] 000: rcu: RCU priority boosting: priority 1 delay 500 ms.
> [ 0.000000] 000: rcu: RCU_SOFTIRQ processing moved to rcuc kthreads.
> [ 0.000000] 000: No expedited grace period (rcu_normal_after_boot).
> [ 0.000000] 000: Tasks RCU enabled.
> [ 0.000000] 000: rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
> [ 0.000000] 000: NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
> [ 0.000000] 000: rcu: Offload RCU callbacks from CPUs: (none).
> [ 0.000000] 000: arch_timer: cp15 timer(s) running at 8.00MHz (virt).
> [ 0.000000] 000: clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
> [ 0.000001] 000: sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
> [ 0.000012] 000: Switching to timer-based delay loop, resolution 125ns
> [ 0.000433] 000: Switching to timer-based delay loop, resolution 41ns
> [ 0.000445] 000: sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
> [ 0.000456] 000: clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
> [ 0.001625] 000: Console: colour dummy device 80x30
> [ 0.001638] 000: printk: console [tty1] enabled
> [ 0.001673] 000: Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
> [ 0.001680] 000: pid_max: default: 32768 minimum: 301
> [ 0.001816] 000: Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
> [ 0.001833] 000: Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
> [ 0.002543] 000: CPU: Testing write buffer coherency: ok
> [ 0.002896] 000: CPU0: update cpu_capacity 1024
> [ 0.002908] 000: CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.060000] 000: Setting up static identity map for 0x80100000 - 0x8010003c
> [ 0.079971] 000: rcu: Hierarchical SRCU implementation.
> [ 0.160105] 000: smp: Bringing up secondary CPUs ...
> [ 0.280352] 000: smp: Brought up 1 node, 1 CPU
> [ 0.280362] 000: SMP: Total of 1 processors activated (48.00 BogoMIPS).
> [ 0.280370] 000: CPU: All CPU(s) started in SVC mode.
> [ 0.281280] 000: devtmpfs: initialized
>
> giorgio
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: imx7d enable second core
2019-10-15 11:37 ` Ahmad Fatoum
@ 2019-10-15 11:51 ` Ahmad Fatoum
2019-10-15 12:11 ` Giorgio Dal Molin
1 sibling, 0 replies; 14+ messages in thread
From: Ahmad Fatoum @ 2019-10-15 11:51 UTC (permalink / raw)
To: barebox
On 10/15/19 1:37 PM, Ahmad Fatoum wrote:
> If you #define DEBUG in arch/arm/cpu/psci.c, a smc command is enabled that can
> be used to test ARM_PSCI_0_2_CPU_ON. This might aid you in your debug effort.
Should've added that I don't have an answer for your original question,
just figured I should note this as it may be helpful.
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: imx7d enable second core
2019-10-15 11:37 ` Ahmad Fatoum
2019-10-15 11:51 ` Ahmad Fatoum
@ 2019-10-15 12:11 ` Giorgio Dal Molin
2019-10-15 12:47 ` Ahmad Fatoum
1 sibling, 1 reply; 14+ messages in thread
From: Giorgio Dal Molin @ 2019-10-15 12:11 UTC (permalink / raw)
To: Ahmad Fatoum, barebox
Hi Ahmad,
thanks for answering,
actually I've already done some tests with the 'smc' DEBUG command but I think
and the results I got are not the expected ones.
(I must admit I'm not really an expert upon this PSCI subsystem of the imx7, so
I could be making some trivial errors...)
For example, if I directly execute 'smc -c' or a 'smc -i' just after barebox
booted up I get a crash:
imx7: / smc -c
prefetch abort
pc : [<10fc388c>] lr : [<bfe4a438>]
sp : bffefe10 ip : bffefe20 fp : 00000000
r10: 00000000 r9 : bfe4a55c r8 : bfe5a0f0
r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000
r3 : 00000000 r2 : bfe4a55c r1 : 00000001 r0 : 84000003
Flags: nZCv IRQs off FIQs off Mode UK6_32
no stack data available
I think this is OK because the secure monitor is still not installed.
Executing first a 'smc -n' I have:
Hit any key to stop autoboot: 4
imx7: / smc -n
imx7: / smc -i
found psci version 1.0
imx7: /
That's OK, I think.
Now I can try a 'smc -c' to enable the second core:
imx7: / smc -c
imx7: /
at this point I would expect to see the debug line generated by the
'psci_printf("2nd CPU online, now turn off again\n");' present in the funtion
'second_entry(void)'. Instead I just don't see anything.
Is this the expected behavior of 'smc -c' ?
giorgio
> On October 15, 2019 at 1:37 PM Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>
>
> On 10/15/19 1:29 PM, Giorgio Dal Molin wrote:
> > Hi,
> >
> > can anyone please confirm that a recent barebox version (v2019.10 or v2019.09)
> > is able to boot a linux kernel so that it can enable the second cpu core ?
>
> If you #define DEBUG in arch/arm/cpu/psci.c, a smc command is enabled that can
> be used to test ARM_PSCI_0_2_CPU_ON. This might aid you in your debug effort.
>
> Cheers
> Ahmad
>
> > It actually used to work in the past but now I only get one core running:
> >
> > Loading ARM Linux zImage '/mnt/boot/kernel.img'
> > Loading devicetree from '/mnt/boot/devtree.dtb'
> > commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0:armgdm:eth0: root=PARTUUID=abd2f9f6-88e5-4657-a5fb-aeb2cc6fde7e rootwait video=HDMI-A-1:1024x768M@60 console=tty1
> > Starting kernel in nonsecure mode
> > [ 0.000000] 000: Booting Linux on physical CPU 0x0
> > [ 0.000000] 000: Linux version 5.2.19-rt11-00268-g0308d71d8410-dirty (giorgio@BVblfs) (gcc version 9.2.1 20190813 (OSELAS.Toolchain 9.2.1)) #1 SMP PREEMPT RT Thu Oct 10 07:50:01 CEST 2019
> > [ 0.000000] 000: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
> > [ 0.000000] 000: CPU: div instructions available: patching division code
> > [ 0.000000] 000: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
> > [ 0.000000] 000: OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
> > [ 0.000000] 000: Memory policy: Data cache writealloc
> > [ 0.000000] 000: cma: Reserved 64 MiB at 0xac000000
> > [ 0.000000] 000: percpu: Embedded 10 pages/cpu s19296 r0 d21664 u40960
> > [ 0.000000] 000: Built 1 zonelists, mobility grouping on. Total pages: 260608
> > [ 0.000000] 000: Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0:armgdm:eth0: root=PARTUUID=abd2f9f6-88e5-4657-a5fb-aeb2cc6fde7e rootwait video=HDMI-A-1:1024x768M@60 console=tty1
> > [ 0.000000] 000: Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
> > [ 0.000000] 000: Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
> > [ 0.000000] 000: Memory: 958252K/1048576K available (9216K kernel code, 403K rwdata, 2308K rodata, 1024K init, 719K bss, 24788K reserved, 65536K cma-reserved, 261700K highmem)
> > [ 0.000000] 000: SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> > [ 0.000000] 000: rcu: Preemptible hierarchical RCU implementation.
> > [ 0.000000] 000: rcu: RCU priority boosting: priority 1 delay 500 ms.
> > [ 0.000000] 000: rcu: RCU_SOFTIRQ processing moved to rcuc kthreads.
> > [ 0.000000] 000: No expedited grace period (rcu_normal_after_boot).
> > [ 0.000000] 000: Tasks RCU enabled.
> > [ 0.000000] 000: rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
> > [ 0.000000] 000: NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
> > [ 0.000000] 000: rcu: Offload RCU callbacks from CPUs: (none).
> > [ 0.000000] 000: arch_timer: cp15 timer(s) running at 8.00MHz (virt).
> > [ 0.000000] 000: clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
> > [ 0.000001] 000: sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
> > [ 0.000012] 000: Switching to timer-based delay loop, resolution 125ns
> > [ 0.000433] 000: Switching to timer-based delay loop, resolution 41ns
> > [ 0.000445] 000: sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
> > [ 0.000456] 000: clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
> > [ 0.001625] 000: Console: colour dummy device 80x30
> > [ 0.001638] 000: printk: console [tty1] enabled
> > [ 0.001673] 000: Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
> > [ 0.001680] 000: pid_max: default: 32768 minimum: 301
> > [ 0.001816] 000: Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
> > [ 0.001833] 000: Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
> > [ 0.002543] 000: CPU: Testing write buffer coherency: ok
> > [ 0.002896] 000: CPU0: update cpu_capacity 1024
> > [ 0.002908] 000: CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> > [ 0.060000] 000: Setting up static identity map for 0x80100000 - 0x8010003c
> > [ 0.079971] 000: rcu: Hierarchical SRCU implementation.
> > [ 0.160105] 000: smp: Bringing up secondary CPUs ...
> > [ 0.280352] 000: smp: Brought up 1 node, 1 CPU
> > [ 0.280362] 000: SMP: Total of 1 processors activated (48.00 BogoMIPS).
> > [ 0.280370] 000: CPU: All CPU(s) started in SVC mode.
> > [ 0.281280] 000: devtmpfs: initialized
> >
> > giorgio
> >
> > _______________________________________________
> > barebox mailing list
> > barebox@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/barebox
> >
>
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: imx7d enable second core
2019-10-15 12:11 ` Giorgio Dal Molin
@ 2019-10-15 12:47 ` Ahmad Fatoum
0 siblings, 0 replies; 14+ messages in thread
From: Ahmad Fatoum @ 2019-10-15 12:47 UTC (permalink / raw)
To: Giorgio Dal Molin, barebox
Hello Giorgio,
On 10/15/19 2:11 PM, Giorgio Dal Molin wrote:
> Hi Ahmad,
>
> thanks for answering,
>
> actually I've already done some tests with the 'smc' DEBUG command but I think
> and the results I got are not the expected ones.
>
> (I must admit I'm not really an expert upon this PSCI subsystem of the imx7, so
> I could be making some trivial errors...)
>
> For example, if I directly execute 'smc -c' or a 'smc -i' just after barebox
> booted up I get a crash:
>
> imx7: / smc -c
> prefetch abort
> pc : [<10fc388c>] lr : [<bfe4a438>]
> sp : bffefe10 ip : bffefe20 fp : 00000000
> r10: 00000000 r9 : bfe4a55c r8 : bfe5a0f0
> r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000
> r3 : 00000000 r2 : bfe4a55c r1 : 00000001 r0 : 84000003
> Flags: nZCv IRQs off FIQs off Mode UK6_32
>
> no stack data available
>
> I think this is OK because the secure monitor is still not installed.
Ye, that's expected.
>
> Executing first a 'smc -n' I have:
>
> Hit any key to stop autoboot: 4
> imx7: / smc -n
> imx7: / smc -i
> found psci version 1.0
> imx7: /
>
> That's OK, I think.
>
> Now I can try a 'smc -c' to enable the second core:
>
> imx7: / smc -c
> imx7: /
>
> at this point I would expect to see the debug line generated by the
> 'psci_printf("2nd CPU online, now turn off again\n");' present in the funtion
> 'second_entry(void)'. Instead I just don't see anything.
> Is this the expected behavior of 'smc -c' ?
If ARM_PSCI_DEBUG=y, you should see something, yes.
You could git-bisect and see when it broke.
>
> giorgio
>
>> On October 15, 2019 at 1:37 PM Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>>
>>
>> On 10/15/19 1:29 PM, Giorgio Dal Molin wrote:
>>> Hi,
>>>
>>> can anyone please confirm that a recent barebox version (v2019.10 or v2019.09)
>>> is able to boot a linux kernel so that it can enable the second cpu core ?
>>
>> If you #define DEBUG in arch/arm/cpu/psci.c, a smc command is enabled that can
>> be used to test ARM_PSCI_0_2_CPU_ON. This might aid you in your debug effort.
>>
>> Cheers
>> Ahmad
>>
>>> It actually used to work in the past but now I only get one core running:
>>>
>>> Loading ARM Linux zImage '/mnt/boot/kernel.img'
>>> Loading devicetree from '/mnt/boot/devtree.dtb'
>>> commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0:armgdm:eth0: root=PARTUUID=abd2f9f6-88e5-4657-a5fb-aeb2cc6fde7e rootwait video=HDMI-A-1:1024x768M@60 console=tty1
>>> Starting kernel in nonsecure mode
>>> [ 0.000000] 000: Booting Linux on physical CPU 0x0
>>> [ 0.000000] 000: Linux version 5.2.19-rt11-00268-g0308d71d8410-dirty (giorgio@BVblfs) (gcc version 9.2.1 20190813 (OSELAS.Toolchain 9.2.1)) #1 SMP PREEMPT RT Thu Oct 10 07:50:01 CEST 2019
>>> [ 0.000000] 000: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
>>> [ 0.000000] 000: CPU: div instructions available: patching division code
>>> [ 0.000000] 000: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
>>> [ 0.000000] 000: OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
>>> [ 0.000000] 000: Memory policy: Data cache writealloc
>>> [ 0.000000] 000: cma: Reserved 64 MiB at 0xac000000
>>> [ 0.000000] 000: percpu: Embedded 10 pages/cpu s19296 r0 d21664 u40960
>>> [ 0.000000] 000: Built 1 zonelists, mobility grouping on. Total pages: 260608
>>> [ 0.000000] 000: Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0:armgdm:eth0: root=PARTUUID=abd2f9f6-88e5-4657-a5fb-aeb2cc6fde7e rootwait video=HDMI-A-1:1024x768M@60 console=tty1
>>> [ 0.000000] 000: Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
>>> [ 0.000000] 000: Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
>>> [ 0.000000] 000: Memory: 958252K/1048576K available (9216K kernel code, 403K rwdata, 2308K rodata, 1024K init, 719K bss, 24788K reserved, 65536K cma-reserved, 261700K highmem)
>>> [ 0.000000] 000: SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
>>> [ 0.000000] 000: rcu: Preemptible hierarchical RCU implementation.
>>> [ 0.000000] 000: rcu: RCU priority boosting: priority 1 delay 500 ms.
>>> [ 0.000000] 000: rcu: RCU_SOFTIRQ processing moved to rcuc kthreads.
>>> [ 0.000000] 000: No expedited grace period (rcu_normal_after_boot).
>>> [ 0.000000] 000: Tasks RCU enabled.
>>> [ 0.000000] 000: rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
>>> [ 0.000000] 000: NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
>>> [ 0.000000] 000: rcu: Offload RCU callbacks from CPUs: (none).
>>> [ 0.000000] 000: arch_timer: cp15 timer(s) running at 8.00MHz (virt).
>>> [ 0.000000] 000: clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
>>> [ 0.000001] 000: sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
>>> [ 0.000012] 000: Switching to timer-based delay loop, resolution 125ns
>>> [ 0.000433] 000: Switching to timer-based delay loop, resolution 41ns
>>> [ 0.000445] 000: sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
>>> [ 0.000456] 000: clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
>>> [ 0.001625] 000: Console: colour dummy device 80x30
>>> [ 0.001638] 000: printk: console [tty1] enabled
>>> [ 0.001673] 000: Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
>>> [ 0.001680] 000: pid_max: default: 32768 minimum: 301
>>> [ 0.001816] 000: Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
>>> [ 0.001833] 000: Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
>>> [ 0.002543] 000: CPU: Testing write buffer coherency: ok
>>> [ 0.002896] 000: CPU0: update cpu_capacity 1024
>>> [ 0.002908] 000: CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
>>> [ 0.060000] 000: Setting up static identity map for 0x80100000 - 0x8010003c
>>> [ 0.079971] 000: rcu: Hierarchical SRCU implementation.
>>> [ 0.160105] 000: smp: Bringing up secondary CPUs ...
>>> [ 0.280352] 000: smp: Brought up 1 node, 1 CPU
>>> [ 0.280362] 000: SMP: Total of 1 processors activated (48.00 BogoMIPS).
>>> [ 0.280370] 000: CPU: All CPU(s) started in SVC mode.
>>> [ 0.281280] 000: devtmpfs: initialized
>>>
>>> giorgio
>>>
>>> _______________________________________________
>>> barebox mailing list
>>> barebox@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/barebox
>>>
>>
>>
>> --
>> Pengutronix e.K. | |
>> Industrial Linux Solutions | http://www.pengutronix.de/ |
>> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
>> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>>
>> _______________________________________________
>> barebox mailing list
>> barebox@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* imx7d enable second core
@ 2018-07-18 7:27 Giorgio Dal Molin
2018-07-18 7:56 ` Oleksij Rempel
2018-07-18 16:54 ` Andrey Smirnov
0 siblings, 2 replies; 14+ messages in thread
From: Giorgio Dal Molin @ 2018-07-18 7:27 UTC (permalink / raw)
To: barebox
Hi all,
I'm currently working with the imx7d sabre board from NXP.
I have now a running barebox bootloader and a booting kernel.
My problem is now that, apparently, only one core is active:
...
commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
Starting kernel in secure mode
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.17.7 (giorgio@BV_blfs) (gcc version 8.1.0 (OSELAS.Toolchain-2018.02.0)) #1 SMP Wed Jul 18 07:44:41 CEST 2018
[ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] cma: Reserved 64 MiB at 0xba000000
[ 0.000000] percpu: Embedded 14 pages/cpu @(ptrval) s36392 r0 d20952 u57344
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260608
[ 0.000000] Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 950804K/1048576K available (10240K kernel code, 450K rwdata, 2188K rodata, 1024K init, 7788K bss, 32236K reserved, 65536K cma-reserved, 196196K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (11232 kB)
[ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
[ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 451 kB)
[ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) (7789 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[ 0.000000] Running RCU self tests
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU event tracing is enabled.
[ 0.000000] RCU lockdep checking is enabled.
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] Offload RCU callbacks from CPUs: (none).
[ 0.000000] arch_timer: cp15 timer(s) running at 8.00MHz (virt).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
[ 0.000009] sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
[ 0.000033] Switching to timer-based delay loop, resolution 125ns
[ 0.000545] Switching to timer-based delay loop, resolution 41ns
[ 0.000574] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
[ 0.000601] clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[ 0.001981] Console: colour dummy device 80x30
[ 0.002013] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.002032] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.002050] ... MAX_LOCK_DEPTH: 48
[ 0.002068] ... MAX_LOCKDEP_KEYS: 8191
[ 0.002086] ... CLASSHASH_SIZE: 4096
[ 0.002104] ... MAX_LOCKDEP_ENTRIES: 32768
[ 0.002122] ... MAX_LOCKDEP_CHAINS: 65536
[ 0.002140] ... CHAINHASH_SIZE: 32768
[ 0.002158] memory used by lock dependency info: 4655 kB
[ 0.002176] per task-struct memory footprint: 1536 bytes
[ 0.002230] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
[ 0.002264] pid_max: default: 32768 minimum: 301
[ 0.002590] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.002622] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.004407] CPU: Testing write buffer coherency: ok
[ 0.005308] CPU0: update cpu_capacity 1024
[ 0.005335] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.006792] Setting up static identity map for 0x80100000 - 0x80100060
[ 0.007218] Hierarchical SRCU implementation.
[ 0.008853] smp: Bringing up secondary CPUs ...
[ 0.010740] smp: Brought up 1 node, 1 CPU
[ 0.010766] SMP: Total of 1 processors activated (48.00 BogoMIPS).
[ 0.010786] CPU: All CPU(s) started in SVC mode.
[ 0.012748] devtmpfs: initialized
...
I was expecting both cores to be enabled at least by the kernel.
Does anyone had the same problem ?
giorgio
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: imx7d enable second core
2018-07-18 7:27 Giorgio Dal Molin
@ 2018-07-18 7:56 ` Oleksij Rempel
2018-07-18 16:54 ` Andrey Smirnov
1 sibling, 0 replies; 14+ messages in thread
From: Oleksij Rempel @ 2018-07-18 7:56 UTC (permalink / raw)
To: Giorgio Dal Molin, barebox, l.stach
[-- Attachment #1.1.1: Type: text/plain, Size: 5173 bytes --]
Am 18.07.2018 um 09:27 schrieb Giorgio Dal Molin:
> Hi all,
>
> I'm currently working with the imx7d sabre board from NXP.
>
> I have now a running barebox bootloader and a booting kernel.
>
> My problem is now that, apparently, only one core is active:
>
> ...
> commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> Starting kernel in secure mode
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.17.7 (giorgio@BV_blfs) (gcc version 8.1.0 (OSELAS.Toolchain-2018.02.0)) #1 SMP Wed Jul 18 07:44:41 CEST 2018
> [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
> [ 0.000000] CPU: div instructions available: patching division code
> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
> [ 0.000000] OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
> [ 0.000000] Memory policy: Data cache writealloc
> [ 0.000000] cma: Reserved 64 MiB at 0xba000000
> [ 0.000000] percpu: Embedded 14 pages/cpu @(ptrval) s36392 r0 d20952 u57344
> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260608
> [ 0.000000] Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
> [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
> [ 0.000000] Memory: 950804K/1048576K available (10240K kernel code, 450K rwdata, 2188K rodata, 1024K init, 7788K bss, 32236K reserved, 65536K cma-reserved, 196196K highmem)
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
> [ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
> [ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
> [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
> [ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (11232 kB)
> [ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
> [ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 451 kB)
> [ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) (7789 kB)
> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> [ 0.000000] Running RCU self tests
> [ 0.000000] Hierarchical RCU implementation.
> [ 0.000000] RCU event tracing is enabled.
> [ 0.000000] RCU lockdep checking is enabled.
> [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
> [ 0.000000] Offload RCU callbacks from CPUs: (none).
> [ 0.000000] arch_timer: cp15 timer(s) running at 8.00MHz (virt).
> [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
> [ 0.000009] sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
> [ 0.000033] Switching to timer-based delay loop, resolution 125ns
> [ 0.000545] Switching to timer-based delay loop, resolution 41ns
> [ 0.000574] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
> [ 0.000601] clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
> [ 0.001981] Console: colour dummy device 80x30
> [ 0.002013] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
> [ 0.002032] ... MAX_LOCKDEP_SUBCLASSES: 8
> [ 0.002050] ... MAX_LOCK_DEPTH: 48
> [ 0.002068] ... MAX_LOCKDEP_KEYS: 8191
> [ 0.002086] ... CLASSHASH_SIZE: 4096
> [ 0.002104] ... MAX_LOCKDEP_ENTRIES: 32768
> [ 0.002122] ... MAX_LOCKDEP_CHAINS: 65536
> [ 0.002140] ... CHAINHASH_SIZE: 32768
> [ 0.002158] memory used by lock dependency info: 4655 kB
> [ 0.002176] per task-struct memory footprint: 1536 bytes
> [ 0.002230] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
> [ 0.002264] pid_max: default: 32768 minimum: 301
> [ 0.002590] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
> [ 0.002622] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
> [ 0.004407] CPU: Testing write buffer coherency: ok
> [ 0.005308] CPU0: update cpu_capacity 1024
> [ 0.005335] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.006792] Setting up static identity map for 0x80100000 - 0x80100060
> [ 0.007218] Hierarchical SRCU implementation.
> [ 0.008853] smp: Bringing up secondary CPUs ...
> [ 0.010740] smp: Brought up 1 node, 1 CPU
> [ 0.010766] SMP: Total of 1 processors activated (48.00 BogoMIPS).
> [ 0.010786] CPU: All CPU(s) started in SVC mode.
> [ 0.012748] devtmpfs: initialized
> ...
>
> I was expecting both cores to be enabled at least by the kernel.
>
> Does anyone had the same problem ?
Yea, I have same problem, but no time to investigate it.
@Lukas, do you know any thing about it?
--
Regards,
Oleksij
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 149 bytes --]
_______________________________________________
barebox mailing list
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: imx7d enable second core
2018-07-18 7:27 Giorgio Dal Molin
2018-07-18 7:56 ` Oleksij Rempel
@ 2018-07-18 16:54 ` Andrey Smirnov
2018-07-19 7:16 ` Giorgio Dal Molin
2018-07-19 15:52 ` Giorgio Dal Molin
1 sibling, 2 replies; 14+ messages in thread
From: Andrey Smirnov @ 2018-07-18 16:54 UTC (permalink / raw)
To: giorgio.nicole; +Cc: Barebox List
On Wed, Jul 18, 2018 at 12:28 AM Giorgio Dal Molin
<giorgio.nicole@arcor.de> wrote:
>
> Hi all,
>
> I'm currently working with the imx7d sabre board from NXP.
>
> I have now a running barebox bootloader and a booting kernel.
>
> My problem is now that, apparently, only one core is active:
>
> ...
> commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> Starting kernel in secure mode
AFAIK, this means that you are booting in secure mode and secure
monitor code, which also implements PSCI needed for SMP to work, will
_not_ be installed by Barebox. One way to fix this would be to set:
global.bootm.secure_state=nonsecure
before booting Linux. Doing that I get:
# lscpu -e
CPU SOCKET CORE ONLINE MAXMHZ MINMHZ
0 0 0 yes 996.0000 792.0000
1 0 1 yes 996.0000 792.0000
#
on my SabreSD board.
Thanks,
Andrey Smirnov
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: imx7d enable second core
2018-07-18 16:54 ` Andrey Smirnov
@ 2018-07-19 7:16 ` Giorgio Dal Molin
2018-07-19 16:02 ` Andrey Smirnov
2018-07-19 15:52 ` Giorgio Dal Molin
1 sibling, 1 reply; 14+ messages in thread
From: Giorgio Dal Molin @ 2018-07-19 7:16 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Barebox List
Hi Andrey,
thank you for your answer,
> On July 18, 2018 at 6:54 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
>
> On Wed, Jul 18, 2018 at 12:28 AM Giorgio Dal Molin
> <giorgio.nicole@arcor.de> wrote:
> >
> > Hi all,
> >
> > I'm currently working with the imx7d sabre board from NXP.
> >
> > I have now a running barebox bootloader and a booting kernel.
> >
> > My problem is now that, apparently, only one core is active:
> >
> > ...
> > commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> > Starting kernel in secure mode
>
> AFAIK, this means that you are booting in secure mode and secure
> monitor code, which also implements PSCI needed for SMP to work, will
> _not_ be installed by Barebox. One way to fix this would be to set:
>
> global.bootm.secure_state=nonsecure
>
> before booting Linux. Doing that I get:
>
> # lscpu -e
> CPU SOCKET CORE ONLINE MAXMHZ MINMHZ
> 0 0 0 yes 996.0000 792.0000
> 1 0 1 yes 996.0000 792.0000
> #
>
> on my SabreSD board.
>
> Thanks,
> Andrey Smirnov
>
yesterday I experimented a bit more with board + barebox + kernel
and found the following procedure that (almost) works:
- enable the PSCI support in barebox and kernel;
- #define DEBUG in '<barebox>/arch/arm/cpu/psci.c' to have the command 'smc';
- boot up barebox on the board, call 'smc -n' and start the kernel:
...
Hit any key to stop autoboot: 4
imx7: / tftp karm
eth0: No MAC address set. Using random address 1a:4e:1f:63:ea:77
eth0: 1000Mbps full duplex link detected
T [#################################################################]
imx7: / tftp darm
[#################################################################]
imx7: / smc -n
imx7: / boot
Loading ARM Linux zImage 'karm'
Loading devicetree from 'darm'
commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
Starting kernel in secure mode
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.17.8-dirty (giorgio@BV_blfs) (gcc version 8.1.0 (OSELAS.Toolchain-2018.02.0)) #2 SMP Thu Jul 19 08:13:42 CEST 2018
[ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] cma: Reserved 64 MiB at 0xba000000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: psci_get_version: called.
[ 0.000000] psci: PSCIv1.0 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.0
[ 0.000000] percpu: Embedded 14 pages/cpu @(ptrval) s36392 r0 d20952 u57344
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260608
[ 0.000000] Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1 video=mxsfb0:dev=hdmi,1024x768M@60
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 950776K/1048576K available (10240K kernel code, 473K rwdata, 2216K rodata, 1024K init, 7790K bss, 32264K reserved, 65536K cma-reserved, 196196K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (11232 kB)
[ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
[ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 474 kB)
[ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) (7791 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[ 0.000000] Running RCU self tests
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU event tracing is enabled.
[ 0.000000] RCU lockdep checking is enabled.
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] Offload RCU callbacks from CPUs: (none).
[ 0.000000] arch_timer: cp15 timer(s) running at 8.00MHz (virt).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
[ 0.000008] sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
[ 0.000032] Switching to timer-based delay loop, resolution 125ns
[ 0.000546] Switching to timer-based delay loop, resolution 41ns
[ 0.000575] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
[ 0.000602] clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[ 0.002000] Console: colour dummy device 80x30
[ 0.002032] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.002051] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.002069] ... MAX_LOCK_DEPTH: 48
[ 0.002087] ... MAX_LOCKDEP_KEYS: 8191
[ 0.002104] ... CLASSHASH_SIZE: 4096
[ 0.002122] ... MAX_LOCKDEP_ENTRIES: 32768
[ 0.002140] ... MAX_LOCKDEP_CHAINS: 65536
[ 0.002158] ... CHAINHASH_SIZE: 32768
[ 0.002176] memory used by lock dependency info: 4655 kB
[ 0.002194] per task-struct memory footprint: 1536 bytes
[ 0.002247] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
[ 0.002281] pid_max: default: 32768 minimum: 301
[ 0.002609] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.002641] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.004422] CPU: Testing write buffer coherency: ok
[ 0.005337] CPU0: update cpu_capacity 1024
[ 0.005364] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.006831] Setting up static identity map for 0x80100000 - 0x80100060
[ 0.007259] Hierarchical SRCU implementation.
[ 0.008927] smp: Bringing up secondary CPUs ...
[ 0.010632] psci: psci_cpu_on: called. cpuid: 0x00000001
[ 0.010993] CPU1: update cpu_capacity 1024
[ 0.011005] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.011622] smp: Brought up 1 node, 2 CPUs
[ 0.011663] SMP: Total of 2 processors activated (96.00 BogoMIPS).
[ 0.011682] CPU: All CPU(s) started in SVC mode.
[ 0.013716] devtmpfs: initialized
...
this way the kernel smp is able to start up the second core.
The problem that remains with this setup is that the CAAM crypto
coprocessor in the imx7 does not work anymore:
...
[ 5.265081] mmc1: SDHCI controller on 30b50000.usdhc [30b50000.usdhc] using ADMA
[ 5.308453] mmc2: SDHCI controller on 30b60000.usdhc [30b60000.usdhc] using ADMA
[ 5.320799] caam 30900000.caam: Entropy delay = 3200
[ 5.352668] caam 30900000.caam: failed to acquire DECO 0
[ 5.358008] caam 30900000.caam: failed to instantiate RNG
[ 5.366479] usbcore: registered new interface driver usbhid
[ 5.372081] usbhid: USB HID core driver
...
This is probably due to the 'secure mode' in which the kernel is now booting
but I need a bit more background knowledge about the PSCI in general to really
understand what's going on here.
The barebox command 'smc -n' calls internally armv7_secure_monitor_install();
without this call the kernel is unable to start the second core; unfortunately
I'm still not able to folllow what happens within armv7_secure_monitor_install().
giorgio
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: imx7d enable second core
2018-07-19 7:16 ` Giorgio Dal Molin
@ 2018-07-19 16:02 ` Andrey Smirnov
2018-07-19 16:16 ` Giorgio Dal Molin
0 siblings, 1 reply; 14+ messages in thread
From: Andrey Smirnov @ 2018-07-19 16:02 UTC (permalink / raw)
To: giorgio.nicole; +Cc: Barebox List
On Thu, Jul 19, 2018 at 12:16 AM Giorgio Dal Molin
<giorgio.nicole@arcor.de> wrote:
>
> Hi Andrey,
>
> thank you for your answer,
>
> > On July 18, 2018 at 6:54 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
> >
> >
> > On Wed, Jul 18, 2018 at 12:28 AM Giorgio Dal Molin
> > <giorgio.nicole@arcor.de> wrote:
> > >
> > > Hi all,
> > >
> > > I'm currently working with the imx7d sabre board from NXP.
> > >
> > > I have now a running barebox bootloader and a booting kernel.
> > >
> > > My problem is now that, apparently, only one core is active:
> > >
> > > ...
> > > commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> > > Starting kernel in secure mode
> >
> > AFAIK, this means that you are booting in secure mode and secure
> > monitor code, which also implements PSCI needed for SMP to work, will
> > _not_ be installed by Barebox. One way to fix this would be to set:
> >
> > global.bootm.secure_state=nonsecure
> >
> > before booting Linux. Doing that I get:
> >
> > # lscpu -e
> > CPU SOCKET CORE ONLINE MAXMHZ MINMHZ
> > 0 0 0 yes 996.0000 792.0000
> > 1 0 1 yes 996.0000 792.0000
> > #
> >
> > on my SabreSD board.
> >
> > Thanks,
> > Andrey Smirnov
> >
>
> yesterday I experimented a bit more with board + barebox + kernel
> and found the following procedure that (almost) works:
>
> - enable the PSCI support in barebox and kernel;
> - #define DEBUG in '<barebox>/arch/arm/cpu/psci.c' to have the command 'smc';
> - boot up barebox on the board, call 'smc -n' and start the kernel:
>
Is there any particular reason you used a command meant for debugging
instead of "global.bootm.secure_state=nonsecure", which is available
without needing to do any source modification?
> ...
> Hit any key to stop autoboot: 4
> imx7: / tftp karm
> eth0: No MAC address set. Using random address 1a:4e:1f:63:ea:77
> eth0: 1000Mbps full duplex link detected
> T [#################################################################]
> imx7: / tftp darm
> [#################################################################]
> imx7: / smc -n
> imx7: / boot
>
> Loading ARM Linux zImage 'karm'
> Loading devicetree from 'darm'
> commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> Starting kernel in secure mode
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.17.8-dirty (giorgio@BV_blfs) (gcc version 8.1.0 (OSELAS.Toolchain-2018.02.0)) #2 SMP Thu Jul 19 08:13:42 CEST 2018
> [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
> [ 0.000000] CPU: div instructions available: patching division code
> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
> [ 0.000000] OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
> [ 0.000000] Memory policy: Data cache writealloc
> [ 0.000000] cma: Reserved 64 MiB at 0xba000000
> [ 0.000000] psci: probing for conduit method from DT.
> [ 0.000000] psci: psci_get_version: called.
> [ 0.000000] psci: PSCIv1.0 detected in firmware.
> [ 0.000000] psci: Using standard PSCI v0.2 function IDs
> [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
> [ 0.000000] psci: SMC Calling Convention v1.0
> [ 0.000000] percpu: Embedded 14 pages/cpu @(ptrval) s36392 r0 d20952 u57344
> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260608
> [ 0.000000] Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1 video=mxsfb0:dev=hdmi,1024x768M@60
> [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
> [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
> [ 0.000000] Memory: 950776K/1048576K available (10240K kernel code, 473K rwdata, 2216K rodata, 1024K init, 7790K bss, 32264K reserved, 65536K cma-reserved, 196196K highmem)
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
> [ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
> [ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
> [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
> [ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (11232 kB)
> [ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
> [ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 474 kB)
> [ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) (7791 kB)
> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> [ 0.000000] Running RCU self tests
> [ 0.000000] Hierarchical RCU implementation.
> [ 0.000000] RCU event tracing is enabled.
> [ 0.000000] RCU lockdep checking is enabled.
> [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
> [ 0.000000] Offload RCU callbacks from CPUs: (none).
> [ 0.000000] arch_timer: cp15 timer(s) running at 8.00MHz (virt).
> [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
> [ 0.000008] sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
> [ 0.000032] Switching to timer-based delay loop, resolution 125ns
> [ 0.000546] Switching to timer-based delay loop, resolution 41ns
> [ 0.000575] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
> [ 0.000602] clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
> [ 0.002000] Console: colour dummy device 80x30
> [ 0.002032] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
> [ 0.002051] ... MAX_LOCKDEP_SUBCLASSES: 8
> [ 0.002069] ... MAX_LOCK_DEPTH: 48
> [ 0.002087] ... MAX_LOCKDEP_KEYS: 8191
> [ 0.002104] ... CLASSHASH_SIZE: 4096
> [ 0.002122] ... MAX_LOCKDEP_ENTRIES: 32768
> [ 0.002140] ... MAX_LOCKDEP_CHAINS: 65536
> [ 0.002158] ... CHAINHASH_SIZE: 32768
> [ 0.002176] memory used by lock dependency info: 4655 kB
> [ 0.002194] per task-struct memory footprint: 1536 bytes
> [ 0.002247] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
> [ 0.002281] pid_max: default: 32768 minimum: 301
> [ 0.002609] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
> [ 0.002641] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
> [ 0.004422] CPU: Testing write buffer coherency: ok
> [ 0.005337] CPU0: update cpu_capacity 1024
> [ 0.005364] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.006831] Setting up static identity map for 0x80100000 - 0x80100060
> [ 0.007259] Hierarchical SRCU implementation.
> [ 0.008927] smp: Bringing up secondary CPUs ...
> [ 0.010632] psci: psci_cpu_on: called. cpuid: 0x00000001
> [ 0.010993] CPU1: update cpu_capacity 1024
> [ 0.011005] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> [ 0.011622] smp: Brought up 1 node, 2 CPUs
> [ 0.011663] SMP: Total of 2 processors activated (96.00 BogoMIPS).
> [ 0.011682] CPU: All CPU(s) started in SVC mode.
> [ 0.013716] devtmpfs: initialized
> ...
>
>
> this way the kernel smp is able to start up the second core.
> The problem that remains with this setup is that the CAAM crypto
> coprocessor in the imx7 does not work anymore:
>
> ...
> [ 5.265081] mmc1: SDHCI controller on 30b50000.usdhc [30b50000.usdhc] using ADMA
> [ 5.308453] mmc2: SDHCI controller on 30b60000.usdhc [30b60000.usdhc] using ADMA
> [ 5.320799] caam 30900000.caam: Entropy delay = 3200
> [ 5.352668] caam 30900000.caam: failed to acquire DECO 0
> [ 5.358008] caam 30900000.caam: failed to instantiate RNG
> [ 5.366479] usbcore: registered new interface driver usbhid
> [ 5.372081] usbhid: USB HID core driver
> ...
I've never used CAAM, so I am not sure what's going on, but my
educated guess would that this might have to do with TrustZone
permissions.
>
> This is probably due to the 'secure mode' in which the kernel is now booting
> but I need a bit more background knowledge about the PSCI in general to really
> understand what's going on here.
You kernel was booting in 'secure mode' before, now it actually boots
in 'nonsecure', but because you installed the monitor through a
backdoor that log line still prints 'secure'.
Thanks,
Andrey Smirnov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: imx7d enable second core
2018-07-19 16:02 ` Andrey Smirnov
@ 2018-07-19 16:16 ` Giorgio Dal Molin
0 siblings, 0 replies; 14+ messages in thread
From: Giorgio Dal Molin @ 2018-07-19 16:16 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Barebox List
Hi Andrey,
> On July 19, 2018 at 6:02 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
>
> On Thu, Jul 19, 2018 at 12:16 AM Giorgio Dal Molin
> <giorgio.nicole@arcor.de> wrote:
> >
> > Hi Andrey,
> >
> > thank you for your answer,
> >
> > > On July 18, 2018 at 6:54 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
> > >
> > >
> > > On Wed, Jul 18, 2018 at 12:28 AM Giorgio Dal Molin
> > > <giorgio.nicole@arcor.de> wrote:
> > > >
> > > > Hi all,
> > > >
> > > > I'm currently working with the imx7d sabre board from NXP.
> > > >
> > > > I have now a running barebox bootloader and a booting kernel.
> > > >
> > > > My problem is now that, apparently, only one core is active:
> > > >
> > > > ...
> > > > commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> > > > Starting kernel in secure mode
> > >
> > > AFAIK, this means that you are booting in secure mode and secure
> > > monitor code, which also implements PSCI needed for SMP to work, will
> > > _not_ be installed by Barebox. One way to fix this would be to set:
> > >
> > > global.bootm.secure_state=nonsecure
> > >
> > > before booting Linux. Doing that I get:
> > >
> > > # lscpu -e
> > > CPU SOCKET CORE ONLINE MAXMHZ MINMHZ
> > > 0 0 0 yes 996.0000 792.0000
> > > 1 0 1 yes 996.0000 792.0000
> > > #
> > >
> > > on my SabreSD board.
> > >
> > > Thanks,
> > > Andrey Smirnov
> > >
> >
> > yesterday I experimented a bit more with board + barebox + kernel
> > and found the following procedure that (almost) works:
> >
> > - enable the PSCI support in barebox and kernel;
> > - #define DEBUG in '<barebox>/arch/arm/cpu/psci.c' to have the command 'smc';
> > - boot up barebox on the board, call 'smc -n' and start the kernel:
> >
>
> Is there any particular reason you used a command meant for debugging
> instead of "global.bootm.secure_state=nonsecure", which is available
> without needing to do any source modification?
No particular reason, I had a problem and tried something...
>
> > ...
> > Hit any key to stop autoboot: 4
> > imx7: / tftp karm
> > eth0: No MAC address set. Using random address 1a:4e:1f:63:ea:77
> > eth0: 1000Mbps full duplex link detected
> > T [#################################################################]
> > imx7: / tftp darm
> > [#################################################################]
> > imx7: / smc -n
> > imx7: / boot
> >
> > Loading ARM Linux zImage 'karm'
> > Loading devicetree from 'darm'
> > commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> > Starting kernel in secure mode
> > [ 0.000000] Booting Linux on physical CPU 0x0
> > [ 0.000000] Linux version 4.17.8-dirty (giorgio@BV_blfs) (gcc version 8.1.0 (OSELAS.Toolchain-2018.02.0)) #2 SMP Thu Jul 19 08:13:42 CEST 2018
> > [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
> > [ 0.000000] CPU: div instructions available: patching division code
> > [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
> > [ 0.000000] OF: fdt: Machine model: Freescale i.MX7 SabreSD Board
> > [ 0.000000] Memory policy: Data cache writealloc
> > [ 0.000000] cma: Reserved 64 MiB at 0xba000000
> > [ 0.000000] psci: probing for conduit method from DT.
> > [ 0.000000] psci: psci_get_version: called.
> > [ 0.000000] psci: PSCIv1.0 detected in firmware.
> > [ 0.000000] psci: Using standard PSCI v0.2 function IDs
> > [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
> > [ 0.000000] psci: SMC Calling Convention v1.0
> > [ 0.000000] percpu: Embedded 14 pages/cpu @(ptrval) s36392 r0 d20952 u57344
> > [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260608
> > [ 0.000000] Kernel command line: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1 video=mxsfb0:dev=hdmi,1024x768M@60
> > [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
> > [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
> > [ 0.000000] Memory: 950776K/1048576K available (10240K kernel code, 473K rwdata, 2216K rodata, 1024K init, 7790K bss, 32264K reserved, 65536K cma-reserved, 196196K highmem)
> > [ 0.000000] Virtual kernel memory layout:
> > [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> > [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
> > [ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
> > [ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
> > [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
> > [ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (11232 kB)
> > [ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
> > [ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 474 kB)
> > [ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) (7791 kB)
> > [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> > [ 0.000000] Running RCU self tests
> > [ 0.000000] Hierarchical RCU implementation.
> > [ 0.000000] RCU event tracing is enabled.
> > [ 0.000000] RCU lockdep checking is enabled.
> > [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
> > [ 0.000000] Offload RCU callbacks from CPUs: (none).
> > [ 0.000000] arch_timer: cp15 timer(s) running at 8.00MHz (virt).
> > [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
> > [ 0.000008] sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
> > [ 0.000032] Switching to timer-based delay loop, resolution 125ns
> > [ 0.000546] Switching to timer-based delay loop, resolution 41ns
> > [ 0.000575] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
> > [ 0.000602] clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
> > [ 0.002000] Console: colour dummy device 80x30
> > [ 0.002032] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
> > [ 0.002051] ... MAX_LOCKDEP_SUBCLASSES: 8
> > [ 0.002069] ... MAX_LOCK_DEPTH: 48
> > [ 0.002087] ... MAX_LOCKDEP_KEYS: 8191
> > [ 0.002104] ... CLASSHASH_SIZE: 4096
> > [ 0.002122] ... MAX_LOCKDEP_ENTRIES: 32768
> > [ 0.002140] ... MAX_LOCKDEP_CHAINS: 65536
> > [ 0.002158] ... CHAINHASH_SIZE: 32768
> > [ 0.002176] memory used by lock dependency info: 4655 kB
> > [ 0.002194] per task-struct memory footprint: 1536 bytes
> > [ 0.002247] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
> > [ 0.002281] pid_max: default: 32768 minimum: 301
> > [ 0.002609] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
> > [ 0.002641] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
> > [ 0.004422] CPU: Testing write buffer coherency: ok
> > [ 0.005337] CPU0: update cpu_capacity 1024
> > [ 0.005364] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> > [ 0.006831] Setting up static identity map for 0x80100000 - 0x80100060
> > [ 0.007259] Hierarchical SRCU implementation.
> > [ 0.008927] smp: Bringing up secondary CPUs ...
> > [ 0.010632] psci: psci_cpu_on: called. cpuid: 0x00000001
> > [ 0.010993] CPU1: update cpu_capacity 1024
> > [ 0.011005] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> > [ 0.011622] smp: Brought up 1 node, 2 CPUs
> > [ 0.011663] SMP: Total of 2 processors activated (96.00 BogoMIPS).
> > [ 0.011682] CPU: All CPU(s) started in SVC mode.
> > [ 0.013716] devtmpfs: initialized
> > ...
> >
> >
> > this way the kernel smp is able to start up the second core.
> > The problem that remains with this setup is that the CAAM crypto
> > coprocessor in the imx7 does not work anymore:
> >
> > ...
> > [ 5.265081] mmc1: SDHCI controller on 30b50000.usdhc [30b50000.usdhc] using ADMA
> > [ 5.308453] mmc2: SDHCI controller on 30b60000.usdhc [30b60000.usdhc] using ADMA
> > [ 5.320799] caam 30900000.caam: Entropy delay = 3200
> > [ 5.352668] caam 30900000.caam: failed to acquire DECO 0
> > [ 5.358008] caam 30900000.caam: failed to instantiate RNG
> > [ 5.366479] usbcore: registered new interface driver usbhid
> > [ 5.372081] usbhid: USB HID core driver
> > ...
>
> I've never used CAAM, so I am not sure what's going on, but my
> educated guess would that this might have to do with TrustZone
> permissions.
I also think so, the cores problem is independent from the CAAM one,
it just happens that when I have 2 cores the CAAM doesn't work...
The CAAM is usefull for me because it accelerates the random number
generation for /dev/random and that's good when you use the ssh daemon,
in userspace.
>
> >
> > This is probably due to the 'secure mode' in which the kernel is now booting
> > but I need a bit more background knowledge about the PSCI in general to really
> > understand what's going on here.
>
> You kernel was booting in 'secure mode' before, now it actually boots
> in 'nonsecure', but because you installed the monitor through a
> backdoor that log line still prints 'secure'.
>
giorgio
_______________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: imx7d enable second core
2018-07-18 16:54 ` Andrey Smirnov
2018-07-19 7:16 ` Giorgio Dal Molin
@ 2018-07-19 15:52 ` Giorgio Dal Molin
2018-07-19 16:09 ` Andrey Smirnov
1 sibling, 1 reply; 14+ messages in thread
From: Giorgio Dal Molin @ 2018-07-19 15:52 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Barebox List
Hi Andrey,
> On July 18, 2018 at 6:54 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
>
> On Wed, Jul 18, 2018 at 12:28 AM Giorgio Dal Molin
> <giorgio.nicole@arcor.de> wrote:
> >
> > Hi all,
> >
> > I'm currently working with the imx7d sabre board from NXP.
> >
> > I have now a running barebox bootloader and a booting kernel.
> >
> > My problem is now that, apparently, only one core is active:
> >
> > ...
> > commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> > Starting kernel in secure mode
>
> AFAIK, this means that you are booting in secure mode and secure
> monitor code, which also implements PSCI needed for SMP to work, will
> _not_ be installed by Barebox. One way to fix this would be to set:
>
> global.bootm.secure_state=nonsecure
>
> before booting Linux. Doing that I get:
>
> # lscpu -e
> CPU SOCKET CORE ONLINE MAXMHZ MINMHZ
> 0 0 0 yes 996.0000 792.0000
> 1 0 1 yes 996.0000 792.0000
> #
>
> on my SabreSD board.
>
I think I've found some inconsistencies in the SECURE / NONSECURE implementation
in barebox.
In arch/arm/include/asm/secure.h there is the definition:
...
enum arm_security_state {
ARM_STATE_SECURE,
ARM_STATE_NONSECURE,
ARM_STATE_HYP,
};
where ARM_STATE_SECURE == 0 and ARM_STATE_NONSECURE == 1;
In arch/arm/cpu/psci.c we have:
...
static int of_psci_fixup(struct device_node *root, void *unused)
{
struct device_node *psci;
int ret;
if (bootm_arm_security_state() < ARM_STATE_NONSECURE)
return 0;
psci = of_create_node(root, "/psci");
if (!psci)
...
This is a bit surprising and conterintuitive: I think the logic should
be so that if the current mode is not secure then we want to go out, otherwise
we want to generate the /psci {} dt block for the kernel. If this is true then
we have an error here.
One more use of the state is in the start_linux() function, in arch/arm/lib32/armlinux.c:
...
void start_linux(void *adr, int swap, unsigned long initrd_address,
unsigned long initrd_size, void *oftree,
enum arm_security_state state)
{
void (*kernel)(int zero, int arch, void *params) = adr;
void *params = NULL;
int architecture;
int ret;
if (IS_ENABLED(CONFIG_ARM_SECURE_MONITOR) && state > ARM_STATE_NONSECURE) {
ret = armv7_secure_monitor_install();
if (ret)
pr_err("Failed to install secure monitor\n");
}
...
In this case the secure monitor would be installed only in case state == ARM_STATE_HYP,
also strange...
I tried to fix things so:
In arch/arm/include/asm/secure.h:
...
enum arm_security_state {
ARM_STATE_NONSECURE,
ARM_STATE_SECURE,
ARM_STATE_HYP,
};
In arch/arm/cpu/psci.c:
...
static int of_psci_fixup(struct device_node *root, void *unused)
{
struct device_node *psci;
int ret;
if (bootm_arm_security_state() < ARM_STATE_SECURE)
return 0;
psci = of_create_node(root, "/psci");
if (!psci)
...
Moreover, in arch/arm/cpu/sm.c I initialized the global var. bootm_secure_state: = ARM_STATE_SECURE
static int sm_init(void)
{
...
bootm_secure_state = ARM_STATE_SECURE
}
With these fixes I can boot the imx7d sabre in secure mode with 2 cores.
Unfortunately the CAAM cripto module still doesn't work :-(
giorgio
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: imx7d enable second core
2018-07-19 15:52 ` Giorgio Dal Molin
@ 2018-07-19 16:09 ` Andrey Smirnov
2018-07-19 16:18 ` Giorgio Dal Molin
0 siblings, 1 reply; 14+ messages in thread
From: Andrey Smirnov @ 2018-07-19 16:09 UTC (permalink / raw)
To: giorgio.nicole; +Cc: Barebox List
On Thu, Jul 19, 2018 at 8:52 AM Giorgio Dal Molin
<giorgio.nicole@arcor.de> wrote:
>
> Hi Andrey,
>
> > On July 18, 2018 at 6:54 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
> >
> >
> > On Wed, Jul 18, 2018 at 12:28 AM Giorgio Dal Molin
> > <giorgio.nicole@arcor.de> wrote:
> > >
> > > Hi all,
> > >
> > > I'm currently working with the imx7d sabre board from NXP.
> > >
> > > I have now a running barebox bootloader and a booting kernel.
> > >
> > > My problem is now that, apparently, only one core is active:
> > >
> > > ...
> > > commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> > > Starting kernel in secure mode
> >
> > AFAIK, this means that you are booting in secure mode and secure
> > monitor code, which also implements PSCI needed for SMP to work, will
> > _not_ be installed by Barebox. One way to fix this would be to set:
> >
> > global.bootm.secure_state=nonsecure
> >
> > before booting Linux. Doing that I get:
> >
> > # lscpu -e
> > CPU SOCKET CORE ONLINE MAXMHZ MINMHZ
> > 0 0 0 yes 996.0000 792.0000
> > 1 0 1 yes 996.0000 792.0000
> > #
> >
> > on my SabreSD board.
> >
>
> I think I've found some inconsistencies in the SECURE / NONSECURE implementation
> in barebox.
>
> In arch/arm/include/asm/secure.h there is the definition:
>
> ...
> enum arm_security_state {
> ARM_STATE_SECURE,
> ARM_STATE_NONSECURE,
> ARM_STATE_HYP,
> };
>
> where ARM_STATE_SECURE == 0 and ARM_STATE_NONSECURE == 1;
>
> In arch/arm/cpu/psci.c we have:
>
> ...
> static int of_psci_fixup(struct device_node *root, void *unused)
> {
> struct device_node *psci;
> int ret;
>
> if (bootm_arm_security_state() < ARM_STATE_NONSECURE)
> return 0;
>
> psci = of_create_node(root, "/psci");
> if (!psci)
> ...
>
> This is a bit surprising and conterintuitive: I think the logic should
> be so that if the current mode is not secure then we want to go out, otherwise
> we want to generate the /psci {} dt block for the kernel. If this is true then
> we have an error here.
In ARM_STATE_SECURE the code will not install a security monitor
implementing PSCI, so it's presence is not signaled via DT to the
kernel in that mode.
>
> One more use of the state is in the start_linux() function, in arch/arm/lib32/armlinux.c:
>
> ...
> void start_linux(void *adr, int swap, unsigned long initrd_address,
> unsigned long initrd_size, void *oftree,
> enum arm_security_state state)
> {
> void (*kernel)(int zero, int arch, void *params) = adr;
> void *params = NULL;
> int architecture;
> int ret;
>
> if (IS_ENABLED(CONFIG_ARM_SECURE_MONITOR) && state > ARM_STATE_NONSECURE) {
> ret = armv7_secure_monitor_install();
> if (ret)
> pr_err("Failed to install secure monitor\n");
> }
> ...
>
Where do you see the code above? Here's what's in master:
https://git.pengutronix.de/cgit/barebox/tree/arch/arm/lib32/armlinux.c#n270
and it looks different form what you are quoting.
Thanks,
Andrey Smirnov
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: imx7d enable second core
2018-07-19 16:09 ` Andrey Smirnov
@ 2018-07-19 16:18 ` Giorgio Dal Molin
0 siblings, 0 replies; 14+ messages in thread
From: Giorgio Dal Molin @ 2018-07-19 16:18 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Barebox List
Hi Andrey,
> On July 19, 2018 at 6:09 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
>
> On Thu, Jul 19, 2018 at 8:52 AM Giorgio Dal Molin
> <giorgio.nicole@arcor.de> wrote:
> >
> > Hi Andrey,
> >
> > > On July 18, 2018 at 6:54 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
> > >
> > >
> > > On Wed, Jul 18, 2018 at 12:28 AM Giorgio Dal Molin
> > > <giorgio.nicole@arcor.de> wrote:
> > > >
> > > > Hi all,
> > > >
> > > > I'm currently working with the imx7d sabre board from NXP.
> > > >
> > > > I have now a running barebox bootloader and a booting kernel.
> > > >
> > > > My problem is now that, apparently, only one core is active:
> > > >
> > > > ...
> > > > commandline: console=ttymxc0,115200n8 ip=11.0.0.4::11.0.0.2:255.0.0.0::eth0: root=/dev/mmcblk0p2 rootdelay=1
> > > > Starting kernel in secure mode
> > >
> > > AFAIK, this means that you are booting in secure mode and secure
> > > monitor code, which also implements PSCI needed for SMP to work, will
> > > _not_ be installed by Barebox. One way to fix this would be to set:
> > >
> > > global.bootm.secure_state=nonsecure
> > >
> > > before booting Linux. Doing that I get:
> > >
> > > # lscpu -e
> > > CPU SOCKET CORE ONLINE MAXMHZ MINMHZ
> > > 0 0 0 yes 996.0000 792.0000
> > > 1 0 1 yes 996.0000 792.0000
> > > #
> > >
> > > on my SabreSD board.
> > >
> >
> > I think I've found some inconsistencies in the SECURE / NONSECURE implementation
> > in barebox.
> >
> > In arch/arm/include/asm/secure.h there is the definition:
> >
> > ...
> > enum arm_security_state {
> > ARM_STATE_SECURE,
> > ARM_STATE_NONSECURE,
> > ARM_STATE_HYP,
> > };
> >
> > where ARM_STATE_SECURE == 0 and ARM_STATE_NONSECURE == 1;
> >
> > In arch/arm/cpu/psci.c we have:
> >
> > ...
> > static int of_psci_fixup(struct device_node *root, void *unused)
> > {
> > struct device_node *psci;
> > int ret;
> >
> > if (bootm_arm_security_state() < ARM_STATE_NONSECURE)
> > return 0;
> >
> > psci = of_create_node(root, "/psci");
> > if (!psci)
> > ...
> >
> > This is a bit surprising and conterintuitive: I think the logic should
> > be so that if the current mode is not secure then we want to go out, otherwise
> > we want to generate the /psci {} dt block for the kernel. If this is true then
> > we have an error here.
>
> In ARM_STATE_SECURE the code will not install a security monitor
> implementing PSCI, so it's presence is not signaled via DT to the
> kernel in that mode.
>
> >
> > One more use of the state is in the start_linux() function, in arch/arm/lib32/armlinux.c:
> >
> > ...
> > void start_linux(void *adr, int swap, unsigned long initrd_address,
> > unsigned long initrd_size, void *oftree,
> > enum arm_security_state state)
> > {
> > void (*kernel)(int zero, int arch, void *params) = adr;
> > void *params = NULL;
> > int architecture;
> > int ret;
> >
> > if (IS_ENABLED(CONFIG_ARM_SECURE_MONITOR) && state > ARM_STATE_NONSECURE) {
> > ret = armv7_secure_monitor_install();
> > if (ret)
> > pr_err("Failed to install secure monitor\n");
> > }
> > ...
> >
>
> Where do you see the code above? Here's what's in master:
>
> https://git.pengutronix.de/cgit/barebox/tree/arch/arm/lib32/armlinux.c#n270
>
> and it looks different form what you are quoting.
>
you are right, I accidentally copied my 'fixed' version.
giorgio
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-10-15 12:47 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-15 11:29 imx7d enable second core Giorgio Dal Molin
2019-10-15 11:37 ` Ahmad Fatoum
2019-10-15 11:51 ` Ahmad Fatoum
2019-10-15 12:11 ` Giorgio Dal Molin
2019-10-15 12:47 ` Ahmad Fatoum
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2018-07-18 7:27 Giorgio Dal Molin
2018-07-18 7:56 ` Oleksij Rempel
2018-07-18 16:54 ` Andrey Smirnov
2018-07-19 7:16 ` Giorgio Dal Molin
2018-07-19 16:02 ` Andrey Smirnov
2018-07-19 16:16 ` Giorgio Dal Molin
2018-07-19 15:52 ` Giorgio Dal Molin
2018-07-19 16:09 ` Andrey Smirnov
2018-07-19 16:18 ` Giorgio Dal Molin
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