From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-wm0-x234.google.com ([2a00:1450:400c:c09::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1abUSP-00058H-Sj for barebox@lists.infradead.org; Thu, 03 Mar 2016 14:42:26 +0000 Received: by mail-wm0-x234.google.com with SMTP id l68so134355207wml.0 for ; Thu, 03 Mar 2016 06:42:05 -0800 (PST) From: Holger Schurig In-Reply-To: <56D831C6.1010101@eurek.it> (gianluca's message of "Thu, 3 Mar 2016 13:44:54 +0100") References: <56D831C6.1010101@eurek.it> Date: Thu, 03 Mar 2016 15:42:01 +0100 Message-ID: <8737s7ei86.fsf@gmail.com> MIME-Version: 1.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: Re: Ethernet PHY KSZ9031 is not working To: gianluca Cc: barebox@lists.infradead.org > USB Host-A has to be tested, but if I type: > >>> usb >> USB: scanning bus for devices... >> Bus 001 Device 001: ID 0000:0000 EHCI Host Controller >> 1 USB Device(s) found > > so I can suppose the host controller is working. I'm unsure if that is correct. When you see the USB IDs of some connected devices then you be (a bit) sure(rer). > - DDR3 Memory Controller > Memtest is passing all tests. So I can suppose the timings are quite > good enough to use the Dynamic RAM correctly. I will do a stress test > later... I had a system once where the memtest in barebox worked, but memtester from Linux found issues. Also be aware that Freecell has some DDR3 memory tester / setting optimizer that work via the USB port, like the USB downloader. Just in case, if you ever run into trouble ... AS for the FEC/PHY, I'm on some SMSC phy. If I recall it correctly, then the Sabre board also has a KSZ phy, and when I had this board here it worked over ethernet. In arch/arm/boards/boundarydevices-nitrogen6x/board.c there do something similar, but not identical to what you're doing. > When Barebox takes control over, those pins are turned off, the device > tree information is telling me: There is one more thing that you should be aware: the ethernet clock can either be driven by the i.MX6, then it's an output. Or it can be generated by the PHY, then it's an input. In my case it was MX6QDL_PAD_GPIO_16__ENET_REF_CLK. This is controlled by a bit in the GPR1 register. Maybe you need to adapt your device tree (search for "enet_ref") for this? On Linux, this is driven by arch/arm/mach-imx/mach-imx6q.c, and on Barebox there is an enet_ref in arch/arm/boards/freescale-mx6sx-sabresdb/board.c. > I don't know where I can check if something goes wrong. May be a > failure on board, but at this time this board is the ONLY BOARD I can > use. Time to get your oscilloscope probe ready then :-) _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox