From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from smtp1-g21.free.fr ([2a01:e0c:1:1599::10]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SeBfm-0000dc-JL for barebox@lists.infradead.org; Mon, 11 Jun 2012 20:57:17 +0000 From: Robert Jarzmik References: Date: Mon, 11 Jun 2012 22:57:03 +0200 In-Reply-To: (Krzysztof Halasa's message of "Sun, 10 Jun 2012 14:08:53 +0200") Message-ID: <87mx49va74.fsf@free.fr> MIME-Version: 1.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: barebox-bounces@lists.infradead.org Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: Re: Is Intel/Marvell PXA really ARMv4? To: Krzysztof Halasa Cc: barebox@lists.infradead.org Krzysztof Halasa writes: > (Commit 36c47ce426cbe7aea59fab4c0218fe07cd80bdc0) > > arch/arm/cpu/Kconfig: > > +# Xscale PXA25x, PXA27x > +config CPU_XSCALE > + bool > + select CPU_32v4T > + > > I think all XScale CPUs are (at least) ARM v5TE, aren't they? Yes they are ... but see next lines ... The PXA processor is an ARMv5TE. The cache-armv5.S in barebox is acutally matched to be used with ARMv5TEJ and doesn't get along with a v5TE. Hence we switch the core depenendy to v4t since the callbacks are fully compatible. That's what in the historical commits of pxa's barebox support. Cheers. -- Robert _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox