[PATCH 00/17] Armada 370/XP NAND driver

[PATCH 00/17] Armada 370/XP NAND driver

[Sebastian Hesselbarth]

This patch set adds support for the NAND flash controller found
on Marvell Armada 370/XP SoCs. The IP is the same as for PXA3xx
SoCs, so we can also reuse the driver. However, this needs some
rework of the existing driver.

First 4 patches free nand_mrvl_nfc from mach-pxa dependency by
adding common clock support to mach-pxa and rework the driver
to get rid of pxa_get_nandclk().

The next 7 patches comprise cleanup and preparation for the
addition of Armada 370/XP version of the NAND controller IP.

Then there is 5 patches adding features found on Armada XP
NAND controller only.

Finally, the last patch adds optimized timings for the NAND
flash found on Lenovo ix4-300d.

This series is, of course, untested on mach-pxa and needs a
Tested-by. I have tested the new driver on Armada XP based
Lenovo ix4-300d and todays -next.

Sebastian Hesselbarth (17):
  arm: pxa: Prepare for NAND clkdev lookup on PXA3xx
  mtd: nand_mrvl_nfc: Use common clock for core clock
  mtd: nand: Clarify Marvell Orion Kconfig prompt
  arm: pxa: Remove pxa_get_nandclk()
  mtd: nand_mrvl_nfc: Remove keep_config
  mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00
  mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase
  mtd: nand_mrvl_nfc: Fix num-cs property parsing
  mtd: nand_mrvl_nfc: Get ecc parameters from DT
  mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths
  mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions
  mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC
  mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC
  mtd: nand_mrvl_nfc: Add support for HW BCH ECC
  mtd: nand_mrvl_nfc: Add support for NDCB3 register
  mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP
  mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U

 arch/arm/Kconfig                       |   1 +
 arch/arm/mach-pxa/Kconfig              |   2 +
 arch/arm/mach-pxa/include/mach/clock.h |   1 -
 arch/arm/mach-pxa/speed-pxa3xx.c       |  18 ++-
 drivers/mtd/nand/Kconfig               |   9 +-
 drivers/mtd/nand/nand_mrvl_nfc.c       | 226 ++++++++++++++++++++++++++++++---
 6 files changed, 229 insertions(+), 28 deletions(-)

---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
-- 
2.1.0


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[PATCH 01/17] arm: pxa: Prepare for NAND clkdev lookup on PXA3xx

[Sebastian Hesselbarth]

To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP,
prepare to provide a common clock for the NAND driver on PXA3xx.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 arch/arm/Kconfig                 |  1 +
 arch/arm/mach-pxa/Kconfig        |  2 ++
 arch/arm/mach-pxa/speed-pxa3xx.c | 16 ++++++++++++++++
 3 files changed, 19 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 203f912e96e5..90af91819f08 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -147,6 +147,7 @@ config ARCH_PXA
 	bool "Intel/Marvell PXA based"
 	select GENERIC_GPIO
 	select HAS_POWEROFF
+	select HAVE_CLK
 
 config ARCH_ROCKCHIP
 	bool "Rockchip RX3xxx"
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 54094f4ca0ed..1c0894892b17 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -17,6 +17,8 @@ config ARCH_PXA2XX
 config ARCH_PXA3XX
        bool
        select CPU_XSC3
+       select CLKDEV_LOOKUP
+       select COMMON_CLK
 
 config ARCH_PXA310
        bool
diff --git a/arch/arm/mach-pxa/speed-pxa3xx.c b/arch/arm/mach-pxa/speed-pxa3xx.c
index 6a08ea78f065..91e03eae4a52 100644
--- a/arch/arm/mach-pxa/speed-pxa3xx.c
+++ b/arch/arm/mach-pxa/speed-pxa3xx.c
@@ -8,6 +8,9 @@
  */
 
 #include <common.h>
+#include <init.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/pxa-regs.h>
 
@@ -31,3 +34,16 @@ unsigned long pxa_get_nandclk(void)
 	else
 		return 156000000;
 }
+
+static int pxa3xx_clock_init(void)
+{
+	unsigned long nand_rate = (cpu_is_pxa320()) ? 104000000 : 156000000;
+	struct clk *clk;
+
+	clk = clk_fixed("nand", nand_rate);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	return clk_register_clkdev(clk, NULL, "mrvl_nand");
+}
+postcore_initcall(pxa3xx_clock_init);
-- 
2.1.0


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[PATCH 02/17] mtd: nand_mrvl_nfc: Use common clock for core clock

[Sebastian Hesselbarth]

With PXA3xx now providing a common clock for the NAND clock, use it
and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP
to reuse the same driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 1ec48cc09e59..bdf949de0e7f 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -24,7 +24,6 @@
 #include <linux/types.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <mach/clock.h>
 #include <malloc.h>
 #include <of_mtd.h>
 #include <stmp-device.h>
@@ -135,6 +134,7 @@ struct mrvl_nand_host {
 	struct nand_chip	chip;
 	struct mtd_partition	*parts;
 	struct device_d		*dev;
+	struct clk		*core_clk;
 
 	/* calculated from mrvl_nand_flash data */
 	unsigned int		col_addr_cycles;
@@ -281,10 +281,10 @@ static struct mrvl_nand_timing timings[] = {
 static void mrvl_nand_set_timing(struct mrvl_nand_host *host, bool use_default)
 {
 	struct mtd_info *mtd = &host->mtd;
+	unsigned long nand_clk = clk_get_rate(host->core_clk);
 	struct mrvl_nand_timing *t;
 	uint32_t ndtr0, ndtr1;
 	u16 id;
-	unsigned long nand_clk = pxa_get_nandclk();
 
 	if (use_default) {
 		id = 0;
@@ -954,6 +954,13 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev)
 		free(host);
 		return host->mmio_base;
 	}
+	host->core_clk = clk_get(dev, NULL);
+	if (IS_ERR(host->core_clk)) {
+		free(host);
+		return (void *)host->core_clk;
+	}
+	clk_enable(host->core_clk);
+
 	if (pdata) {
 		host->keep_config = pdata->keep_config;
 		host->flash_bbt = pdata->flash_bbt;
-- 
2.1.0


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[PATCH 03/17] mtd: nand: Clarify Marvell Orion Kconfig prompt

[Sebastian Hesselbarth]

Kconfig prompt for Marvell Orion SoCs is missing a "Marvell"
prefix, add it to the prompt.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index ff265848459a..3426ec055756 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -92,7 +92,7 @@ config NAND_OMAP_GPMC
 
 config NAND_ORION
 	bool
-	prompt "Orion NAND driver"
+	prompt "Marvell Orion NAND driver"
 	depends on ARCH_KIRKWOOD
 	help
 	  Support for the Orion NAND controller, present in Kirkwood SoCs.
-- 
2.1.0


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[PATCH 04/17] arm: pxa: Remove pxa_get_nandclk()

[Sebastian Hesselbarth]

With a common clock provided for NAND controller, get rid of the
mach/clock.h way of getting the NAND clock.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 arch/arm/mach-pxa/include/mach/clock.h | 1 -
 arch/arm/mach-pxa/speed-pxa3xx.c       | 8 --------
 2 files changed, 9 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/clock.h b/arch/arm/mach-pxa/include/mach/clock.h
index 40f6223cd982..f86152f7af50 100644
--- a/arch/arm/mach-pxa/include/mach/clock.h
+++ b/arch/arm/mach-pxa/include/mach/clock.h
@@ -14,7 +14,6 @@
 unsigned long pxa_get_uartclk(void);
 unsigned long pxa_get_mmcclk(void);
 unsigned long pxa_get_lcdclk(void);
-unsigned long pxa_get_nandclk(void);
 unsigned long pxa_get_pwmclk(void);
 
 #endif	/* !__MACH_CLOCK_H */
diff --git a/arch/arm/mach-pxa/speed-pxa3xx.c b/arch/arm/mach-pxa/speed-pxa3xx.c
index 91e03eae4a52..6851911fa7aa 100644
--- a/arch/arm/mach-pxa/speed-pxa3xx.c
+++ b/arch/arm/mach-pxa/speed-pxa3xx.c
@@ -27,14 +27,6 @@ unsigned long pxa_get_pwmclk(void)
 	return BASE_CLK;
 }
 
-unsigned long pxa_get_nandclk(void)
-{
-	if (cpu_is_pxa320())
-		return 104000000;
-	else
-		return 156000000;
-}
-
 static int pxa3xx_clock_init(void)
 {
 	unsigned long nand_rate = (cpu_is_pxa320()) ? 104000000 : 156000000;
-- 
2.1.0


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[PATCH 05/17] mtd: nand_mrvl_nfc: Remove keep_config

[Sebastian Hesselbarth]

keep_config and it's corresponding DT property is meant for the
Linux kernel to keep the config setup by a boot-loader. As we
are the bootloader and it is not used at all, get rid of it.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index bdf949de0e7f..d220900e10db 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -149,7 +149,6 @@ struct mrvl_nand_host {
 
 	unsigned char		*data_buff;
 
-	int			keep_config;
 	int			ecc_strength;
 	int			ecc_step;
 
@@ -962,7 +961,6 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev)
 	clk_enable(host->core_clk);
 
 	if (pdata) {
-		host->keep_config = pdata->keep_config;
 		host->flash_bbt = pdata->flash_bbt;
 		host->ecc_strength = pdata->ecc_strength;
 		host->ecc_step = pdata->ecc_step_size;
@@ -981,8 +979,6 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 {
 	struct device_node *np = host->dev->device_node;
 
-	if (of_get_property(np, "marvell,nand-keep-config", NULL))
-		host->keep_config = 1;
 	of_property_read_u32(np, "num-cs", &host->cs);
 	if (of_get_nand_on_flash_bbt(np))
 		host->flash_bbt = 1;
-- 
2.1.0


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[PATCH 06/17] mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00

[Sebastian Hesselbarth]

If OOB data is not required on page program, we have to clear
the corresponding data with 0xff instead of 0x00.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index d220900e10db..b10d449da444 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -718,7 +718,7 @@ static int mrvl_nand_write_page_hwecc(struct mtd_info *mtd,
 		memcpy(host->data_buff + mtd->writesize, chip->oob_poi,
 		       mtd->oobsize);
 	else
-		memset(host->data_buff + mtd->writesize, 0, mtd->oobsize);
+		memset(host->data_buff + mtd->writesize, 0xff, mtd->oobsize);
 	dev_dbg(host->dev, "%s(buf=%p, oob_required=%d) => 0\n",
 		__func__, buf, oob_required);
 	return 0;
-- 
2.1.0


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[PATCH 07/17] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase

[Sebastian Hesselbarth]

Marvell NAND controller allows to enable an Auto Read Status feature
that will monitor NAND status during Erase and Program operations.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index b10d449da444..9d1803ccc6ba 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -561,6 +561,7 @@ static int prepare_set_command(struct mrvl_nand_host *host, int command,
 
 	case NAND_CMD_PAGEPROG:
 		host->ndcb0 |= NDCB0_CMD_TYPE(0x1)
+				| NDCB0_AUTO_RS
 				| NDCB0_DBC
 				| (NAND_CMD_PAGEPROG << 8)
 				| NAND_CMD_SEQIN
@@ -598,6 +599,7 @@ static int prepare_set_command(struct mrvl_nand_host *host, int command,
 
 	case NAND_CMD_ERASE1:
 		host->ndcb0 |= NDCB0_CMD_TYPE(2)
+				| NDCB0_AUTO_RS
 				| NDCB0_ADDR_CYC(3)
 				| NDCB0_DBC
 				| (NAND_CMD_ERASE2 << 8)
-- 
2.1.0


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[PATCH 08/17] mtd: nand_mrvl_nfc: Fix num-cs property parsing

[Sebastian Hesselbarth]

The "num-cs" property does not encode flashes CS line but number
of available CS signals. Fix wrong property parsing to ->cs by
adding proper ->num_cs variable to host struct.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 9d1803ccc6ba..a472d072fd68 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -152,6 +152,7 @@ struct mrvl_nand_host {
 	int			ecc_strength;
 	int			ecc_step;
 
+	int			num_cs;		/* avaiable CS signals */
 	int			cs;		/* selected chip 0/1 */
 	int			use_ecc;	/* use HW ECC ? */
 	int			use_spare;	/* use spare ? */
@@ -928,6 +929,7 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev)
 
 	pdata = dev->platform_data;
 	host = xzalloc(sizeof(*host));
+	host->num_cs = 1;
 	host->cs = 0;
 	mtd = &host->mtd;
 	mtd->priv = &host->chip;
@@ -981,7 +983,7 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 {
 	struct device_node *np = host->dev->device_node;
 
-	of_property_read_u32(np, "num-cs", &host->cs);
+	of_property_read_u32(np, "num-cs", &host->num_cs);
 	if (of_get_nand_on_flash_bbt(np))
 		host->flash_bbt = 1;
 
-- 
2.1.0


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[PATCH 09/17] mtd: nand_mrvl_nfc: Get ecc parameters from DT

[Sebastian Hesselbarth]

With DT helpers for ECC step size and strength, now use them on
Marvell NAND driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index a472d072fd68..676846e546a2 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -987,6 +987,14 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 	if (of_get_nand_on_flash_bbt(np))
 		host->flash_bbt = 1;
 
+	host->ecc_strength = of_get_nand_ecc_strength(np);
+	if (host->ecc_strength < 0)
+		host->ecc_strength = 0;
+
+	host->ecc_step = of_get_nand_ecc_step_size(np);
+	if (host->ecc_step < 0)
+		host->ecc_step = 0;
+
 	return 0;
 }
 
-- 
2.1.0


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[PATCH 10/17] mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths

[Sebastian Hesselbarth]

Newer versions of Marvell PXA3xx NFC also support BCH and therefore
higher ECC strengths than 1. Prepare for different ECC strength by
factoring out ECC init into separate functions by strength. Also,
add a new host variable that indicates BCH ECC.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 36 +++++++++++++++++++++++++++++-------
 1 file changed, 29 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 676846e546a2..5ff5ed72ff49 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -155,6 +155,7 @@ struct mrvl_nand_host {
 	int			num_cs;		/* avaiable CS signals */
 	int			cs;		/* selected chip 0/1 */
 	int			use_ecc;	/* use HW ECC ? */
+	int			ecc_bch;	/* HW ECC is BCH */
 	int			use_spare;	/* use spare ? */
 	int			flash_bbt;
 
@@ -823,32 +824,53 @@ static void mrvl_nand_config_flash(struct mrvl_nand_host *host)
 	host->reg_ndcr = ndcr;
 }
 
-static int pxa_ecc_init(struct mrvl_nand_host *host,
-			struct nand_ecc_ctrl *ecc,
-			int strength, int ecc_stepsize, int page_size)
+static int pxa_ecc_strength1(struct mrvl_nand_host *host,
+		struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
 {
-	if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
+	if (ecc_stepsize == 512 && page_size == 2048) {
 		host->chunk_size = 2048;
 		host->spare_size = 40;
 		host->ecc_size = 24;
+		host->ecc_bch = 0;
 		ecc->mode = NAND_ECC_HW;
 		ecc->size = 512;
 		ecc->strength = 1;
 		ecc->layout = &ecc_layout_2KB_hwecc;
+		return 0;
+	}
 
-	} else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
+	if (ecc_stepsize == 512 && page_size == 512) {
 		host->chunk_size = 512;
 		host->spare_size = 8;
 		host->ecc_size = 8;
+		host->ecc_bch = 0;
 		ecc->mode = NAND_ECC_HW;
 		ecc->size = 512;
 		ecc->layout = &ecc_layout_512B_hwecc;
 		ecc->strength = 1;
-	} else {
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
+static int pxa_ecc_init(struct mrvl_nand_host *host,
+			struct nand_ecc_ctrl *ecc,
+			int strength, int ecc_stepsize, int page_size)
+{
+	int ret = -ENODEV;
+
+	switch (strength) {
+	case 1:
+		ret = pxa_ecc_strength1(host, ecc, ecc_stepsize, page_size);
+		break;
+	}
+
+	if (ret) {
 		dev_err(host->dev,
 			"ECC strength %d at page size %d is not supported\n",
 			strength, page_size);
-		return -ENODEV;
+		return ret;
 	}
 
 	dev_info(host->dev, "ECC strength %d, ECC step size %d\n",
-- 
2.1.0


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[PATCH 11/17] mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions

[Sebastian Hesselbarth]

Marvell PXA3xx NAND flash controller IP has been reused in later SoCs
with additional HW features. Add HW BCH ECC as the first known HW
difference.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 5ff5ed72ff49..8a05fc88824b 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -142,6 +142,8 @@ struct mrvl_nand_host {
 	size_t			read_id_bytes;
 
 	void __iomem		*mmio_base;
+	unsigned int		hwflags;
+#define HWFLAGS_ECC_BCH		BIT(0)
 
 	unsigned int		buf_start;
 	unsigned int		buf_count;
@@ -234,9 +236,12 @@ static struct nand_ecclayout ecc_layout_2KB_hwecc = {
 #define mtd_info_to_host(mtd) ((struct mrvl_nand_host *) \
 			       (((struct nand_chip *)((mtd)->priv))->priv))
 
+const unsigned int pxa3xx_hwflags;
+
 static struct of_device_id mrvl_nand_dt_ids[] = {
 	{
 		.compatible = "marvell,pxa3xx-nand",
+		.data = &pxa3xx_hwflags,
 	},
 	{}
 };
@@ -1004,6 +1009,8 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev)
 static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 {
 	struct device_node *np = host->dev->device_node;
+	const struct of_device_id *match =
+		of_match_node(mrvl_nand_dt_ids, np);
 
 	of_property_read_u32(np, "num-cs", &host->num_cs);
 	if (of_get_nand_on_flash_bbt(np))
@@ -1017,6 +1024,8 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 	if (host->ecc_step < 0)
 		host->ecc_step = 0;
 
+	host->hwflags = ((unsigned int *)match->data)[0];
+
 	return 0;
 }
 
-- 
2.1.0


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[PATCH 12/17] mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC

[Sebastian Hesselbarth]

Add support for 4bit HW ECC modes supported by later IP versions.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 65 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 8a05fc88824b..2fb9823d1497 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -222,6 +222,31 @@ static struct nand_ecclayout ecc_layout_2KB_hwecc = {
 	.oobfree = { {0, 40} }
 };
 
+static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
+	.eccbytes = 32,
+	.eccpos = {
+		32, 33, 34, 35, 36, 37, 38, 39,
+		40, 41, 42, 43, 44, 45, 46, 47,
+		48, 49, 50, 51, 52, 53, 54, 55,
+		56, 57, 58, 59, 60, 61, 62, 63},
+	.oobfree = { {2, 30} }
+};
+
+static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
+	.eccbytes = 64,
+	.eccpos = {
+		32,  33,  34,  35,  36,  37,  38,  39,
+		40,  41,  42,  43,  44,  45,  46,  47,
+		48,  49,  50,  51,  52,  53,  54,  55,
+		56,  57,  58,  59,  60,  61,  62,  63,
+		96,  97,  98,  99,  100, 101, 102, 103,
+		104, 105, 106, 107, 108, 109, 110, 111,
+		112, 113, 114, 115, 116, 117, 118, 119,
+		120, 121, 122, 123, 124, 125, 126, 127},
+	/* Bootrom looks in bytes 0 & 5 for bad blocks */
+	.oobfree = { {1, 4}, {6, 26}, {64, 32} }
+};
+
 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
 #define NDTR0_tWH(c)	(min((c), 7) << 11)
@@ -859,6 +884,43 @@ static int pxa_ecc_strength1(struct mrvl_nand_host *host,
 	return -ENODEV;
 }
 
+static int pxa_ecc_strength4(struct mrvl_nand_host *host,
+		struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
+{
+	if (!(host->hwflags & HWFLAGS_ECC_BCH))
+		return -ENODEV;
+
+	/*
+	 * Required ECC: 4-bit correction per 512 bytes
+	 * Select: 16-bit correction per 2048 bytes
+	 */
+	if (ecc_stepsize == 512 && page_size == 2048) {
+		host->chunk_size = 2048;
+		host->spare_size = 32;
+		host->ecc_size = 32;
+		host->ecc_bch = 1;
+		ecc->mode = NAND_ECC_HW;
+		ecc->size = 2048;
+		ecc->layout = &ecc_layout_2KB_bch4bit;
+		ecc->strength = 16;
+		return 0;
+	}
+
+	if (ecc_stepsize == 512 && page_size == 4096) {
+		host->chunk_size = 2048;
+		host->spare_size = 32;
+		host->ecc_size = 32;
+		host->ecc_bch = 1;
+		ecc->mode = NAND_ECC_HW;
+		ecc->size = 2048;
+		ecc->layout = &ecc_layout_4KB_bch4bit;
+		ecc->strength = 16;
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
 static int pxa_ecc_init(struct mrvl_nand_host *host,
 			struct nand_ecc_ctrl *ecc,
 			int strength, int ecc_stepsize, int page_size)
@@ -869,6 +931,9 @@ static int pxa_ecc_init(struct mrvl_nand_host *host,
 	case 1:
 		ret = pxa_ecc_strength1(host, ecc, ecc_stepsize, page_size);
 		break;
+	case 4:
+		ret = pxa_ecc_strength4(host, ecc, ecc_stepsize, page_size);
+		break;
 	}
 
 	if (ret) {
-- 
2.1.0


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[PATCH 13/17] mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC

[Sebastian Hesselbarth]

Add support for 8bit HW ECC modes supported by later IP versions.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 2fb9823d1497..7c26ad15874d 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -247,6 +247,17 @@ static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
 	.oobfree = { {1, 4}, {6, 26}, {64, 32} }
 };
 
+static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
+	.eccbytes = 64,
+	.eccpos = {
+		32,  33,  34,  35,  36,  37,  38,  39,
+		40,  41,  42,  43,  44,  45,  46,  47,
+		48,  49,  50,  51,  52,  53,  54,  55,
+		56,  57,  58,  59,  60,  61,  62,  63},
+	/* Bootrom looks in bytes 0 & 5 for bad blocks */
+	.oobfree = { {1, 4}, {6, 26} }
+};
+
 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
 #define NDTR0_tWH(c)	(min((c), 7) << 11)
@@ -921,6 +932,31 @@ static int pxa_ecc_strength4(struct mrvl_nand_host *host,
 	return -ENODEV;
 }
 
+static int pxa_ecc_strength8(struct mrvl_nand_host *host,
+		struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
+{
+	if (!(host->hwflags & HWFLAGS_ECC_BCH))
+		return -ENODEV;
+
+	/*
+	 * Required ECC: 8-bit correction per 512 bytes
+	 * Select: 16-bit correction per 1024 bytes
+	 */
+	if (ecc_stepsize == 512 && page_size == 4096) {
+		host->chunk_size = 1024;
+		host->spare_size = 0;
+		host->ecc_size = 32;
+		host->ecc_bch = 1;
+		ecc->mode = NAND_ECC_HW;
+		ecc->size = 1024;
+		ecc->layout = &ecc_layout_4KB_bch8bit;
+		ecc->strength = 16;
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
 static int pxa_ecc_init(struct mrvl_nand_host *host,
 			struct nand_ecc_ctrl *ecc,
 			int strength, int ecc_stepsize, int page_size)
@@ -934,6 +970,9 @@ static int pxa_ecc_init(struct mrvl_nand_host *host,
 	case 4:
 		ret = pxa_ecc_strength4(host, ecc, ecc_stepsize, page_size);
 		break;
+	case 8:
+		ret = pxa_ecc_strength8(host, ecc, ecc_stepsize, page_size);
+		break;
 	}
 
 	if (ret) {
-- 
2.1.0


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[PATCH 14/17] mtd: nand_mrvl_nfc: Add support for HW BCH ECC

[Sebastian Hesselbarth]

Add support for HW BCH ECC for those HW versions that support it.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 7c26ad15874d..16752c1aa4d5 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -92,6 +92,8 @@
 #define NDSR_RDDREQ		(0x1 << 1)
 #define NDSR_WRCMDREQ		(0x1)
 
+#define NDECCCTRL_BCH_EN	BIT(0)
+
 #define NDCB0_LEN_OVRD		(0x1 << 28)
 #define NDCB0_ST_ROW_EN         (0x1 << 26)
 #define NDCB0_AUTO_RS		(0x1 << 25)
@@ -419,6 +421,17 @@ static void mrvl_nand_start(struct mrvl_nand_host *host)
 {
 	uint32_t ndcr;
 
+	if (host->hwflags & HWFLAGS_ECC_BCH) {
+		uint32_t reg = nand_readl(host, NDECCCTRL);
+
+		if (host->use_ecc && host->ecc_bch)
+			reg |= NDECCCTRL_BCH_EN;
+		else
+			reg &= ~NDECCCTRL_BCH_EN;
+
+		nand_writel(host, NDECCCTRL, reg);
+	}
+
 	ndcr = host->reg_ndcr;
 	if (host->use_ecc)
 		ndcr |= NDCR_ECC_EN;
@@ -787,8 +800,15 @@ static int mrvl_nand_read_page_hwecc(struct mtd_info *mtd,
 		else
 			ret = -EBADMSG;
 	}
-	if (ndsr & NDSR_CORERR)
-		ret = 1;
+	if (ndsr & NDSR_CORERR) {
+		if ((host->hwflags & HWFLAGS_ECC_BCH) && host->ecc_bch) {
+			ret = NDSR_ERR_CNT(ndsr);
+			ndsr &= ~(NDSR_ERR_CNT_MASK << NDSR_ERR_CNT_OFF);
+			nand_writel(host, NDSR, ndsr);
+		}
+		else
+			ret = 1;
+	}
 	dev_dbg(host->dev, "%s(buf=%p, page=%d, oob_required=%d) => %d\n",
 		__func__, buf, page, oob_required, ret);
 	return ret;
@@ -1001,6 +1021,11 @@ static int mrvl_nand_scan(struct mtd_info *mtd)
 	ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
 	host->reg_ndcr = ndcr;
 
+	/* Device detection must be done with BCH ECC disabled */
+	if (host->hwflags & HWFLAGS_ECC_BCH)
+		nand_writel(host, NDECCCTRL,
+			    nand_readl(host, NDECCCTRL) & ~NDECCCTRL_BCH_EN);
+
 	mrvl_nand_set_timing(host, true);
 	if (nand_scan_ident(mtd, 1, NULL)) {
 		host->reg_ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
-- 
2.1.0


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[PATCH 15/17] mtd: nand_mrvl_nfc: Add support for NDCB3 register

[Sebastian Hesselbarth]

Newer versions of PXA3xx NAND controller support a 4th Command Buffer
register. Add the required HWFLAGS and additional write to NDCB0.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 16752c1aa4d5..8594cf688d0c 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -53,6 +53,7 @@
 #define NDCB0		(0x48) /* Command Buffer0 */
 #define NDCB1		(0x4C) /* Command Buffer1 */
 #define NDCB2		(0x50) /* Command Buffer2 */
+#define NDCB3		(0x54) /* Command Buffer3 */
 
 #define NDCR_SPARE_EN		(0x1 << 31)
 #define NDCR_ECC_EN		(0x1 << 30)
@@ -146,6 +147,7 @@ struct mrvl_nand_host {
 	void __iomem		*mmio_base;
 	unsigned int		hwflags;
 #define HWFLAGS_ECC_BCH		BIT(0)
+#define HWFLAGS_HAS_NDCB3	BIT(1)
 
 	unsigned int		buf_start;
 	unsigned int		buf_count;
@@ -458,12 +460,19 @@ static void mrvl_nand_start(struct mrvl_nand_host *host)
 		dev_err(host->dev, "Waiting for command request failed\n");
 	} else {
 		/*
-		 * Writing 12 bytes to NDBC0 sets NDBC0, NDBC1 and NDBC2 !
+		 * Command buffer registers NDCB{0-2,3}
+		 * must be loaded by writing directly either 12 or 16
+		 * bytes directly to NDCB0, four bytes at a time.
+		 *
+		 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
+		 * but each NDCBx register can be read.
 		 */
 		nand_writel(host, NDSR, NDSR_WRCMDREQ);
 		nand_writel(host, NDCB0, host->ndcb0);
 		nand_writel(host, NDCB0, host->ndcb1);
 		nand_writel(host, NDCB0, host->ndcb2);
+		if (host->hwflags & HWFLAGS_HAS_NDCB3)
+			nand_writel(host, NDCB0, host->ndcb3);
 	}
 }
 
-- 
2.1.0


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[PATCH 16/17] mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP

[Sebastian Hesselbarth]

Marvell PXA3xx and Armada 370/XP share the same NAND controller IP
with some minor differences. With support for controller IP v2, now
allow to build the driver on Armada 370/XP.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/Kconfig         | 7 ++++---
 drivers/mtd/nand/nand_mrvl_nfc.c | 5 +++++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3426ec055756..2b4a478a03dd 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -99,10 +99,11 @@ config NAND_ORION
 
 config NAND_MRVL_NFC
 	bool
-	prompt "Marvell NAND driver"
-	depends on ARCH_PXA3XX
+	prompt "Marvell PXA3xx NAND driver"
+	depends on ARCH_ARMADA_370 || ARCH_ARMADA_XP || ARCH_PXA3XX
 	help
-	  Support for the PXA3xx NAND controller, present in pxa3xx SoCs.
+	  Support for the PXA3xx NAND controller, present in Armada 370/XP and
+	  PXA3xx SoCs.
 
 config NAND_ATMEL
 	bool
diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 8594cf688d0c..07dc1bdbe6cf 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -277,12 +277,17 @@ static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
 			       (((struct nand_chip *)((mtd)->priv))->priv))
 
 const unsigned int pxa3xx_hwflags;
+const unsigned int armada370_hwflags = HWFLAGS_ECC_BCH | HWFLAGS_HAS_NDCB3;
 
 static struct of_device_id mrvl_nand_dt_ids[] = {
 	{
 		.compatible = "marvell,pxa3xx-nand",
 		.data = &pxa3xx_hwflags,
 	},
+	{
+		.compatible = "marvell,armada370-nand",
+		.data = &armada370_hwflags,
+	},
 	{}
 };
 
-- 
2.1.0


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[PATCH 17/17] mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U

[Sebastian Hesselbarth]

This adds optimized timings for Samsung K9K8G08U 1Gb NAND flash.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 07dc1bdbe6cf..bf0e5e534e32 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -321,6 +321,7 @@ static struct mrvl_nand_timing timings[] = {
 	{ 0x46ec, 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 	{ 0xdaec, 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 	{ 0xd7ec, 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
+	{ 0xd3ec,  5, 20, 10,  12, 10,  12, 25000,  60, 10, },
 	{ 0xa12c, 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 	{ 0xb12c, 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 	{ 0xdc2c, 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
-- 
2.1.0


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Re: [PATCH 01/17] arm: pxa: Prepare for NAND clkdev lookup on PXA3xx

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP,
> prepare to provide a common clock for the NAND driver on PXA3xx.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Hi Sebastian,

I have several questions on the serie :
 - on which tree did you base that serie ?
   This patch for example doesn't apply on top of the trees I have

 - do you know that PXA has already support for the common clock framework
   (see drivers/clk/pxa/*) ?

As a consequence, CLKDEV_LOOKUP, COMMON_CLK, etc ... are already selected.

Moreover, I won't take patches to speed-pxa3xx.c unless there is a really strong
reason; at least it should be stronger than a simple clk_get(dev, NULL) solution.

Cheers.

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Re: [PATCH 01/17] arm: pxa: Prepare for NAND clkdev lookup on PXA3xx

[Robert Jarzmik]

Robert Jarzmik <robert.jarzmik@free.fr> writes:

> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>
>> To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP,
>> prepare to provide a common clock for the NAND driver on PXA3xx.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Hi Sebastian,
>
> I have several questions on the serie :
>  - on which tree did you base that serie ?
>    This patch for example doesn't apply on top of the trees I have
>
>  - do you know that PXA has already support for the common clock framework
>    (see drivers/clk/pxa/*) ?
>
> As a consequence, CLKDEV_LOOKUP, COMMON_CLK, etc ... are already selected.
>
> Moreover, I won't take patches to speed-pxa3xx.c unless there is a really strong
> reason; at least it should be stronger than a simple clk_get(dev, NULL) solution.
>
> Cheers.
Oh sorry Sebastian, my mailer betrayed me, I thought it was the kernel mailing
list, didn't notice the barebox list ...

Scratch all I said in the previous mail ...

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Re: [PATCH 05/17] mtd: nand_mrvl_nfc: Remove keep_config

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> keep_config and it's corresponding DT property is meant for the
> Linux kernel to keep the config setup by a boot-loader. As we
> are the bootloader and it is not used at all, get rid of it.

NAK on this one.
We're the "secondary bootloader". The first code running is the pxa3xx ROM code,
which initialized the NAND, read the OBMI, then read barebox, and transfered
control.

It can be assumed that for stacked NAND, the ROM code's timings are more
accurate than the generic ones, hence keep_config.

Cheers.

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Re: [PATCH 05/17] mtd: nand_mrvl_nfc: Remove keep_config

[Sebastian Hesselbarth]

On 09.10.2015 21:16, Robert Jarzmik wrote:
> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>
>> keep_config and it's corresponding DT property is meant for the
>> Linux kernel to keep the config setup by a boot-loader. As we
>> are the bootloader and it is not used at all, get rid of it.
>
> NAK on this one.
> We're the "secondary bootloader". The first code running is the pxa3xx ROM code,
> which initialized the NAND, read the OBMI, then read barebox, and transfered
> control.

Well, you are right with the secondary bootloader, but I doubt that
BootROM will _always_ have the optimal timings set but rather the
most conservative.

Also, as we are reusing the dts files that were made for Linux, it
may prevent barebox to pick more optimized settings.

Anyway, I am fine with keeping the keep-config parsing and remove
the property on some boards with using the barebox's dts overlays.

> It can be assumed that for stacked NAND, the ROM code's timings are more
> accurate than the generic ones, hence keep_config.

There is more issues here: Currently the binding of the nand
_controller_ also contains properties of the nand _device_, e.g.
mtd partitions are direct sub-nodes of the controller.

For the long run, i.e. including Linux rework, we should have
nand device sub-nodes, e.g.

nfc: nand@foo {
	compatible = "marvell,armada-370-nand";
	reg = <foo bar>;
	#address-cells = <1>;
	#size-cells = <0>;
	num-cs = <2>;

	flash@0 {
		reg = <0>; /* reg == CSn line */

		ecc-strength = <bla>;
		...

		partition@0 { ... };
	};

	flash@1 {
		reg = <1>;
		...
	};
};

Sebastian

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Re: [PATCH 05/17] mtd: nand_mrvl_nfc: Remove keep_config

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> On 09.10.2015 21:16, Robert Jarzmik wrote:
> Anyway, I am fine with keeping the keep-config parsing and remove
> the property on some boards with using the barebox's dts overlays.
Excellent.

>
>> It can be assumed that for stacked NAND, the ROM code's timings are more
>> accurate than the generic ones, hence keep_config.
>
> There is more issues here: Currently the binding of the nand
> _controller_ also contains properties of the nand _device_, e.g.
> mtd partitions are direct sub-nodes of the controller.
>
> For the long run, i.e. including Linux rework, we should have
> nand device sub-nodes, e.g.
I'm not really a devicetree expert, so I'll let others answer on that one. Yet I
find your example quite logical, having the controller and then devices on it.

Cheers.

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Re: [PATCH 01/17] arm: pxa: Prepare for NAND clkdev lookup on PXA3xx

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP,
> prepare to provide a common clock for the NAND driver on PXA3xx.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>

Cheers.

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Re: [PATCH 02/17] mtd: nand_mrvl_nfc: Use common clock for core clock

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> With PXA3xx now providing a common clock for the NAND clock, use it
> and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP
> to reuse the same driver.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>

Cheers.

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Re: [PATCH 04/17] arm: pxa: Remove pxa_get_nandclk()

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> With a common clock provided for NAND controller, get rid of the
> mach/clock.h way of getting the NAND clock.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>

Cheers.

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Re: [PATCH 06/17] mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> If OOB data is not required on page program, we have to clear
> the corresponding data with 0xff instead of 0x00.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>

Cheers.

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Re: [PATCH 07/17] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> Marvell NAND controller allows to enable an Auto Read Status feature
> that will monitor NAND status during Erase and Program operations.

Okay, I seem to remember barebox nand core code does read it after erase and
write anyway by issuing a status read command. Could you tell me what this
brings I don't see ?

Cheers.

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Re: [PATCH 15/17] mtd: nand_mrvl_nfc: Add support for NDCB3 register

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> Newer versions of PXA3xx NAND controller support a 4th Command Buffer
> register. Add the required HWFLAGS and additional write to NDCB0.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Hi quite like the hwflags approach, this is something that would be good in
linux kernel too :)

Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>

Cheers.

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Re: [PATCH 16/17] mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> Marvell PXA3xx and Armada 370/XP share the same NAND controller IP
> with some minor differences. With support for controller IP v2, now
> allow to build the driver on Armada 370/XP.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>

Cheers.

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Re: [PATCH 07/17] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase

[Sebastian Hesselbarth]

On 10.10.2015 10:44, Robert Jarzmik wrote:
> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>
>> Marvell NAND controller allows to enable an Auto Read Status feature
>> that will monitor NAND status during Erase and Program operations.
>
> Okay, I seem to remember barebox nand core code does read it after erase and
> write anyway by issuing a status read command. Could you tell me what this
> brings I don't see ?

The Auto RS feature makes the controller poll NAND status and holds
the READY bit until it is sure the NAND has finished erase/pageprog
command.

I have timeout issues without it and I am pretty sure it just hides
some timing misconfiguration on my side. _But_ at this point I think
it is better than reworking timing setup now. I will have a deeper look
at timing configuration for sure but this involves in-depth PXA vs
Armada (vs Berlin) timing register comparison.

And the reason why I didn't do any timing rework is that DT
infrastructure for passing timing information, ONFI parsing, aso
is still very vague. I really need more time to think about the
best way to deal with it.

For example, ONFI timings give you a set of timings but they do
not specify tPROG, tERASE and friends. Those have to be parsed
from some other ONFI commands. I really want to do this step
by step and it has to be in-sync with Linux mtd... something
that would stall NAND support on Armada a little while.

Bottom-line: If the Auto RS feature doesn't break PXA, I'd
appreciate if it is enabled at least until I can confirm
proper timings are being read for the device I have.

Sebastian



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Re: [PATCH 07/17] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> And the reason why I didn't do any timing rework is that DT
> infrastructure for passing timing information, ONFI parsing, aso
> is still very vague. I really need more time to think about the
> best way to deal with it.
>
> For example, ONFI timings give you a set of timings but they do
> not specify tPROG, tERASE and friends. Those have to be parsed
> from some other ONFI commands. I really want to do this step
> by step and it has to be in-sync with Linux mtd... something
> that would stall NAND support on Armada a little while.
>
> Bottom-line: If the Auto RS feature doesn't break PXA, I'd
> appreciate if it is enabled at least until I can confirm
> proper timings are being read for the device I have.
I'll make the test.
And yes, if no breakage, that's a good reason, it even deserves a note in the
commit message, at least that without it you have timeout issues on Armada.

Cheers.

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Re: [PATCH 15/17] mtd: nand_mrvl_nfc: Add support for NDCB3 register

[Sebastian Hesselbarth]

On 10.10.2015 10:48, Robert Jarzmik wrote:
> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>
>> Newer versions of PXA3xx NAND controller support a 4th Command Buffer
>> register. Add the required HWFLAGS and additional write to NDCB0.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Hi quite like the hwflags approach, this is something that would be good in
> linux kernel too :)

Definetely. I have the bad feeling that Berlin NAND IP is - as always -
"same same but different" ;)

> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
>
> Cheers.
>


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Re: [PATCH 09/17] mtd: nand_mrvl_nfc: Get ecc parameters from DT

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> With DT helpers for ECC step size and strength, now use them on
> Marvell NAND driver.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This one break the pxa (zylonite310_defconfig) build :
drivers/mtd/nand/nand_mrvl_nfc.c: In function ‘mrvl_nand_probe_dt’:
drivers/mtd/nand/nand_mrvl_nfc.c:1163:2: error: implicit declaration of function ‘of_get_nand_ecc_strength’ [-Werror=implicit-function-declaration]
  host->ecc_strength = of_get_nand_ecc_strength(np);
  ^
drivers/mtd/nand/nand_mrvl_nfc.c:1167:2: error: implicit declaration of function ‘of_get_nand_ecc_step_size’ [-Werror=implicit-function-declaration]
  host->ecc_step = of_get_nand_ecc_step_size(np);
  ^
cc1: some warnings being treated as errors

Cheers.

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Re: [PATCH 09/17] mtd: nand_mrvl_nfc: Get ecc parameters from DT

[Sascha Hauer]

On Sun, Oct 11, 2015 at 10:39:52PM +0200, Robert Jarzmik wrote:
> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
> 
> > With DT helpers for ECC step size and strength, now use them on
> > Marvell NAND driver.
> >
> > Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> This one break the pxa (zylonite310_defconfig) build :
> drivers/mtd/nand/nand_mrvl_nfc.c: In function ‘mrvl_nand_probe_dt’:
> drivers/mtd/nand/nand_mrvl_nfc.c:1163:2: error: implicit declaration of function ‘of_get_nand_ecc_strength’ [-Werror=implicit-function-declaration]
>   host->ecc_strength = of_get_nand_ecc_strength(np);
>   ^
> drivers/mtd/nand/nand_mrvl_nfc.c:1167:2: error: implicit declaration of function ‘of_get_nand_ecc_step_size’ [-Werror=implicit-function-declaration]
>   host->ecc_step = of_get_nand_ecc_step_size(np);
>   ^
> cc1: some warnings being treated as errors

Yes, we currently do not have these functions in barebox.

Sascha


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Re: [PATCH 11/17] mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions

[Sascha Hauer]

On Fri, Oct 09, 2015 at 12:06:13AM +0200, Sebastian Hesselbarth wrote:
> Marvell PXA3xx NAND flash controller IP has been reused in later SoCs
> with additional HW features. Add HW BCH ECC as the first known HW
> difference.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Robert Jarzmik <robert.jarzmik@free.fr>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> Cc: barebox@lists.infradead.org
> ---
>  drivers/mtd/nand/nand_mrvl_nfc.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
> index 5ff5ed72ff49..8a05fc88824b 100644
> --- a/drivers/mtd/nand/nand_mrvl_nfc.c
> +++ b/drivers/mtd/nand/nand_mrvl_nfc.c
> @@ -142,6 +142,8 @@ struct mrvl_nand_host {
>  	size_t			read_id_bytes;
>  
>  	void __iomem		*mmio_base;
> +	unsigned int		hwflags;
> +#define HWFLAGS_ECC_BCH		BIT(0)
>  
>  	unsigned int		buf_start;
>  	unsigned int		buf_count;
> @@ -234,9 +236,12 @@ static struct nand_ecclayout ecc_layout_2KB_hwecc = {
>  #define mtd_info_to_host(mtd) ((struct mrvl_nand_host *) \
>  			       (((struct nand_chip *)((mtd)->priv))->priv))
>  
> +const unsigned int pxa3xx_hwflags;

Could you make this a struct type? That makes it a bit easier to read
since it's a more common pattern. Also make it static.

Sascha

> +
>  static struct of_device_id mrvl_nand_dt_ids[] = {
>  	{
>  		.compatible = "marvell,pxa3xx-nand",
> +		.data = &pxa3xx_hwflags,
>  	},
>  	{}
>  };
> @@ -1004,6 +1009,8 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev)
>  static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
>  {
>  	struct device_node *np = host->dev->device_node;
> +	const struct of_device_id *match =
> +		of_match_node(mrvl_nand_dt_ids, np);
>  
>  	of_property_read_u32(np, "num-cs", &host->num_cs);
>  	if (of_get_nand_on_flash_bbt(np))
> @@ -1017,6 +1024,8 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
>  	if (host->ecc_step < 0)
>  		host->ecc_step = 0;
>  
> +	host->hwflags = ((unsigned int *)match->data)[0];
> +
>  	return 0;
>  }
>  
> -- 
> 2.1.0
> 
> 
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Re: [PATCH 09/17] mtd: nand_mrvl_nfc: Get ecc parameters from DT

[Sebastian Hesselbarth]

On 12.10.2015 08:28, Sascha Hauer wrote:
> On Sun, Oct 11, 2015 at 10:39:52PM +0200, Robert Jarzmik wrote:
>> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>>
>>> With DT helpers for ECC step size and strength, now use them on
>>> Marvell NAND driver.
>>>
>>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> This one break the pxa (zylonite310_defconfig) build :
>> drivers/mtd/nand/nand_mrvl_nfc.c: In function ‘mrvl_nand_probe_dt’:
>> drivers/mtd/nand/nand_mrvl_nfc.c:1163:2: error: implicit declaration of function ‘of_get_nand_ecc_strength’ [-Werror=implicit-function-declaration]
>>    host->ecc_strength = of_get_nand_ecc_strength(np);
>>    ^
>> drivers/mtd/nand/nand_mrvl_nfc.c:1167:2: error: implicit declaration of function ‘of_get_nand_ecc_step_size’ [-Werror=implicit-function-declaration]
>>    host->ecc_step = of_get_nand_ecc_step_size(np);
>>    ^
>> cc1: some warnings being treated as errors
>
> Yes, we currently do not have these functions in barebox.

Sorry, I simply failed to add this patch to the series. I'll
send the missing patch later today and make sure it'll be
included in v2 once all issues have been worked out.

Sebastian



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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> This series is, of course, untested on mach-pxa and needs a
> Tested-by. I have tested the new driver on Armada XP based
> Lenovo ix4-300d and todays -next.

I tested the parial serie patches :
* 7f109d9 (test-sebastian) mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths
* 1b791e9 mtd: nand_mrvl_nfc: Fix num-cs property parsing
* 2b1b488 mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase
* b198e62 mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00
* 56e0cfd mtd: nand_mrvl_nfc: Remove keep_config
* 1a42d8e arm: pxa: Remove pxa_get_nandclk()
* bc3db6f mtd: nand: Clarify Marvell Orion Kconfig prompt
* 15577a6 mtd: nand_mrvl_nfc: Use common clock for core clock
* 40debf2 arm: pxa: Prepare for NAND clkdev lookup on PXA3xx
* ace2e99 (HEAD, tmp) net: netconsole: add puts
* 0b8212a (tag: v2015.10.0) Release v2015.10.0

As a result I have :
	mrvl_nand mrvl_nand0: alloc nand resource failed
	mrvl_nand mrvl_nand0: probe failed: No such file or directory

This breaks zylonite support. Without the serie, the NAND works (ie. at "tmp"
branch").

Cheers.

--
Robert

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[PATCH] of: mtd: Import of_get_nand_ecc_{step_size, strength} from Linux

[Sebastian Hesselbarth]

This imports DT helpers for MTD ECC step size and strength from
Linux kernel.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: barebox@lists.infradead.org

Just for completeness, the patch that will import of_mtd helpers
for ECC from Linux. I'll make sure this is included in v2.

Sebastian
---
 drivers/of/of_mtd.c | 34 ++++++++++++++++++++++++++++++++++
 include/of_mtd.h    |  2 ++
 2 files changed, 36 insertions(+)

diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index 97f3095740f7..0956ee15d393 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -49,6 +49,40 @@ int of_get_nand_ecc_mode(struct device_node *np)
 EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
 
 /**
+ * of_get_nand_ecc_step_size - Get ECC step size associated to
+ * the required ECC strength (see below).
+ * @np:	Pointer to the given device_node
+ *
+ * return the ECC step size, or errno in error case.
+ */
+int of_get_nand_ecc_step_size(struct device_node *np)
+{
+	int ret;
+	u32 val;
+
+	ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
+	return ret ? ret : val;
+}
+EXPORT_SYMBOL_GPL(of_get_nand_ecc_step_size);
+
+/**
+ * of_get_nand_ecc_strength - Get required ECC strength over the
+ * correspnding step size as defined by 'nand-ecc-size'
+ * @np:	Pointer to the given device_node
+ *
+ * return the ECC strength, or errno in error case.
+ */
+int of_get_nand_ecc_strength(struct device_node *np)
+{
+	int ret;
+	u32 val;
+
+	ret = of_property_read_u32(np, "nand-ecc-strength", &val);
+	return ret ? ret : val;
+}
+EXPORT_SYMBOL_GPL(of_get_nand_ecc_strength);
+
+/**
  * of_get_nand_bus_width - Get nand bus witdh for given device_node
  * @np:	Pointer to the given device_node
  *
diff --git a/include/of_mtd.h b/include/of_mtd.h
index a5a8f20daff6..9f5b8a2796a2 100644
--- a/include/of_mtd.h
+++ b/include/of_mtd.h
@@ -12,6 +12,8 @@
 #include <of.h>
 
 int of_get_nand_ecc_mode(struct device_node *np);
+int of_get_nand_ecc_step_size(struct device_node *np);
+int of_get_nand_ecc_strength(struct device_node *np);
 int of_get_nand_bus_width(struct device_node *np);
 bool of_get_nand_on_flash_bbt(struct device_node *np);
 
-- 
2.1.0


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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Sebastian Hesselbarth]

On 12.10.2015 12:38, Robert Jarzmik wrote:
> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>
>> This series is, of course, untested on mach-pxa and needs a
>> Tested-by. I have tested the new driver on Armada XP based
>> Lenovo ix4-300d and todays -next.
>
> I tested the parial serie patches :
> * 7f109d9 (test-sebastian) mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths
> * 1b791e9 mtd: nand_mrvl_nfc: Fix num-cs property parsing
> * 2b1b488 mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase
> * b198e62 mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00
> * 56e0cfd mtd: nand_mrvl_nfc: Remove keep_config
> * 1a42d8e arm: pxa: Remove pxa_get_nandclk()
> * bc3db6f mtd: nand: Clarify Marvell Orion Kconfig prompt
> * 15577a6 mtd: nand_mrvl_nfc: Use common clock for core clock
> * 40debf2 arm: pxa: Prepare for NAND clkdev lookup on PXA3xx
> * ace2e99 (HEAD, tmp) net: netconsole: add puts
> * 0b8212a (tag: v2015.10.0) Release v2015.10.0
>
> As a result I have :
> 	mrvl_nand mrvl_nand0: alloc nand resource failed
> 	mrvl_nand mrvl_nand0: probe failed: No such file or directory
>
> This breaks zylonite support. Without the serie, the NAND works (ie. at "tmp"
> branch").

Ok, this is clk_get() failing to find the NAND clock. I have reworked
speed-3xx.c and Zylonite's board.c.

AFAIKS, clk_register_clkdev() does not link the clock to the nfc device,
therefore we have to use clkdev_add_physbase() in board.c.

I have prepared a branch for you based on above v2015.10.0 to ease
testing with all comments included so far:

https://github.com/shesselba/barebox-dove.git testing/nfc-for-robert

Thanks,
   Sebastian

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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> I have prepared a branch for you based on above v2015.10.0 to ease
> testing with all comments included so far:
>
> https://github.com/shesselba/barebox-dove.git testing/nfc-for-robert
That's cool, really.

It doesn't work yet :
	clk = clk_get_sys("nand", NULL);
	printf("%s(): clk = %p\n", __func__, clk);
=>
        zylonite_devices_init(): clk = fffffffe

Cheers.

-- 
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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Sebastian Hesselbarth]

On 12.10.2015 21:16, Robert Jarzmik wrote:
> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>
>> I have prepared a branch for you based on above v2015.10.0 to ease
>> testing with all comments included so far:
>>
>> https://github.com/shesselba/barebox-dove.git testing/nfc-for-robert
> That's cool, really.
>
> It doesn't work yet :
> 	clk = clk_get_sys("nand", NULL);
> 	printf("%s(): clk = %p\n", __func__, clk);
> =>
>          zylonite_devices_init(): clk = fffffffe

Ok, thanks for testing.

I've fast-forward pushed the branch with one last try for today again.
Misread clk_get, clk_find and clk_register_clkdev and friends.

Sebastian

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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> On 12.10.2015 21:16, Robert Jarzmik wrote:
>> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>>
>>> I have prepared a branch for you based on above v2015.10.0 to ease
>>> testing with all comments included so far:
>>>
>>> https://github.com/shesselba/barebox-dove.git testing/nfc-for-robert
>> That's cool, really.
>>
>> It doesn't work yet :
>> 	clk = clk_get_sys("nand", NULL);
>> 	printf("%s(): clk = %p\n", __func__, clk);
>> =>
>>          zylonite_devices_init(): clk = fffffffe
>
> Ok, thanks for testing.
>
> I've fast-forward pushed the branch with one last try for today again.
> Misread clk_get, clk_find and clk_register_clkdev and friends.
Well, I still have a probe error :
	alloc_nand_resource(): clk_get() -> fffffffe
	mrvl_nand mrvl_nand0: alloc nand resource failed
	mrvl_nand mrvl_nand0: probe failed: No such file or directory
	zylonite_devices_init(): clk = 83703328

Cheers.

-- 
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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Sebastian Hesselbarth]

On 13.10.2015 11:35, Robert Jarzmik wrote:
> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>
>> On 12.10.2015 21:16, Robert Jarzmik wrote:
>>> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>>>
>>>> I have prepared a branch for you based on above v2015.10.0 to ease
>>>> testing with all comments included so far:
>>>>
>>>> https://github.com/shesselba/barebox-dove.git testing/nfc-for-robert
>>> That's cool, really.
>>>
>>> It doesn't work yet :
>>> 	clk = clk_get_sys("nand", NULL);
>>> 	printf("%s(): clk = %p\n", __func__, clk);
>>> =>
>>>           zylonite_devices_init(): clk = fffffffe
>>
>> Ok, thanks for testing.
>>
>> I've fast-forward pushed the branch with one last try for today again.
>> Misread clk_get, clk_find and clk_register_clkdev and friends.
> Well, I still have a probe error :
> 	alloc_nand_resource(): clk_get() -> fffffffe
> 	mrvl_nand mrvl_nand0: alloc nand resource failed
> 	mrvl_nand mrvl_nand0: probe failed: No such file or directory
> 	zylonite_devices_init(): clk = 83703328

Hmm. I have to have a closer look at how clkdev lookup is supposed
to work then. Thanks for testing up to here, it will take a day or
two until I can get back to it.

Sebastian


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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Sascha Hauer]

On Tue, Oct 13, 2015 at 11:53:14AM +0200, Sebastian Hesselbarth wrote:
> On 13.10.2015 11:35, Robert Jarzmik wrote:
> >Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
> >
> >>On 12.10.2015 21:16, Robert Jarzmik wrote:
> >>>Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
> >>>
> >>>>I have prepared a branch for you based on above v2015.10.0 to ease
> >>>>testing with all comments included so far:
> >>>>
> >>>>https://github.com/shesselba/barebox-dove.git testing/nfc-for-robert
> >>>That's cool, really.
> >>>
> >>>It doesn't work yet :
> >>>	clk = clk_get_sys("nand", NULL);
> >>>	printf("%s(): clk = %p\n", __func__, clk);
> >>>=>
> >>>          zylonite_devices_init(): clk = fffffffe
> >>
> >>Ok, thanks for testing.
> >>
> >>I've fast-forward pushed the branch with one last try for today again.
> >>Misread clk_get, clk_find and clk_register_clkdev and friends.
> >Well, I still have a probe error :
> >	alloc_nand_resource(): clk_get() -> fffffffe
> >	mrvl_nand mrvl_nand0: alloc nand resource failed
> >	mrvl_nand mrvl_nand0: probe failed: No such file or directory
> >	zylonite_devices_init(): clk = 83703328
> 
> Hmm. I have to have a closer look at how clkdev lookup is supposed
> to work then. Thanks for testing up to here, it will take a day or
> two until I can get back to it.

In your temporary patch you have:

> @@ -67,6 +71,9 @@ static int zylonite_devices_init(void)
>  			   &smsc91x_pdata);
>  	add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL,
>  			   0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata);
> +	clk = clk_get_sys("nand", NULL);
> +	if (!IS_ERR(clk))
> +		clkdev_add_physbase(clk, 0x43100000, NULL);

Could it be that you register the clk lookup after the nand driver is probed? This
hunk should be moved before the nand device registration.

Sascha

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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Robert Jarzmik]

Sascha Hauer <s.hauer@pengutronix.de> writes:

> In your temporary patch you have:
>
>> @@ -67,6 +71,9 @@ static int zylonite_devices_init(void)
>>  			   &smsc91x_pdata);
>>  	add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL,
>>  			   0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata);
>> +	clk = clk_get_sys("nand", NULL);
>> +	if (!IS_ERR(clk))
>> +		clkdev_add_physbase(clk, 0x43100000, NULL);
>
> Could it be that you register the clk lookup after the nand driver is probed? This
> hunk should be moved before the nand device registration.
That's what I had thought, but changing the order gave me a panic, so I didn't
push forward.

This is what I had, decoded in [1].

Cheers.

--
Robert

[1] My backtrace with the inversion :

barebox@Zylonite:/ bootm /mnt/tftp/barebox.bin
bootm /mnt/tftp/barebox.bin
netconsole: netconsole initialized with 255.255.255.255:6662
eth0: 100Mbps full duplex link detected
DHCP client bound to address 192.168.1.232

Loading ARM barebox image '/mnt/tftp/barebox.bin'
commandline: ram=64M console=ttyS0,115200   mtdparts=pxa3xx_nand-0:128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)
arch_number: 1233
netconsole: port not set
netconsole: registered as netconsole-1
smc91c111 smc91c1110: chip is revision= 9, version= 2
mdio_bus: miibus0: probed
eth0: got preset MAC address: 00:0e:0c:a7:26:f7
zylonite_devices_init(): clk = 83703328
alloc_nand_resource(): clk_get() -> 83703328
unable to handle NULL pointer dereference at address 0x00000004
pc : [<83f15b9c>]    lr : [<83f15b90>]
sp : 83fffed0  ip : 000001b0  fp : 00000000
r10: 00000002  r9 : 83706888  r8 : 83f8c88c
r7 : 00000000  r6 : 00000000  r5 : 83706948  r4 : 00000000
r3 : 83706888  r2 : 43100000  r1 : 83f60783  r0 : 00000000
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
(mrvl_nand_probe+0x1ac/0x650) from device_probe (/drivers/base/driver.c:93)
(device_probe+0x30/0xb8) from match.part.3 (/drivers/base/driver.c:153)
(match.part.3+0x44/0x54) from register_device (/drivers/base/driver.c:192)
(register_device+0x120/0x15c) from add_generic_device (/drivers/base/resource.c:84)
(add_generic_device+0x3c/0x48) from zylonite_devices_init (/arch/arm/boards/zylonite/board.c:78)
(zylonite_devices_init+0x9c/0x108) from start_barebox (/common/startup.c:101)
(start_barebox+0x30/0xe8) from __start (/arch/arm/cpu/start.c:142)
(__start+0x124/0x13c) from 0x8386c290

(unwind_backtrace+0x0/0x90) from panic (/common/misc.c:209)
(panic+0x28/0x38) from do_exception (/arch/arm/cpu/interrupts.c:85)
(do_exception+0x10/0x14) from do_data_abort (/arch/arm/cpu/interrupts.c:139)
(do_data_abort+0x2c/0x38) from do_abort_6 (:?)
### ERROR ### Please RESET the board ###

And a special gift :
rj@belgarion:~/mio_linux/barebox$ addr2line -i -e barebox 0x83f15b9c
/home/rj/mio_linux/barebox/drivers/mtd/nand/nand_mrvl_nfc.c:1172
/home/rj/mio_linux/barebox/drivers/mtd/nand/nand_mrvl_nfc.c:1202

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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Sascha Hauer]

On Tue, Oct 13, 2015 at 12:38:51PM +0200, Robert Jarzmik wrote:
> Sascha Hauer <s.hauer@pengutronix.de> writes:
> 
> > In your temporary patch you have:
> >
> >> @@ -67,6 +71,9 @@ static int zylonite_devices_init(void)
> >>  			   &smsc91x_pdata);
> >>  	add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL,
> >>  			   0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata);
> >> +	clk = clk_get_sys("nand", NULL);
> >> +	if (!IS_ERR(clk))
> >> +		clkdev_add_physbase(clk, 0x43100000, NULL);
> >
> > Could it be that you register the clk lookup after the nand driver is probed? This
> > hunk should be moved before the nand device registration.
> That's what I had thought, but changing the order gave me a panic, so I didn't
> push forward.
> 
> This is what I had, decoded in [1].
> 
> Cheers.
> 
> --
> Robert
> 
> [1] My backtrace with the inversion :
> 
> barebox@Zylonite:/ bootm /mnt/tftp/barebox.bin
> bootm /mnt/tftp/barebox.bin
> netconsole: netconsole initialized with 255.255.255.255:6662
> eth0: 100Mbps full duplex link detected
> DHCP client bound to address 192.168.1.232
> 
> Loading ARM barebox image '/mnt/tftp/barebox.bin'
> commandline: ram=64M console=ttyS0,115200   mtdparts=pxa3xx_nand-0:128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)
> arch_number: 1233
> netconsole: port not set
> netconsole: registered as netconsole-1
> smc91c111 smc91c1110: chip is revision= 9, version= 2
> mdio_bus: miibus0: probed
> eth0: got preset MAC address: 00:0e:0c:a7:26:f7
> zylonite_devices_init(): clk = 83703328
> alloc_nand_resource(): clk_get() -> 83703328
> unable to handle NULL pointer dereference at address 0x00000004
> pc : [<83f15b9c>]    lr : [<83f15b90>]
> sp : 83fffed0  ip : 000001b0  fp : 00000000
> r10: 00000002  r9 : 83706888  r8 : 83f8c88c
> r7 : 00000000  r6 : 00000000  r5 : 83706948  r4 : 00000000
> r3 : 83706888  r2 : 43100000  r1 : 83f60783  r0 : 00000000
> Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
> (mrvl_nand_probe+0x1ac/0x650) from device_probe (/drivers/base/driver.c:93)
> (device_probe+0x30/0xb8) from match.part.3 (/drivers/base/driver.c:153)
> (match.part.3+0x44/0x54) from register_device (/drivers/base/driver.c:192)
> (register_device+0x120/0x15c) from add_generic_device (/drivers/base/resource.c:84)
> (add_generic_device+0x3c/0x48) from zylonite_devices_init (/arch/arm/boards/zylonite/board.c:78)
> (zylonite_devices_init+0x9c/0x108) from start_barebox (/common/startup.c:101)
> (start_barebox+0x30/0xe8) from __start (/arch/arm/cpu/start.c:142)
> (__start+0x124/0x13c) from 0x8386c290
> 
> (unwind_backtrace+0x0/0x90) from panic (/common/misc.c:209)
> (panic+0x28/0x38) from do_exception (/arch/arm/cpu/interrupts.c:85)
> (do_exception+0x10/0x14) from do_data_abort (/arch/arm/cpu/interrupts.c:139)
> (do_data_abort+0x2c/0x38) from do_abort_6 (:?)
> ### ERROR ### Please RESET the board ###
> 
> And a special gift :
> rj@belgarion:~/mio_linux/barebox$ addr2line -i -e barebox 0x83f15b9c
> /home/rj/mio_linux/barebox/drivers/mtd/nand/nand_mrvl_nfc.c:1172
> /home/rj/mio_linux/barebox/drivers/mtd/nand/nand_mrvl_nfc.c:1202

This seems to be in mrvl_nand_probe_dt() and we are probing without
device tree here, right?

We have:

	struct device_node *np = host->dev->device_node;
	const struct of_device_id *match =
		of_match_node(mrvl_nand_dt_ids, np);
	const struct mrvl_nand_variant *variant = match->data;

of_match_node() is a static inline wrapper returning NULL, so next line
we dereference a NULL pointer.

Sascha

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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Sebastian Hesselbarth]

On 13.10.2015 12:38, Robert Jarzmik wrote:
> Sascha Hauer <s.hauer@pengutronix.de> writes:
>
>> In your temporary patch you have:
>>
>>> @@ -67,6 +71,9 @@ static int zylonite_devices_init(void)
>>>   			   &smsc91x_pdata);
>>>   	add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL,
>>>   			   0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata);
>>> +	clk = clk_get_sys("nand", NULL);
>>> +	if (!IS_ERR(clk))
>>> +		clkdev_add_physbase(clk, 0x43100000, NULL);
>>
>> Could it be that you register the clk lookup after the nand driver is probed? This
>> hunk should be moved before the nand device registration.
> That's what I had thought, but changing the order gave me a panic, so I didn't
> push forward.

Robert,

I pushed another version of the patch set with the following changes:

- Bail out of mrvl_nand_probe_dt early if
   !IS_ENABLED(CONFIG_OFTREE) || host->dev->platform_data

- Move clkdev_add_physbase() before add_generic_device("mrvl_nand")
   (Thanks Sascha!)

I hope the issues are resolved now and thanks a lot for testing
again!

Sebastian

> This is what I had, decoded in [1].
>
> Cheers.
>
> --
> Robert
>
> [1] My backtrace with the inversion :
>
> barebox@Zylonite:/ bootm /mnt/tftp/barebox.bin
> bootm /mnt/tftp/barebox.bin
> netconsole: netconsole initialized with 255.255.255.255:6662
> eth0: 100Mbps full duplex link detected
> DHCP client bound to address 192.168.1.232
>
> Loading ARM barebox image '/mnt/tftp/barebox.bin'
> commandline: ram=64M console=ttyS0,115200   mtdparts=pxa3xx_nand-0:128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)
> arch_number: 1233
> netconsole: port not set
> netconsole: registered as netconsole-1
> smc91c111 smc91c1110: chip is revision= 9, version= 2
> mdio_bus: miibus0: probed
> eth0: got preset MAC address: 00:0e:0c:a7:26:f7
> zylonite_devices_init(): clk = 83703328
> alloc_nand_resource(): clk_get() -> 83703328
> unable to handle NULL pointer dereference at address 0x00000004
> pc : [<83f15b9c>]    lr : [<83f15b90>]
> sp : 83fffed0  ip : 000001b0  fp : 00000000
> r10: 00000002  r9 : 83706888  r8 : 83f8c88c
> r7 : 00000000  r6 : 00000000  r5 : 83706948  r4 : 00000000
> r3 : 83706888  r2 : 43100000  r1 : 83f60783  r0 : 00000000
> Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
> (mrvl_nand_probe+0x1ac/0x650) from device_probe (/drivers/base/driver.c:93)
> (device_probe+0x30/0xb8) from match.part.3 (/drivers/base/driver.c:153)
> (match.part.3+0x44/0x54) from register_device (/drivers/base/driver.c:192)
> (register_device+0x120/0x15c) from add_generic_device (/drivers/base/resource.c:84)
> (add_generic_device+0x3c/0x48) from zylonite_devices_init (/arch/arm/boards/zylonite/board.c:78)
> (zylonite_devices_init+0x9c/0x108) from start_barebox (/common/startup.c:101)
> (start_barebox+0x30/0xe8) from __start (/arch/arm/cpu/start.c:142)
> (__start+0x124/0x13c) from 0x8386c290
>
> (unwind_backtrace+0x0/0x90) from panic (/common/misc.c:209)
> (panic+0x28/0x38) from do_exception (/arch/arm/cpu/interrupts.c:85)
> (do_exception+0x10/0x14) from do_data_abort (/arch/arm/cpu/interrupts.c:139)
> (do_data_abort+0x2c/0x38) from do_abort_6 (:?)
> ### ERROR ### Please RESET the board ###
>
> And a special gift :
> rj@belgarion:~/mio_linux/barebox$ addr2line -i -e barebox 0x83f15b9c
> /home/rj/mio_linux/barebox/drivers/mtd/nand/nand_mrvl_nfc.c:1172
> /home/rj/mio_linux/barebox/drivers/mtd/nand/nand_mrvl_nfc.c:1202
>


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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> Robert,
>
> I pushed another version of the patch set with the following changes:
>
> - Bail out of mrvl_nand_probe_dt early if
>   !IS_ENABLED(CONFIG_OFTREE) || host->dev->platform_data
>
> - Move clkdev_add_physbase() before add_generic_device("mrvl_nand")
>   (Thanks Sascha!)
>
> I hope the issues are resolved now and thanks a lot for testing
> again!
Nope, see [1].
It's this part with match which is NULL in my case:
	const struct mrvl_nand_variant *variant = match->data;

Cheers.

-- 
Robert

[1] Backtrace
unable to handle NULL pointer dereference at address 0x00000004
pc : [<83f15b90>]    lr : [<83f15b7c>]
sp : 83fffed0  ip : 000001c8  fp : 00000000
r10: 00000002  r9 : 83706870  r8 : 83f8c74c
r7 : 00000000  r6 : 00000000  r5 : 83706930  r4 : 00000000
r3 : 83706870  r2 : 83f8518c  r1 : 00000000  r0 : 00000000
Flags: NzCv  IRQs off  FIQs off  Mode SVC_32
[<83f15b90>] (mrvl_nand_probe+0x1a0/0x604) from [<83f0bed8>] (device_probe+0x30/0xb8)
[<83f0bed8>] (device_probe+0x30/0xb8) from [<83f0bfa4>] (match.part.3+0x44/0x54)
[<83f0bfa4>] (match.part.3+0x44/0x54) from [<83f0c518>] (register_device+0x120/0x15c)
[<83f0c518>] (register_device+0x120/0x15c) from [<83f0c7ac>] (add_generic_device+0x3c/0x48)
[<83f0c7ac>] (add_generic_device+0x3c/0x48) from [<83f5a8ec>] (zylonite_devices_init+0x84/0xe8)
[<83f5a8ec>] (zylonite_devices_init+0x84/0xe8) from [<83f01258>] (start_barebox+0x30/0xe8)
[<83f01258>] (start_barebox+0x30/0xe8) from [<83f5cddc>] (__start+0x124/0x13c)
[<83f5cddc>] (__start+0x124/0x13c) from [<8386c1d0>] (0x8386c1d0)

[<83f5c534>] (unwind_backtrace+0x0/0x90) from [<83f01628>] (panic+0x28/0x38)
[<83f01628>] (panic+0x28/0x38) from [<83f5cb9c>] (do_exception+0x10/0x14)
[<83f5cb9c>] (do_exception+0x10/0x14) from [<83f5cc28>] (do_data_abort+0x2c/0x38)
[<83f5cc28>] (do_data_abort+0x2c/0x38) from [<83f5c8f4>] (do_abort_6+0x48/0x54)

@belgarion:~/mio_linux/barebox$ arm-none-eabi-addr2line -e barebox -i 0x83f15b90
/home/rj/mio_linux/barebox/drivers/mtd/nand/nand_mrvl_nfc.c:1174
/home/rj/mio_linux/barebox/drivers/mtd/nand/nand_mrvl_nfc.c:1204

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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Sebastian Hesselbarth]

On 16.10.2015 20:40, Robert Jarzmik wrote:
> It's this part with match which is NULL in my case:
> 	const struct mrvl_nand_variant *variant = match->data;

Ok. I now moved the of_match and variant assignment below the
OF protection. New version at the same branch.

Sebastian


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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Robert Jarzmik]

Robert Jarzmik <robert.jarzmik@free.fr> writes:

> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>
>> Robert,
>>
>> I pushed another version of the patch set with the following changes:

Okay, with the latest version (a6400be (HEAD, test-sebastian) mtd:
nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U) zylonite is working
all right.

Cheers.

--
Robert

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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Sebastian Hesselbarth]

On 20.10.2015 21:25, Robert Jarzmik wrote:
> Robert Jarzmik <robert.jarzmik@free.fr> writes:
> 
>> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>>
>>> Robert,
>>>
>>> I pushed another version of the patch set with the following changes:
> 
> Okay, with the latest version (a6400be (HEAD, test-sebastian) mtd:
> nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U) zylonite is working
> all right.

Robert,

thanks again for patient testing. I ran out of time before
vacation but now I plan to resend the series rebased on
latest barebox.

I assume you are fine with me adding your Tested-by on the
next version?

Sebastian


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Re: [PATCH 00/17] Armada 370/XP NAND driver

[Robert Jarzmik]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> On 20.10.2015 21:25, Robert Jarzmik wrote:
>> Robert Jarzmik <robert.jarzmik@free.fr> writes:
>> 
>>> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:
>>>
>>>> Robert,
>>>>
>>>> I pushed another version of the patch set with the following changes:
>> 
>> Okay, with the latest version (a6400be (HEAD, test-sebastian) mtd:
>> nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U) zylonite is working
>> all right.
>
> Robert,
>
> thanks again for patient testing. I ran out of time before
> vacation but now I plan to resend the series rebased on
> latest barebox.
>
> I assume you are fine with me adding your Tested-by on the
> next version?
Sure.

Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>

Cheers.

-- 
Robert

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