* boards/enclustra-sa2: add new board (HELP NEEDED)
@ 2025-07-03 14:21 David Picard
2025-07-03 20:35 ` Sascha Hauer
0 siblings, 1 reply; 2+ messages in thread
From: David Picard @ 2025-07-03 14:21 UTC (permalink / raw)
To: MList-Barebox
Hello,
I'm trying to port the Enclustra SA2 module. I started off the Terasic
DE0 nano Soc board, that I could run with success previously. They both
have a Cyclone V SoC FPGA. I added some pr_debug().
My code is here, in the board-enclustra-sa2 branch:
https://github.com/dpproto/barebox
It hangs when the execution jumps to the uncompressed Barebox image, and
I'm really stuck.
Enclustra provides a U-Boot configuration, with handoff files. I tried
to compare them with those I copied from a sample Quartus project they
provide too. I couldn't notice striking differences, although it's not
easy to compare because they used an older version of Quartus.
- The addresses and sizes in the log output below don't seem to exceed
SDRAM boundaries, do they?
- Any hint on anything to check?
David
=============================
barebox 2025.06.1 #1 Thu Jul 3 10:53:43 CEST 2025
Board: SoCFPGA
No consoles were activated. Activating all consoles as fallback!
dw_mmc dw_mmc0: registered as mci0
mci0: detected SD card version 2.0
mci0: registered disk0
starting bootloader...
arch/arm/boards/enclustra-sa2/lowlevel.c: __start_socfpga_sa2() >>> start
include/mach/socfpga/lowlevel.h: start_socfpga_c5_common() >>> start
include/mach/socfpga/lowlevel.h: start_socfpga_c5_common() >>>
arm_cpu_lowlevel_init() OK
include/mach/socfpga/lowlevel.h: start_socfpga_c5_common() >>>
fdt_blob=0x00002320 fdt=0x1ff87ae8 size=0x40000000
include/mach/socfpga/lowlevel.h: start_socfpga_c5_common() >>> calling
barebox_arm_entry()...
uncompress.c: memory at 0x00000000, size 0x40000000
mmu: enabling MMU, ttb @ 0x3ffe0000
endmem = 0x40000000
arm_mem_scratch = 0x3fff8000+0x00008000
arm_mem_stack = 0x3fff0000+0x00008000
arm_mem_ttb = 0x3ffe0000+0x00010000
arm_mem_barebox_image = 0x3fe00000+0x00200000
arm_mem_early_malloc = 0x3fde0000+0x00020000
membase = 0x00000000+0x40000000
uncompress.c: uncompressing barebox binary at 0x1ff8c800 (size
0x00056b67) to 0x3fe00000 (uncompressed size: 0x000778b0)
uncompress.c: jumping to uncompressed image at 0x3fe00001
uncompress.c: calling armv7_switch_to_hyp()...
uncompress.c: armv7_switch_to_hyp() OK. Now jumping...
=============================
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: boards/enclustra-sa2: add new board (HELP NEEDED)
2025-07-03 14:21 boards/enclustra-sa2: add new board (HELP NEEDED) David Picard
@ 2025-07-03 20:35 ` Sascha Hauer
0 siblings, 0 replies; 2+ messages in thread
From: Sascha Hauer @ 2025-07-03 20:35 UTC (permalink / raw)
To: David Picard; +Cc: MList-Barebox
On Thu, Jul 03, 2025 at 04:21:52PM +0200, David Picard wrote:
> Hello,
>
> I'm trying to port the Enclustra SA2 module. I started off the Terasic DE0
> nano Soc board, that I could run with success previously. They both have a
> Cyclone V SoC FPGA. I added some pr_debug().
>
> My code is here, in the board-enclustra-sa2 branch:
> https://github.com/dpproto/barebox
>
> It hangs when the execution jumps to the uncompressed Barebox image, and I'm
> really stuck.
>
> Enclustra provides a U-Boot configuration, with handoff files. I tried to
> compare them with those I copied from a sample Quartus project they provide
> too. I couldn't notice striking differences, although it's not easy to
> compare because they used an older version of Quartus.
>
> - The addresses and sizes in the log output below don't seem to exceed SDRAM
> boundaries, do they?
> - Any hint on anything to check?
>
> David
>
> =============================
> barebox 2025.06.1 #1 Thu Jul 3 10:53:43 CEST 2025
>
>
> Board: SoCFPGA
> No consoles were activated. Activating all consoles as fallback!
> dw_mmc dw_mmc0: registered as mci0
> mci0: detected SD card version 2.0
> mci0: registered disk0
> starting bootloader...
> arch/arm/boards/enclustra-sa2/lowlevel.c: __start_socfpga_sa2() >>> start
> include/mach/socfpga/lowlevel.h: start_socfpga_c5_common() >>> start
> include/mach/socfpga/lowlevel.h: start_socfpga_c5_common() >>>
> arm_cpu_lowlevel_init() OK
> include/mach/socfpga/lowlevel.h: start_socfpga_c5_common() >>>
> fdt_blob=0x00002320 fdt=0x1ff87ae8 size=0x40000000
This looks strange. Your fdt blob is at offset 0x2320 in the binary, but
the final pointer is at 0x1ff87ae8 meaning that your binary is only 8
byte aligned in memory. I would expect a bigger alignment here. The
buffer should be allocated by read_file_2(). Could you replace the
call to calloc there with a memalign() call aligning to something like
64 bytes?
Could be a red herring though.
> include/mach/socfpga/lowlevel.h: start_socfpga_c5_common() >>> calling
> barebox_arm_entry()...
> uncompress.c: memory at 0x00000000, size 0x40000000
> mmu: enabling MMU, ttb @ 0x3ffe0000
> endmem = 0x40000000
> arm_mem_scratch = 0x3fff8000+0x00008000
> arm_mem_stack = 0x3fff0000+0x00008000
> arm_mem_ttb = 0x3ffe0000+0x00010000
> arm_mem_barebox_image = 0x3fe00000+0x00200000
> arm_mem_early_malloc = 0x3fde0000+0x00020000
> membase = 0x00000000+0x40000000
> uncompress.c: uncompressing barebox binary at 0x1ff8c800 (size 0x00056b67)
> to 0x3fe00000 (uncompressed size: 0x000778b0)
> uncompress.c: jumping to uncompressed image at 0x3fe00001
> uncompress.c: calling armv7_switch_to_hyp()...
> uncompress.c: armv7_switch_to_hyp() OK. Now jumping...
Have you tried adding some debug output to barebox_non_pbl_start()?
pr_debug and friends will only work after setup_c() is called, but you
can either use putc_ll() before that or directly write to the UART TX
register.
Sascha
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