Re: [PATCH] ARM: boards: Add support for phyBOARD-Segin i.MX 93

[Bastian Krause <bst@pengutronix.de>]

Hi Jonas,

On 3/4/25 5:24 PM, Jonas Rebmann wrote:
> This patch adds support for the phyBOARD-Segin i.MX 93 and the phyCORE
> i.MX 93 SoM it is based upon.
> 
> Note that support is only provided for the standard configuration
> featuring 1GB RAM as testing was only possible on that variant and only
> the single-configuration lpddr4_timing.c as initially committed to
> u-boot in 7c1f8ce3956 worked.
> 
> The 1GB configuration from later revisions results in a freeze during
> dram setup.
> 
> The following functionality has been tested:
>   - barebox starts via imxusbloader, tftp and emmc
>   - both ethertnet interfaces work
>   - barebox_update to emmc
>   - boot kernel via network
>   - USB OTG
>   - USB mass storage on USB Host Port
>   - reset
> 
> Signed-off-by: Jonas Rebmann <jre@pengutronix.de>
> ---
>   arch/arm/boards/Makefile                           |    1 +
>   arch/arm/boards/phytec-phycore-imx93/Makefile      |    2 +
>   arch/arm/boards/phytec-phycore-imx93/board.c       |   56 +
>   arch/arm/boards/phytec-phycore-imx93/lowlevel.c    |   60 +
>   .../boards/phytec-phycore-imx93/lpddr4_timing.c    | 1546 ++++++++++++++++++++
>   arch/arm/configs/imx_v8_defconfig                  |    1 +
>   arch/arm/configs/multi_v8_defconfig                |    1 +
>   arch/arm/dts/Makefile                              |    1 +
>   arch/arm/dts/imx93-phyboard-segin-downstream.dtsi  |  269 ++++
>   arch/arm/dts/imx93-phyboard-segin.dts              |   28 +
>   arch/arm/mach-imx/Kconfig                          |    9 +
>   images/Makefile.imx                                |    4 +
>   12 files changed, 1978 insertions(+)
> 
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index c6104d04329774655712db5aaf6df671fd74142e..1e67b304f1855df2c32305638c3d9029ed0994c6 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -78,6 +78,7 @@ obj-$(CONFIG_MACH_PCM038)			+= phytec-phycore-imx27/
>   obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X)		+= phytec-som-am335x/
>   obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6)		+= phytec-som-imx6/
>   obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7)		+= phytec-phycore-imx7/
> +obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX93)		+= phytec-phycore-imx93/
>   obj-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1)	+= phytec-phycore-stm32mp1/
>   obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM)		+= phytec-som-imx8mm/
>   obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ)		+= phytec-som-imx8mq/
> diff --git a/arch/arm/boards/phytec-phycore-imx93/Makefile b/arch/arm/boards/phytec-phycore-imx93/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..ae29bb9249e62cb649e21e580559383fa9d18386
> --- /dev/null
> +++ b/arch/arm/boards/phytec-phycore-imx93/Makefile
> @@ -0,0 +1,2 @@
> +lwl-y += lowlevel.o lpddr4_timing.o
> +obj-y += board.o
> diff --git a/arch/arm/boards/phytec-phycore-imx93/board.c b/arch/arm/boards/phytec-phycore-imx93/board.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..149248ca654624826d0e8f6fe0f1f42c2747e248
> --- /dev/null
> +++ b/arch/arm/boards/phytec-phycore-imx93/board.c
> @@ -0,0 +1,56 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#define pr_fmt(fmt) "phyCORE imx93: " fmt
> +
> +#include <common.h>
> +#include <init.h>
> +#include <linux/kernel.h>
> +#include <environment.h>
> +#include <mfd/pca9450.h>
> +#include <deep-probe.h>
> +#include <mach/imx/bbu.h>
> +#include <linux/pinctrl/consumer.h>
> +
> +static void phycore_imx93_init_pmic(struct regmap *map)
> +{
> +	/* set WDOG_B_CFG to cold reset */
> +	regmap_write(map, PCA9450_RESET_CTRL, 0xA1);
> +}
> +
> +static int phycore_imx93_probe(struct device *dev)
> +{
> +	struct device_node *np;
> +
> +	pca9450_register_init_callback(phycore_imx93_init_pmic);
> +
> +	/*
> +	 * The phy on the EQOS has its MDIO lines connected to the FEC. The phy
> +	 * registers can only be successfully read when the EQOS pinctrl setup
> +	 * has been done. The phys on the FEC MDIO bus are probed during the
> +	 * FEC driver probe, so do the EQOS pinctrl setup here to make sure it's
> +	 * done before the FEC probes.
> +	 */
> +	np = of_find_compatible_node(dev->of_node, NULL, "nxp,imx93-dwmac-eqos");
> +	BUG_ON(!np);
> +	of_pinctrl_select_state_default(np);
> +
> +	imx9_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", 0);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id phycore_imx93_of_match[] = {
> +	{
> +		.compatible = "phytec,imx93-phyboard-segin",
> +	},
> +	{ /* sentinel */ },
> +};
> +
> +static struct driver phycore_imx93_board_driver = {
> +	.name = "board-phycore_imx93",
> +	.probe = phycore_imx93_probe,
> +	.of_compatible = phycore_imx93_of_match,
> +};
> +coredevice_platform_driver(phycore_imx93_board_driver);
> +
> +BAREBOX_DEEP_PROBE_ENABLE(phycore_imx93_of_match);
> diff --git a/arch/arm/boards/phytec-phycore-imx93/lowlevel.c b/arch/arm/boards/phytec-phycore-imx93/lowlevel.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..7678d2f2633ea07e532684f999b62ddecc2b79dc
> --- /dev/null
> +++ b/arch/arm/boards/phytec-phycore-imx93/lowlevel.c
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <common.h>
> +#include <debug_ll.h>
> +#include <mach/imx/debug_ll.h>
> +#include <mach/imx/generic.h>
> +#include <mach/imx/xload.h>
> +#include <asm/barebox-arm.h>
> +#include <soc/imx9/ddr.h>
> +#include <mach/imx/atf.h>
> +#include <mach/imx/xload.h>
> +#include <mach/imx/romapi.h>

This shouldn't be needed.

Regards,
Bastian

> +#include <mach/imx/esdctl.h>
> +#include <pbl/i2c.h>
> +
> +extern char __dtb_z_imx93_phyboard_segin_start[];
> +extern struct dram_timing_info dram_timing;
> +
> +static noinline void phycore_imx93_continue(void)
> +{
> +	void *base = IOMEM(MX9_UART1_BASE_ADDR);
> +	void *muxbase = IOMEM(MX9_IOMUXC_BASE_ADDR);
> +	void *fdt;
> +
> +	/* uart iomux-setup */
> +	writel(0x0, muxbase + 0x0184); /* TX */
> +	writel(0x0, muxbase + 0x0180); /* RX */
> +
> +	imx9_uart_setup(IOMEM(base));
> +	pbl_set_putc(lpuart32_putc, base + 0x10);
> +
> +	if (current_el() == 3) {
> +
> +		/*
> +		 * Current u-boot master has two dram variants but neither
> +		 * where found to work here. As a workaround, lpddr4_timing.c
> +		 * is based on the initial single config version
> +		 */
> +
> +		imx93_ddr_init(&dram_timing, DRAM_TYPE_LPDDR4);
> +		imx93_load_and_start_image_via_tfa();
> +	}
> +
> +	fdt = __dtb_z_imx93_phyboard_segin_start;
> +
> +	imx93_barebox_entry(fdt);
> +
> +	__builtin_unreachable();
> +}
> +
> +ENTRY_FUNCTION(start_imx93_phyboard_segin, r0, r1, r2)
> +{
> +	if (current_el() == 3)
> +		imx93_cpu_lowlevel_init();
> +
> +	relocate_to_current_adr();
> +	setup_c();
> +
> +	phycore_imx93_continue();
> +}
> diff --git a/arch/arm/boards/phytec-phycore-imx93/lpddr4_timing.c b/arch/arm/boards/phytec-phycore-imx93/lpddr4_timing.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..6ff5dc158ee1135d8024223f7c672ecde6cfc6c1
> --- /dev/null
> +++ b/arch/arm/boards/phytec-phycore-imx93/lpddr4_timing.c
> @@ -0,0 +1,1546 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2023 NXP
> + * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> + * Christoph Stoidner <c.stoidner@phytec.de>
> + *
> + * Code generated with DDR Tool v1.0.0.
> + */
> +
> +#include <linux/kernel.h>
> +#include <soc/imx9/ddr.h>
> +
> +static struct dram_cfg_param ddr_ddrc_cfg[] = {
> +	/** Initialize DDRC registers **/
> +	{0x4e300110, 0x44100001},
> +	{0x4e300000, 0x8000bf},
> +	{0x4e300008, 0x0},
> +	{0x4e300080, 0x80000412},
> +	{0x4e300084, 0x0},
> +	{0x4e300114, 0x1002},
> +	{0x4e300260, 0x4080},
> +	{0x4e300f04, 0x80},
> +	{0x4e300800, 0x43b30002},
> +	{0x4e300804, 0x1f1f1f1f},
> +	{0x4e301000, 0x0},
> +	{0x4e301240, 0x0},
> +	{0x4e301244, 0x0},
> +	{0x4e301248, 0x0},
> +	{0x4e30124c, 0x0},
> +	{0x4e301250, 0x0},
> +	{0x4e301254, 0x0},
> +	{0x4e301258, 0x0},
> +	{0x4e30125c, 0x0},
> +
> +};
> +
> +/* dram fsp cfg */
> +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
> +	{
> +		{
> +			{0x4e300100, 0x24A0421B},
> +			{0x4e300104, 0xF8EE001B},
> +			{0x4e300108, 0x2F263233},
> +			{0x4e30010C, 0x0005E18B},
> +			{0x4e300124, 0x1C770000},
> +			{0x4e300160, 0x00009102},
> +			{0x4e30016C, 0x35F00000},
> +			{0x4e300170, 0x8B0B0608},
> +			{0x4e300250, 0x00000028},
> +			{0x4e300254, 0x00FE00FE},
> +			{0x4e300258, 0x00000008},
> +			{0x4e30025C, 0x00000400},
> +			{0x4e300300, 0x224F2215},
> +			{0x4e300304, 0x00FE2213},
> +			{0x4e300308, 0x0A3C0E3C},
> +		},
> +		{
> +			{0x01, 0xE4},
> +			{0x02, 0x36},
> +			{0x03, 0xF2},
> +			{0x0b, 0x46},
> +			{0x0c, 0x11},
> +			{0x0e, 0x11},
> +			{0x16, 0x04},
> +		},
> +		0,
> +	},
> +
> +};
> +
> +/* PHY Initialize Configuration */
> +static struct dram_cfg_param ddr_ddrphy_cfg[] = {
> +	{0x100a0, 0x0},
> +	{0x100a1, 0x1},
> +	{0x100a2, 0x2},
> +	{0x100a3, 0x3},
> +	{0x100a4, 0x4},
> +	{0x100a5, 0x5},
> +	{0x100a6, 0x6},
> +	{0x100a7, 0x7},
> +	{0x110a0, 0x0},
> +	{0x110a1, 0x1},
> +	{0x110a2, 0x2},
> +	{0x110a3, 0x3},
> +	{0x110a4, 0x4},
> +	{0x110a5, 0x5},
> +	{0x110a6, 0x6},
> +	{0x110a7, 0x7},
> +	{0x1005f, 0x5ff},
> +	{0x1015f, 0x5ff},
> +	{0x1105f, 0x5ff},
> +	{0x1115f, 0x5ff},
> +	{0x55, 0x1ff},
> +	{0x1055, 0x1ff},
> +	{0x2055, 0x1ff},
> +	{0x200c5, 0x19},
> +	{0x2002e, 0x2},
> +	{0x90204, 0x0},
> +	{0x20024, 0x1e3},
> +	{0x2003a, 0x2},
> +	{0x2007d, 0x212},
> +	{0x2007c, 0x61},
> +	{0x20056, 0x3},
> +	{0x1004d, 0x600},
> +	{0x1014d, 0x600},
> +	{0x1104d, 0x600},
> +	{0x1114d, 0x600},
> +	{0x10049, 0xe00},
> +	{0x10149, 0xe00},
> +	{0x11049, 0xe00},
> +	{0x11149, 0xe00},
> +	{0x43, 0x60},
> +	{0x1043, 0x60},
> +	{0x2043, 0x60},
> +	{0x20018, 0x1},
> +	{0x20075, 0x4},
> +	{0x20050, 0x0},
> +	{0x2009b, 0x2},
> +	{0x20008, 0x3a5},
> +	{0x20088, 0x9},
> +	{0x200b2, 0x10c},
> +	{0x10043, 0x5a1},
> +	{0x10143, 0x5a1},
> +	{0x11043, 0x5a1},
> +	{0x11143, 0x5a1},
> +	{0x200fa, 0x2},
> +	{0x20019, 0x1},
> +	{0x200f0, 0x600},
> +	{0x200f1, 0x0},
> +	{0x200f2, 0x4444},
> +	{0x200f3, 0x8888},
> +	{0x200f4, 0x5655},
> +	{0x200f5, 0x0},
> +	{0x200f6, 0x0},
> +	{0x200f7, 0xf000},
> +	{0x20025, 0x0},
> +	{0x2002d, 0x1},
> +	{0x2002c, 0x0},
> +	{0x20021, 0x0},
> +	{0x200c7, 0x21},
> +	{0x1200c7, 0x21},
> +	{0x200ca, 0x24},
> +	{0x1200ca, 0x24},
> +
> +};
> +
> +/* ddr phy trained csr */
> +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> +	{0x1005f, 0x0},
> +	{0x1015f, 0x0},
> +	{0x1105f, 0x0},
> +	{0x1115f, 0x0},
> +	{0x55, 0x0},
> +	{0x1055, 0x0},
> +	{0x2055, 0x0},
> +	{0x200c5, 0x0},
> +	{0x2002e, 0x0},
> +	{0x90204, 0x0},
> +	{0x20024, 0x0},
> +	{0x2003a, 0x0},
> +	{0x2007d, 0x0},
> +	{0x2007c, 0x0},
> +	{0x20056, 0x0},
> +	{0x1004d, 0x0},
> +	{0x1014d, 0x0},
> +	{0x1104d, 0x0},
> +	{0x1114d, 0x0},
> +	{0x10049, 0x0},
> +	{0x10149, 0x0},
> +	{0x11049, 0x0},
> +	{0x11149, 0x0},
> +	{0x43, 0x0},
> +	{0x1043, 0x0},
> +	{0x2043, 0x0},
> +	{0x20018, 0x0},
> +	{0x20075, 0x0},
> +	{0x20050, 0x0},
> +	{0x2009b, 0x0},
> +	{0x20008, 0x0},
> +	{0x20088, 0x0},
> +	{0x200b2, 0x0},
> +	{0x10043, 0x0},
> +	{0x10143, 0x0},
> +	{0x11043, 0x0},
> +	{0x11143, 0x0},
> +	{0x200fa, 0x0},
> +	{0x20019, 0x0},
> +	{0x200f0, 0x0},
> +	{0x200f1, 0x0},
> +	{0x200f2, 0x0},
> +	{0x200f3, 0x0},
> +	{0x200f4, 0x0},
> +	{0x200f5, 0x0},
> +	{0x200f6, 0x0},
> +	{0x200f7, 0x0},
> +	{0x20025, 0x0},
> +	{0x2002d, 0x0},
> +	{0x2002c, 0x0},
> +	{0xd0000, 0x0},
> +	{0x90000, 0x0},
> +	{0x90001, 0x0},
> +	{0x90002, 0x0},
> +	{0x90003, 0x0},
> +	{0x90004, 0x0},
> +	{0x90005, 0x0},
> +	{0x90029, 0x0},
> +	{0x9002a, 0x0},
> +	{0x9002b, 0x0},
> +	{0x9002c, 0x0},
> +	{0x9002d, 0x0},
> +	{0x9002e, 0x0},
> +	{0x9002f, 0x0},
> +	{0x90030, 0x0},
> +	{0x90031, 0x0},
> +	{0x90032, 0x0},
> +	{0x90033, 0x0},
> +	{0x90034, 0x0},
> +	{0x90035, 0x0},
> +	{0x90036, 0x0},
> +	{0x90037, 0x0},
> +	{0x90038, 0x0},
> +	{0x90039, 0x0},
> +	{0x9003a, 0x0},
> +	{0x9003b, 0x0},
> +	{0x9003c, 0x0},
> +	{0x9003d, 0x0},
> +	{0x9003e, 0x0},
> +	{0x9003f, 0x0},
> +	{0x90040, 0x0},
> +	{0x90041, 0x0},
> +	{0x90042, 0x0},
> +	{0x90043, 0x0},
> +	{0x90044, 0x0},
> +	{0x90045, 0x0},
> +	{0x90046, 0x0},
> +	{0x90047, 0x0},
> +	{0x90048, 0x0},
> +	{0x90049, 0x0},
> +	{0x9004a, 0x0},
> +	{0x9004b, 0x0},
> +	{0x9004c, 0x0},
> +	{0x9004d, 0x0},
> +	{0x9004e, 0x0},
> +	{0x9004f, 0x0},
> +	{0x90050, 0x0},
> +	{0x90051, 0x0},
> +	{0x90052, 0x0},
> +	{0x90053, 0x0},
> +	{0x90054, 0x0},
> +	{0x90055, 0x0},
> +	{0x90056, 0x0},
> +	{0x90057, 0x0},
> +	{0x90058, 0x0},
> +	{0x90059, 0x0},
> +	{0x9005a, 0x0},
> +	{0x9005b, 0x0},
> +	{0x9005c, 0x0},
> +	{0x9005d, 0x0},
> +	{0x9005e, 0x0},
> +	{0x9005f, 0x0},
> +	{0x90060, 0x0},
> +	{0x90061, 0x0},
> +	{0x90062, 0x0},
> +	{0x90063, 0x0},
> +	{0x90064, 0x0},
> +	{0x90065, 0x0},
> +	{0x90066, 0x0},
> +	{0x90067, 0x0},
> +	{0x90068, 0x0},
> +	{0x90069, 0x0},
> +	{0x9006a, 0x0},
> +	{0x9006b, 0x0},
> +	{0x9006c, 0x0},
> +	{0x9006d, 0x0},
> +	{0x9006e, 0x0},
> +	{0x9006f, 0x0},
> +	{0x90070, 0x0},
> +	{0x90071, 0x0},
> +	{0x90072, 0x0},
> +	{0x90073, 0x0},
> +	{0x90074, 0x0},
> +	{0x90075, 0x0},
> +	{0x90076, 0x0},
> +	{0x90077, 0x0},
> +	{0x90078, 0x0},
> +	{0x90079, 0x0},
> +	{0x9007a, 0x0},
> +	{0x9007b, 0x0},
> +	{0x9007c, 0x0},
> +	{0x9007d, 0x0},
> +	{0x9007e, 0x0},
> +	{0x9007f, 0x0},
> +	{0x90080, 0x0},
> +	{0x90081, 0x0},
> +	{0x90082, 0x0},
> +	{0x90083, 0x0},
> +	{0x90084, 0x0},
> +	{0x90085, 0x0},
> +	{0x90086, 0x0},
> +	{0x90087, 0x0},
> +	{0x90088, 0x0},
> +	{0x90089, 0x0},
> +	{0x9008a, 0x0},
> +	{0x9008b, 0x0},
> +	{0x9008c, 0x0},
> +	{0x9008d, 0x0},
> +	{0x9008e, 0x0},
> +	{0x9008f, 0x0},
> +	{0x90090, 0x0},
> +	{0x90091, 0x0},
> +	{0x90092, 0x0},
> +	{0x90093, 0x0},
> +	{0x90094, 0x0},
> +	{0x90095, 0x0},
> +	{0x90096, 0x0},
> +	{0x90097, 0x0},
> +	{0x90098, 0x0},
> +	{0x90099, 0x0},
> +	{0x9009a, 0x0},
> +	{0x9009b, 0x0},
> +	{0x9009c, 0x0},
> +	{0x9009d, 0x0},
> +	{0x9009e, 0x0},
> +	{0x9009f, 0x0},
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> +	{0x115c1, 0x0},
> +	{0x116c0, 0x0},
> +	{0x116c1, 0x0},
> +	{0x117c0, 0x0},
> +	{0x117c1, 0x0},
> +	{0x118c0, 0x0},
> +	{0x118c1, 0x0},
> +	{0x110ae, 0x0},
> +	{0x110af, 0x0},
> +	{0x90201, 0x0},
> +	{0x90202, 0x0},
> +	{0x90203, 0x0},
> +	{0x90205, 0x0},
> +	{0x90206, 0x0},
> +	{0x90207, 0x0},
> +	{0x90208, 0x0},
> +	{0x20020, 0x0},
> +	{0x20077, 0x0},
> +	{0x20072, 0x0},
> +	{0x20073, 0x0},
> +	{0x400c0, 0x0},
> +	{0x10040, 0x0},
> +	{0x10140, 0x0},
> +	{0x10240, 0x0},
> +	{0x10340, 0x0},
> +	{0x10440, 0x0},
> +	{0x10540, 0x0},
> +	{0x10640, 0x0},
> +	{0x10740, 0x0},
> +	{0x10840, 0x0},
> +	{0x11040, 0x0},
> +	{0x11140, 0x0},
> +	{0x11240, 0x0},
> +	{0x11340, 0x0},
> +	{0x11440, 0x0},
> +	{0x11540, 0x0},
> +	{0x11640, 0x0},
> +	{0x11740, 0x0},
> +	{0x11840, 0x0},
> +
> +};
> +
> +/* P0 message block parameter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_cfg[] = {
> +	{0xd0000, 0x0},
> +	{0x54003, 0xe94},
> +	{0x54004, 0x4},
> +	{0x54006, 0x15},
> +	{0x54008, 0x131f},
> +	{0x54009, 0xc8},
> +	{0x5400b, 0x4},
> +	{0x5400d, 0x100},
> +	{0x5400f, 0x100},
> +	{0x54012, 0x110},
> +	{0x54019, 0x36e4},
> +	{0x5401a, 0xf2},
> +	{0x5401b, 0x1146},
> +	{0x5401c, 0x1108},
> +	{0x5401e, 0x4},
> +	{0x5401f, 0x36e4},
> +	{0x54020, 0xf2},
> +	{0x54021, 0x1146},
> +	{0x54022, 0x1108},
> +	{0x54024, 0x4},
> +	{0x54032, 0xe400},
> +	{0x54033, 0xf236},
> +	{0x54034, 0x4600},
> +	{0x54035, 0x811},
> +	{0x54036, 0x11},
> +	{0x54037, 0x400},
> +	{0x54038, 0xe400},
> +	{0x54039, 0xf236},
> +	{0x5403a, 0x4600},
> +	{0x5403b, 0x811},
> +	{0x5403c, 0x11},
> +	{0x5403d, 0x400},
> +	{0xd0000, 0x1}
> +};
> +
> +/* P0 2D message block parameter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> +	{0xd0000, 0x0},
> +	{0x54003, 0xe94},
> +	{0x54004, 0x4},
> +	{0x54006, 0x15},
> +	{0x54008, 0x61},
> +	{0x54009, 0xc8},
> +	{0x5400b, 0x4},
> +	{0x5400d, 0x100},
> +	{0x5400f, 0x100},
> +	{0x54010, 0x2080},
> +	{0x54012, 0x110},
> +	{0x54019, 0x36e4},
> +	{0x5401a, 0xf2},
> +	{0x5401b, 0x1146},
> +	{0x5401c, 0x1108},
> +	{0x5401e, 0x4},
> +	{0x5401f, 0x36e4},
> +	{0x54020, 0xf2},
> +	{0x54021, 0x1146},
> +	{0x54022, 0x1108},
> +	{0x54024, 0x4},
> +	{0x54032, 0xe400},
> +	{0x54033, 0xf236},
> +	{0x54034, 0x4600},
> +	{0x54035, 0x811},
> +	{0x54036, 0x11},
> +	{0x54037, 0x400},
> +	{0x54038, 0xe400},
> +	{0x54039, 0xf236},
> +	{0x5403a, 0x4600},
> +	{0x5403b, 0x811},
> +	{0x5403c, 0x11},
> +	{0x5403d, 0x400},
> +	{0xd0000, 0x1}
> +};
> +
> +/* DRAM PHY init engine image */
> +static struct dram_cfg_param ddr_phy_pie[] = {
> +	{0xd0000, 0x0},
> +	{0x90000, 0x10},
> +	{0x90001, 0x400},
> +	{0x90002, 0x10e},
> +	{0x90003, 0x0},
> +	{0x90004, 0x0},
> +	{0x90005, 0x8},
> +	{0x90029, 0xb},
> +	{0x9002a, 0x480},
> +	{0x9002b, 0x109},
> +	{0x9002c, 0x8},
> +	{0x9002d, 0x448},
> +	{0x9002e, 0x139},
> +	{0x9002f, 0x8},
> +	{0x90030, 0x478},
> +	{0x90031, 0x109},
> +	{0x90032, 0x0},
> +	{0x90033, 0xe8},
> +	{0x90034, 0x109},
> +	{0x90035, 0x2},
> +	{0x90036, 0x10},
> +	{0x90037, 0x139},
> +	{0x90038, 0xb},
> +	{0x90039, 0x7c0},
> +	{0x9003a, 0x139},
> +	{0x9003b, 0x44},
> +	{0x9003c, 0x633},
> +	{0x9003d, 0x159},
> +	{0x9003e, 0x14f},
> +	{0x9003f, 0x630},
> +	{0x90040, 0x159},
> +	{0x90041, 0x47},
> +	{0x90042, 0x633},
> +	{0x90043, 0x149},
> +	{0x90044, 0x4f},
> +	{0x90045, 0x633},
> +	{0x90046, 0x179},
> +	{0x90047, 0x8},
> +	{0x90048, 0xe0},
> +	{0x90049, 0x109},
> +	{0x9004a, 0x0},
> +	{0x9004b, 0x7c8},
> +	{0x9004c, 0x109},
> +	{0x9004d, 0x0},
> +	{0x9004e, 0x1},
> +	{0x9004f, 0x8},
> +	{0x90050, 0x30},
> +	{0x90051, 0x65a},
> +	{0x90052, 0x9},
> +	{0x90053, 0x0},
> +	{0x90054, 0x45a},
> +	{0x90055, 0x9},
> +	{0x90056, 0x0},
> +	{0x90057, 0x448},
> +	{0x90058, 0x109},
> +	{0x90059, 0x40},
> +	{0x9005a, 0x633},
> +	{0x9005b, 0x179},
> +	{0x9005c, 0x1},
> +	{0x9005d, 0x618},
> +	{0x9005e, 0x109},
> +	{0x9005f, 0x40c0},
> +	{0x90060, 0x633},
> +	{0x90061, 0x149},
> +	{0x90062, 0x8},
> +	{0x90063, 0x4},
> +	{0x90064, 0x48},
> +	{0x90065, 0x4040},
> +	{0x90066, 0x633},
> +	{0x90067, 0x149},
> +	{0x90068, 0x0},
> +	{0x90069, 0x4},
> +	{0x9006a, 0x48},
> +	{0x9006b, 0x40},
> +	{0x9006c, 0x633},
> +	{0x9006d, 0x149},
> +	{0x9006e, 0x0},
> +	{0x9006f, 0x658},
> +	{0x90070, 0x109},
> +	{0x90071, 0x10},
> +	{0x90072, 0x4},
> +	{0x90073, 0x18},
> +	{0x90074, 0x0},
> +	{0x90075, 0x4},
> +	{0x90076, 0x78},
> +	{0x90077, 0x549},
> +	{0x90078, 0x633},
> +	{0x90079, 0x159},
> +	{0x9007a, 0xd49},
> +	{0x9007b, 0x633},
> +	{0x9007c, 0x159},
> +	{0x9007d, 0x94a},
> +	{0x9007e, 0x633},
> +	{0x9007f, 0x159},
> +	{0x90080, 0x441},
> +	{0x90081, 0x633},
> +	{0x90082, 0x149},
> +	{0x90083, 0x42},
> +	{0x90084, 0x633},
> +	{0x90085, 0x149},
> +	{0x90086, 0x1},
> +	{0x90087, 0x633},
> +	{0x90088, 0x149},
> +	{0x90089, 0x0},
> +	{0x9008a, 0xe0},
> +	{0x9008b, 0x109},
> +	{0x9008c, 0xa},
> +	{0x9008d, 0x10},
> +	{0x9008e, 0x109},
> +	{0x9008f, 0x9},
> +	{0x90090, 0x3c0},
> +	{0x90091, 0x149},
> +	{0x90092, 0x9},
> +	{0x90093, 0x3c0},
> +	{0x90094, 0x159},
> +	{0x90095, 0x18},
> +	{0x90096, 0x10},
> +	{0x90097, 0x109},
> +	{0x90098, 0x0},
> +	{0x90099, 0x3c0},
> +	{0x9009a, 0x109},
> +	{0x9009b, 0x18},
> +	{0x9009c, 0x4},
> +	{0x9009d, 0x48},
> +	{0x9009e, 0x18},
> +	{0x9009f, 0x4},
> +	{0x900a0, 0x58},
> +	{0x900a1, 0xb},
> +	{0x900a2, 0x10},
> +	{0x900a3, 0x109},
> +	{0x900a4, 0x1},
> +	{0x900a5, 0x10},
> +	{0x900a6, 0x109},
> +	{0x900a7, 0x5},
> +	{0x900a8, 0x7c0},
> +	{0x900a9, 0x109},
> +	{0x40000, 0x811},
> +	{0x40020, 0x880},
> +	{0x40040, 0x0},
> +	{0x40060, 0x0},
> +	{0x40001, 0x4008},
> +	{0x40021, 0x83},
> +	{0x40041, 0x4f},
> +	{0x40061, 0x0},
> +	{0x40002, 0x4040},
> +	{0x40022, 0x83},
> +	{0x40042, 0x51},
> +	{0x40062, 0x0},
> +	{0x40003, 0x811},
> +	{0x40023, 0x880},
> +	{0x40043, 0x0},
> +	{0x40063, 0x0},
> +	{0x40004, 0x720},
> +	{0x40024, 0xf},
> +	{0x40044, 0x1740},
> +	{0x40064, 0x0},
> +	{0x40005, 0x16},
> +	{0x40025, 0x83},
> +	{0x40045, 0x4b},
> +	{0x40065, 0x0},
> +	{0x40006, 0x716},
> +	{0x40026, 0xf},
> +	{0x40046, 0x2001},
> +	{0x40066, 0x0},
> +	{0x40007, 0x716},
> +	{0x40027, 0xf},
> +	{0x40047, 0x2800},
> +	{0x40067, 0x0},
> +	{0x40008, 0x716},
> +	{0x40028, 0xf},
> +	{0x40048, 0xf00},
> +	{0x40068, 0x0},
> +	{0x40009, 0x720},
> +	{0x40029, 0xf},
> +	{0x40049, 0x1400},
> +	{0x40069, 0x0},
> +	{0x4000a, 0xe08},
> +	{0x4002a, 0xc15},
> +	{0x4004a, 0x0},
> +	{0x4006a, 0x0},
> +	{0x4000b, 0x625},
> +	{0x4002b, 0x15},
> +	{0x4004b, 0x0},
> +	{0x4006b, 0x0},
> +	{0x4000c, 0x4028},
> +	{0x4002c, 0x80},
> +	{0x4004c, 0x0},
> +	{0x4006c, 0x0},
> +	{0x4000d, 0xe08},
> +	{0x4002d, 0xc1a},
> +	{0x4004d, 0x0},
> +	{0x4006d, 0x0},
> +	{0x4000e, 0x625},
> +	{0x4002e, 0x1a},
> +	{0x4004e, 0x0},
> +	{0x4006e, 0x0},
> +	{0x4000f, 0x4040},
> +	{0x4002f, 0x80},
> +	{0x4004f, 0x0},
> +	{0x4006f, 0x0},
> +	{0x40010, 0x2604},
> +	{0x40030, 0x15},
> +	{0x40050, 0x0},
> +	{0x40070, 0x0},
> +	{0x40011, 0x708},
> +	{0x40031, 0x5},
> +	{0x40051, 0x0},
> +	{0x40071, 0x2002},
> +	{0x40012, 0x8},
> +	{0x40032, 0x80},
> +	{0x40052, 0x0},
> +	{0x40072, 0x0},
> +	{0x40013, 0x2604},
> +	{0x40033, 0x1a},
> +	{0x40053, 0x0},
> +	{0x40073, 0x0},
> +	{0x40014, 0x708},
> +	{0x40034, 0xa},
> +	{0x40054, 0x0},
> +	{0x40074, 0x2002},
> +	{0x40015, 0x4040},
> +	{0x40035, 0x80},
> +	{0x40055, 0x0},
> +	{0x40075, 0x0},
> +	{0x40016, 0x60a},
> +	{0x40036, 0x15},
> +	{0x40056, 0x1200},
> +	{0x40076, 0x0},
> +	{0x40017, 0x61a},
> +	{0x40037, 0x15},
> +	{0x40057, 0x1300},
> +	{0x40077, 0x0},
> +	{0x40018, 0x60a},
> +	{0x40038, 0x1a},
> +	{0x40058, 0x1200},
> +	{0x40078, 0x0},
> +	{0x40019, 0x642},
> +	{0x40039, 0x1a},
> +	{0x40059, 0x1300},
> +	{0x40079, 0x0},
> +	{0x4001a, 0x4808},
> +	{0x4003a, 0x880},
> +	{0x4005a, 0x0},
> +	{0x4007a, 0x0},
> +	{0x900aa, 0x0},
> +	{0x900ab, 0x790},
> +	{0x900ac, 0x11a},
> +	{0x900ad, 0x8},
> +	{0x900ae, 0x7aa},
> +	{0x900af, 0x2a},
> +	{0x900b0, 0x10},
> +	{0x900b1, 0x7b2},
> +	{0x900b2, 0x2a},
> +	{0x900b3, 0x0},
> +	{0x900b4, 0x7c8},
> +	{0x900b5, 0x109},
> +	{0x900b6, 0x10},
> +	{0x900b7, 0x10},
> +	{0x900b8, 0x109},
> +	{0x900b9, 0x10},
> +	{0x900ba, 0x2a8},
> +	{0x900bb, 0x129},
> +	{0x900bc, 0x8},
> +	{0x900bd, 0x370},
> +	{0x900be, 0x129},
> +	{0x900bf, 0xa},
> +	{0x900c0, 0x3c8},
> +	{0x900c1, 0x1a9},
> +	{0x900c2, 0xc},
> +	{0x900c3, 0x408},
> +	{0x900c4, 0x199},
> +	{0x900c5, 0x14},
> +	{0x900c6, 0x790},
> +	{0x900c7, 0x11a},
> +	{0x900c8, 0x8},
> +	{0x900c9, 0x4},
> +	{0x900ca, 0x18},
> +	{0x900cb, 0xe},
> +	{0x900cc, 0x408},
> +	{0x900cd, 0x199},
> +	{0x900ce, 0x8},
> +	{0x900cf, 0x8568},
> +	{0x900d0, 0x108},
> +	{0x900d1, 0x18},
> +	{0x900d2, 0x790},
> +	{0x900d3, 0x16a},
> +	{0x900d4, 0x8},
> +	{0x900d5, 0x1d8},
> +	{0x900d6, 0x169},
> +	{0x900d7, 0x10},
> +	{0x900d8, 0x8558},
> +	{0x900d9, 0x168},
> +	{0x900da, 0x1ff8},
> +	{0x900db, 0x85a8},
> +	{0x900dc, 0x1e8},
> +	{0x900dd, 0x50},
> +	{0x900de, 0x798},
> +	{0x900df, 0x16a},
> +	{0x900e0, 0x60},
> +	{0x900e1, 0x7a0},
> +	{0x900e2, 0x16a},
> +	{0x900e3, 0x8},
> +	{0x900e4, 0x8310},
> +	{0x900e5, 0x168},
> +	{0x900e6, 0x8},
> +	{0x900e7, 0xa310},
> +	{0x900e8, 0x168},
> +	{0x900e9, 0xa},
> +	{0x900ea, 0x408},
> +	{0x900eb, 0x169},
> +	{0x900ec, 0x6e},
> +	{0x900ed, 0x0},
> +	{0x900ee, 0x68},
> +	{0x900ef, 0x0},
> +	{0x900f0, 0x408},
> +	{0x900f1, 0x169},
> +	{0x900f2, 0x0},
> +	{0x900f3, 0x8310},
> +	{0x900f4, 0x168},
> +	{0x900f5, 0x0},
> +	{0x900f6, 0xa310},
> +	{0x900f7, 0x168},
> +	{0x900f8, 0x1ff8},
> +	{0x900f9, 0x85a8},
> +	{0x900fa, 0x1e8},
> +	{0x900fb, 0x68},
> +	{0x900fc, 0x798},
> +	{0x900fd, 0x16a},
> +	{0x900fe, 0x78},
> +	{0x900ff, 0x7a0},
> +	{0x90100, 0x16a},
> +	{0x90101, 0x68},
> +	{0x90102, 0x790},
> +	{0x90103, 0x16a},
> +	{0x90104, 0x8},
> +	{0x90105, 0x8b10},
> +	{0x90106, 0x168},
> +	{0x90107, 0x8},
> +	{0x90108, 0xab10},
> +	{0x90109, 0x168},
> +	{0x9010a, 0xa},
> +	{0x9010b, 0x408},
> +	{0x9010c, 0x169},
> +	{0x9010d, 0x58},
> +	{0x9010e, 0x0},
> +	{0x9010f, 0x68},
> +	{0x90110, 0x0},
> +	{0x90111, 0x408},
> +	{0x90112, 0x169},
> +	{0x90113, 0x0},
> +	{0x90114, 0x8b10},
> +	{0x90115, 0x168},
> +	{0x90116, 0x1},
> +	{0x90117, 0xab10},
> +	{0x90118, 0x168},
> +	{0x90119, 0x0},
> +	{0x9011a, 0x1d8},
> +	{0x9011b, 0x169},
> +	{0x9011c, 0x80},
> +	{0x9011d, 0x790},
> +	{0x9011e, 0x16a},
> +	{0x9011f, 0x18},
> +	{0x90120, 0x7aa},
> +	{0x90121, 0x6a},
> +	{0x90122, 0xa},
> +	{0x90123, 0x0},
> +	{0x90124, 0x1e9},
> +	{0x90125, 0x8},
> +	{0x90126, 0x8080},
> +	{0x90127, 0x108},
> +	{0x90128, 0xf},
> +	{0x90129, 0x408},
> +	{0x9012a, 0x169},
> +	{0x9012b, 0xc},
> +	{0x9012c, 0x0},
> +	{0x9012d, 0x68},
> +	{0x9012e, 0x9},
> +	{0x9012f, 0x0},
> +	{0x90130, 0x1a9},
> +	{0x90131, 0x0},
> +	{0x90132, 0x408},
> +	{0x90133, 0x169},
> +	{0x90134, 0x0},
> +	{0x90135, 0x8080},
> +	{0x90136, 0x108},
> +	{0x90137, 0x8},
> +	{0x90138, 0x7aa},
> +	{0x90139, 0x6a},
> +	{0x9013a, 0x0},
> +	{0x9013b, 0x8568},
> +	{0x9013c, 0x108},
> +	{0x9013d, 0xb7},
> +	{0x9013e, 0x790},
> +	{0x9013f, 0x16a},
> +	{0x90140, 0x1f},
> +	{0x90141, 0x0},
> +	{0x90142, 0x68},
> +	{0x90143, 0x8},
> +	{0x90144, 0x8558},
> +	{0x90145, 0x168},
> +	{0x90146, 0xf},
> +	{0x90147, 0x408},
> +	{0x90148, 0x169},
> +	{0x90149, 0xd},
> +	{0x9014a, 0x0},
> +	{0x9014b, 0x68},
> +	{0x9014c, 0x0},
> +	{0x9014d, 0x408},
> +	{0x9014e, 0x169},
> +	{0x9014f, 0x0},
> +	{0x90150, 0x8558},
> +	{0x90151, 0x168},
> +	{0x90152, 0x8},
> +	{0x90153, 0x3c8},
> +	{0x90154, 0x1a9},
> +	{0x90155, 0x3},
> +	{0x90156, 0x370},
> +	{0x90157, 0x129},
> +	{0x90158, 0x20},
> +	{0x90159, 0x2aa},
> +	{0x9015a, 0x9},
> +	{0x9015b, 0x8},
> +	{0x9015c, 0xe8},
> +	{0x9015d, 0x109},
> +	{0x9015e, 0x0},
> +	{0x9015f, 0x8140},
> +	{0x90160, 0x10c},
> +	{0x90161, 0x10},
> +	{0x90162, 0x8138},
> +	{0x90163, 0x104},
> +	{0x90164, 0x8},
> +	{0x90165, 0x448},
> +	{0x90166, 0x109},
> +	{0x90167, 0xf},
> +	{0x90168, 0x7c0},
> +	{0x90169, 0x109},
> +	{0x9016a, 0x0},
> +	{0x9016b, 0xe8},
> +	{0x9016c, 0x109},
> +	{0x9016d, 0x47},
> +	{0x9016e, 0x630},
> +	{0x9016f, 0x109},
> +	{0x90170, 0x8},
> +	{0x90171, 0x618},
> +	{0x90172, 0x109},
> +	{0x90173, 0x8},
> +	{0x90174, 0xe0},
> +	{0x90175, 0x109},
> +	{0x90176, 0x0},
> +	{0x90177, 0x7c8},
> +	{0x90178, 0x109},
> +	{0x90179, 0x8},
> +	{0x9017a, 0x8140},
> +	{0x9017b, 0x10c},
> +	{0x9017c, 0x0},
> +	{0x9017d, 0x478},
> +	{0x9017e, 0x109},
> +	{0x9017f, 0x0},
> +	{0x90180, 0x1},
> +	{0x90181, 0x8},
> +	{0x90182, 0x8},
> +	{0x90183, 0x4},
> +	{0x90184, 0x0},
> +	{0x90006, 0x8},
> +	{0x90007, 0x7c8},
> +	{0x90008, 0x109},
> +	{0x90009, 0x0},
> +	{0x9000a, 0x400},
> +	{0x9000b, 0x106},
> +	{0xd00e7, 0x400},
> +	{0x90017, 0x0},
> +	{0x9001f, 0x2b},
> +	{0x90026, 0x69},
> +	{0x400d0, 0x0},
> +	{0x400d1, 0x101},
> +	{0x400d2, 0x105},
> +	{0x400d3, 0x107},
> +	{0x400d4, 0x10f},
> +	{0x400d5, 0x202},
> +	{0x400d6, 0x20a},
> +	{0x400d7, 0x20b},
> +	{0x2003a, 0x2},
> +	{0x200be, 0x3},
> +	{0x2000b, 0x75},
> +	{0x2000c, 0xe9},
> +	{0x2000d, 0x91c},
> +	{0x2000e, 0x2c},
> +	{0x9000c, 0x0},
> +	{0x9000d, 0x173},
> +	{0x9000e, 0x60},
> +	{0x9000f, 0x6110},
> +	{0x90010, 0x2152},
> +	{0x90011, 0xdfbd},
> +	{0x90012, 0x2060},
> +	{0x90013, 0x6152},
> +	{0x20010, 0x5a},
> +	{0x20011, 0x3},
> +	{0x40080, 0xe0},
> +	{0x40081, 0x12},
> +	{0x40082, 0xe0},
> +	{0x40083, 0x12},
> +	{0x40084, 0xe0},
> +	{0x40085, 0x12},
> +	{0x400fd, 0xf},
> +	{0x400f1, 0xe},
> +	{0x10011, 0x1},
> +	{0x10012, 0x1},
> +	{0x10013, 0x180},
> +	{0x10018, 0x1},
> +	{0x10002, 0x6209},
> +	{0x100b2, 0x1},
> +	{0x101b4, 0x1},
> +	{0x102b4, 0x1},
> +	{0x103b4, 0x1},
> +	{0x104b4, 0x1},
> +	{0x105b4, 0x1},
> +	{0x106b4, 0x1},
> +	{0x107b4, 0x1},
> +	{0x108b4, 0x1},
> +	{0x11011, 0x1},
> +	{0x11012, 0x1},
> +	{0x11013, 0x180},
> +	{0x11018, 0x1},
> +	{0x11002, 0x6209},
> +	{0x110b2, 0x1},
> +	{0x111b4, 0x1},
> +	{0x112b4, 0x1},
> +	{0x113b4, 0x1},
> +	{0x114b4, 0x1},
> +	{0x115b4, 0x1},
> +	{0x116b4, 0x1},
> +	{0x117b4, 0x1},
> +	{0x118b4, 0x1},
> +	{0x20089, 0x1},
> +	{0x20088, 0x19},
> +	{0xc0080, 0x0},
> +	{0xd0000, 0x1},
> +
> +};
> +
> +static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> +	{
> +		/* P0 3733mts 1D */
> +		.drate = 3733,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> +
> +	},
> +
> +	{
> +		/* P0 3733mts 2D */
> +		.drate = 3733,
> +		.fw_type = FW_2D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_2d_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> +	},
> +
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info dram_timing = {
> +	.ddrc_cfg = ddr_ddrc_cfg,
> +	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> +	.ddrphy_cfg = ddr_ddrphy_cfg,
> +	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> +	.fsp_msg = ddr_dram_fsp_msg,
> +	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> +	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> +	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> +	.ddrphy_pie = ddr_phy_pie,
> +	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> +	.fsp_table = { 3733, },
> +	.fsp_cfg = ddr_dram_fsp_cfg,
> +	.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
> +};
> diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
> index e58a2ca13d7a7f4767b680cceefed27fb6950f9b..445f20a303cc7f31f574125d38b34b9bdffd74da 100644
> --- a/arch/arm/configs/imx_v8_defconfig
> +++ b/arch/arm/configs/imx_v8_defconfig
> @@ -16,6 +16,7 @@ CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
>   CONFIG_MACH_ZII_IMX8MQ_DEV=y
>   CONFIG_64BIT=y
>   CONFIG_MACH_TQMA93XX=y
> +CONFIG_MACH_PHYTEC_PHYCORE_IMX93=y
>   CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
>   CONFIG_MMU=y
>   CONFIG_MALLOC_SIZE=0x0
> diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
> index b1e66e85f4607752efd79bdda6648b750bf872a1..c66b8a0be803a1f3c243e7ec3da5169e3d5451a1 100644
> --- a/arch/arm/configs/multi_v8_defconfig
> +++ b/arch/arm/configs/multi_v8_defconfig
> @@ -22,6 +22,7 @@ CONFIG_MACH_TQ_MBA8MPXL=y
>   CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
>   CONFIG_MACH_ZII_IMX8MQ_DEV=y
>   CONFIG_MACH_TQMA93XX=y
> +CONFIG_MACH_PHYTEC_PHYCORE_IMX93=y
>   CONFIG_IMX_IIM=y
>   CONFIG_ARCH_LAYERSCAPE_PPA=y
>   CONFIG_MACH_LS1028ARDB=y
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index d3462858523067d68cd41112daaa81d72a072957..3423115b4b447a14d9755ecd63c05a36328c158a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -81,6 +81,7 @@ lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
>   				imx6ull-phytec-phycore-som-nand.dtb.o \
>   				imx6ull-phytec-phycore-som-emmc.dtb.o
>   lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
> +lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX93) += imx93-phyboard-segin.dtb.o
>   lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += stm32mp157c-phycore-stm32mp1-3.dtb.o
>   lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM) += imx8mm-phyboard-polis-rdk.dtb.o
>   lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
> diff --git a/arch/arm/dts/imx93-phyboard-segin-downstream.dtsi b/arch/arm/dts/imx93-phyboard-segin-downstream.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..d2a81069e335c12933cdf48bbc1b7c13e937a6c3
> --- /dev/null
> +++ b/arch/arm/dts/imx93-phyboard-segin-downstream.dtsi
> @@ -0,0 +1,269 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> + * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
> + */
> +
> +/*
> + * Contents of this file are copied from the linux-phytec-imx downstream and
> + * can be removed once mainlined.
> + */
> +
> +/ {
> +	reg_vcc_1v8_audio: regulator-vcc1v8-audio {
> +		compatible = "regulator-fixed";
> +		regulator-max-microvolt = <1800000>;
> +		regulator-min-microvolt = <1800000>;
> +		regulator-name = "VCC1V8_AUDIO";
> +	};
> +	reg_vcc_3v3: regulator-vcc-3v3 {
> +		compatible = "regulator-fixed";
> +		regulator-max-microvolt = <3300000>;
> +		regulator-min-microvolt = <3300000>;
> +		regulator-name = "VCC3V3";
> +	};
> +};
> +
> +&reg_usdhc2_vmmc {
> +	compatible = "regulator-fixed";
> +	gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> +	enable-active-high;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-min-microvolt = <3300000>;
> +	regulator-name = "VCC_SD";
> +};
> +
> +/* I2C3 */
> +&lpi2c3 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpi2c3>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	pmic@25 {
> +		compatible = "nxp,pca9451a";
> +		reg = <0x25>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pmic>;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
> +
> +		regulators {
> +			buck1: BUCK1 {
> +				regulator-name = "VDD_SOC";
> +				regulator-min-microvolt = <610000>;
> +				regulator-max-microvolt = <950000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			buck2: BUCK2 {
> +				regulator-name = "VDDQ_0V6";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <600000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck4: BUCK4 {
> +				regulator-name = "VDD_3V3_BUCK";
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck5: BUCK5 {
> +				regulator-name = "VDD_1V8";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck6: BUCK6 {
> +				regulator-name = "VDD_1V1";
> +				regulator-min-microvolt = <1100000>;
> +				regulator-max-microvolt = <1100000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo1: LDO1 {
> +				regulator-name = "PMIC_SNVS_1V8";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo4: LDO4 {
> +				regulator-name = "VDD_0V8";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo5: LDO5 {
> +				regulator-name = "NVCC_SD2";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +
> +	eeprom@50 {
> +		compatible = "atmel,24c32";
> +		reg = <0x50>;
> +		pagesize = <32>;
> +		vcc-supply = <&buck4>;
> +	};
> +
> +	eepromid@58 {
> +		compatible = "atmel,24c32";
> +		pagesize = <32>;
> +		reg = <0x58>;
> +		size = <32>;
> +		vcc-supply = <&buck4>;
> +	};
> +};
> +
> +/* Ethernet */
> +&eqos {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_eqos>;
> +	phy-mode = "rmii";
> +	phy-handle = <&ethphy2>;
> +	assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
> +			  <&clk IMX93_CLK_ENET>;
> +	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> +				 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> +	assigned-clock-rates = <100000000>, <50000000>;
> +	status = "okay";
> +};
> +
> +/* ENET2 MDIO */
> +&mdio {
> +	ethphy2: ethernet-phy@2 {
> +		reg = <2>;
> +		micrel,led-mode = <1>;
> +		compatible = "ethernet-phy-id0022.1561";
> +
> +		/*
> +		 * HACK:
> +		 * IMX93_CLK_ENET is the ref clock and should be running at 50Mhz.
> +		 * Using it here to tell the PHY we are running at 50MHz is not working.
> +		 * Let us simply use another clock here.
> +		 */
> +		/* clocks = <&clk IMX93_CLK_ENET>; */
> +		clocks = <&clk IMX93_CLK_ENET_REF_PHY>;
> +		clock-names = "rmii-ref";
> +	};
> +};
> +
> +/* USB  */
> +&usbotg1 {
> +	disable-over-current;
> +	dr_mode = "otg";
> +	status = "okay";
> +};
> +
> +&usbotg2 {
> +	disable-over-current;
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
> +/* SD-Card */
> +&usdhc2 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
> +	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
> +	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
> +	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
> +	vmmc-supply = <&reg_usdhc2_vmmc>;
> +	bus-width = <4>;
> +	disable-wp;
> +	no-sdio;
> +	no-mmc;
> +	status = "okay";
> +};
> +
> +/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +&pinctrl_usdhc2_default {
> +	fsl,pins = <
> +		MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e
> +		MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000139e
> +		MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e
> +		MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e
> +		MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e
> +		MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000139e
> +		MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
> +	>;
> +};
> +
> +/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +&pinctrl_usdhc2_100mhz {
> +	fsl,pins = <
> +		MX93_PAD_SD2_CLK__USDHC2_CLK            0x159e
> +		MX93_PAD_SD2_CMD__USDHC2_CMD            0x4000139e
> +		MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x4000138e
> +		MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x4000138e
> +		MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x4000139e
> +		MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x4000139e
> +		MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
> +	>;
> +};
> +
> +/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +&pinctrl_usdhc2_200mhz {
> +	fsl,pins = <
> +		MX93_PAD_SD2_CLK__USDHC2_CLK            0x158e
> +		MX93_PAD_SD2_CMD__USDHC2_CMD            0x4000139e
> +		MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x4000139e
> +		MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x4000139e
> +		MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x4000139e
> +		MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x4000139e
> +		MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
> +	>;
> +};
> +
> +
> +&iomuxc {
> +	pinctrl_eqos: eqosgrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000050e
> +			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
> +			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
> +			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x50e
> +			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x50e
> +			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
> +			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x50e
> +			MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER			0x57e
> +		>;
> +	};
> +	pinctrl_lpi2c3: lpi2c3grp {
> +		fsl,pins = <
> +			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e
> +			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e
> +		>;
> +	};
> +	pinctrl_pmic: pmicgrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET2_RD3__GPIO4_IO27			0x31e
> +		>;
> +	};
> +	pinctrl_rtc: rtcgrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET2_RD2__GPIO4_IO26		0x31e
> +		>;
> +	};
> +};
> diff --git a/arch/arm/dts/imx93-phyboard-segin.dts b/arch/arm/dts/imx93-phyboard-segin.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..0fc69b8789661eaa3c904efbe3e439170a83adb6
> --- /dev/null
> +++ b/arch/arm/dts/imx93-phyboard-segin.dts
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +
> +#include <arm64/freescale/imx93-phyboard-segin.dts>
> +#include "imx93.dtsi"
> +#include "imx93-phyboard-segin-downstream.dtsi"
> +
> +/ {
> +	chosen {
> +		environment-emmc {
> +			compatible = "barebox,environment";
> +			device-path = &environment_emmc;
> +		};
> +	};
> +};
> +
> +&usdhc1 {
> +	partitions {
> +		compatible = "fixed-partitions";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		environment_emmc: partition@80000 {
> +			label = "barebox-environment";
> +			reg = <0x0 0x80000 0x0 0x80000>;
> +		};
> +	};
> +
> +};
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 5ae7ab12ee94f4fab3fe446904ea785c5cd51193..552e7227a0221fee8232dfba5dcdd60de923ff0c 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -746,6 +746,15 @@ config MACH_ZII_IMX8MQ_DEV
>   
>   comment "i.MX93 boards"
>   
> +config MACH_PHYTEC_PHYCORE_IMX93
> +	bool "phyCORE i.MX93 SoM based devices"
> +	select ARCH_IMX93
> +	select IMX9_DRAM
> +	select I2C
> +	select I2C_IMX_LPI2C
> +	select FIRMWARE_IMX93_ATF
> +	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
> +
>   config MACH_TQMA93XX
>   	bool "TQ i.MX93 on TQMA93XX Board"
>   	select ARCH_IMX93
> diff --git a/images/Makefile.imx b/images/Makefile.imx
> index c3f1bd5f05a008321944cf68659c146f8cd25ce1..93264254e9e4cda3969bf7bf4812f2d1c5b59c09 100644
> --- a/images/Makefile.imx
> +++ b/images/Makefile.imx
> @@ -521,3 +521,7 @@ $(obj)/%.imx9img: $(obj)/% FORCE
>   pblb-$(CONFIG_MACH_TQMA93XX) += start_imx93_tqma93xx
>   FILE_barebox-tqma93xx.img = start_imx93_tqma93xx.pblb.imx9img
>   image-$(CONFIG_MACH_TQMA93XX) += barebox-tqma93xx.img
> +
> +pblb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX93) += start_imx93_phyboard_segin
> +FILE_barebox-phyboard_segin.img = start_imx93_phyboard_segin.pblb.imx9img
> +image-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX93) += barebox-phyboard_segin.img
> 
> ---
> base-commit: 75296e2aa356f6fbd680aa2204545732ac49e37d
> change-id: 20250304-phyboard-segin-imx93-257c1809d4f8
> 
> Best regards,


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