[PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[Florian Bäuerle]

Signed-off-by: Florian Bäuerle <florian.baeuerle@allegion.com>
---
 arch/arm/boards/phytec-phycard-imx27/lowlevel.c | 15 +++++++++++++++
 arch/arm/mach-imx/include/mach/debug_ll.h       | 13 +++++++++++++
 include/serial/imx-uart.h                       |  5 +++++
 3 files changed, 33 insertions(+)

diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
index e1132e0..8244337 100644
--- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
@@ -14,6 +14,8 @@
 #include <mach/imx-pll.h>
 #include <mach/esdctl.h>
 #include <mach/imx-nand.h>
+#include <mach/debug_ll.h>
+#include <serial/imx-uart.h>
 
 #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
 
@@ -58,6 +60,18 @@ static void sdram_init(void)
 			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
 }
 
+static void setup_uart(void)
+{
+	/* Set PE[12-15] use, direction, function and pull-up */
+	writel(0xfffc0f27, MX27_GPIO5_BASE_ADDR + 0x20);
+	writel(0x00005000, MX27_GPIO5_BASE_ADDR);
+	writel(0x00000000, MX27_GPIO5_BASE_ADDR + 0x38);
+	writel(0xffff0fff, MX27_GPIO5_BASE_ADDR + 0x40);
+
+	imx27_ungate_all_peripherals();
+	imx27_uart_setup_ll();
+}
+
 void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
 {
 	unsigned long r;
@@ -97,6 +111,7 @@ void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
 		MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
 
 	sdram_init();
+	setup_uart();
 
 	imx27_barebox_boot_nand_external(fdt);
 }
diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index 1550e05..6c9b21d 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -56,6 +56,12 @@
 #error "unknown i.MX debug uart soc type"
 #endif
 
+static inline void imx27_uart_setup_ll(void)  {
+	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
+				CONFIG_DEBUG_IMX_UART_PORT));
+	imx27_uart_setup(base);
+}
+
 static inline void imx50_uart_setup_ll(void)
 {
 	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
@@ -121,6 +127,7 @@ static inline void PUTC_LL(int c)
 
 #else
 
+static inline void imx27_uart_setup_ll(void) {}
 static inline void imx50_uart_setup_ll(void) {}
 static inline void imx51_uart_setup_ll(void) {}
 static inline void imx53_uart_setup_ll(void) {}
@@ -138,6 +145,12 @@ static inline void imx_ungate_all_peripherals(void __iomem *ccmbase)
 		writel(0xffffffff, ccmbase + i);
 }
 
+static inline void imx27_ungate_all_peripherals(void)
+{
+	writel(0xfffffbff, IOMEM(MX27_CCM_BASE_ADDR) + 0x20);
+	writel(0xfffffffc, IOMEM(MX27_CCM_BASE_ADDR) + 0x24);
+}
+
 static inline void imx6_ungate_all_peripherals(void)
 {
 	imx_ungate_all_peripherals(IOMEM(MX6_CCM_BASE_ADDR));
diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
index c236065..0c033c2 100644
--- a/include/serial/imx-uart.h
+++ b/include/serial/imx-uart.h
@@ -155,6 +155,11 @@ static inline void imx_uart_set_dte(void __iomem *uartbase)
 	writel(ufcr, uartbase + UFCR);
 }
 
+static inline void imx27_uart_setup(void __iomem *uartbase)
+{
+	imx_uart_setup(uartbase, 66500000);
+}
+
 static inline void imx50_uart_setup(void __iomem *uartbase)
 {
 	imx_uart_setup(uartbase, 66666666);
-- 
1.8.3.1


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[Baeuerle, Florian]

Some background on that patch:

I've tried to get barebox master compiled with OSELAS 2018 running on a
phycard-imx27. I had a few problems with that:

It turned out, that I can boot the resulting image as a seconds stage (from an
older version of barebox), after commenting out pca100_usb_init(). I suppose
that is not a real problem, but probably related to some clock setup that
barebox master does somewhere during early boot (which I suppose, is skipped
when booting it as 2nd stage).

However, when flashing the resulting image to NAND, there seems to be a bigger
issue somewhere during early boot. This problem does not exist when compiling
barebox master with OSELAS 2016.

The result is that I do not see anything on the console. The imx27 also does not
seem to enter bootstrap mode though.

Further I found out that with CONSOLE_PBL, barebox also has issues somewhere
during early boot. It breaks either after calling pbl_set_putc(), or even
without calling pbl_set_putc(), when I increase the compile and default
loglevel.

So I tested the patch with the OSELAS 2016-Toolchain, without CONSOLE_PBL and it
worked. No success so far with the OSELAS 2018-Toolchain (to be clear: the patch
does not break barebox in that case, barebox is broken without the patch as well).

Am Donnerstag, den 23.08.2018, 11:58 +0200 schrieb Florian Bäuerle:
> Signed-off-by: Florian Bäuerle <florian.baeuerle@allegion.com>
> ---
>  arch/arm/boards/phytec-phycard-imx27/lowlevel.c | 15 +++++++++++++++
>  arch/arm/mach-imx/include/mach/debug_ll.h       | 13 +++++++++++++
>  include/serial/imx-uart.h                       |  5 +++++
>  3 files changed, 33 insertions(+)
> 
> diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> index e1132e0..8244337 100644
> --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> @@ -14,6 +14,8 @@
>  #include <mach/imx-pll.h>
>  #include <mach/esdctl.h>
>  #include <mach/imx-nand.h>
> +#include <mach/debug_ll.h>
> +#include <serial/imx-uart.h>
>  
>  #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
>  
> @@ -58,6 +60,18 @@ static void sdram_init(void)
>  			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
>  }
>  
> +static void setup_uart(void)
> +{
> +	/* Set PE[12-15] use, direction, function and pull-up */
> +	writel(0xfffc0f27, MX27_GPIO5_BASE_ADDR + 0x20);
> +	writel(0x00005000, MX27_GPIO5_BASE_ADDR);
> +	writel(0x00000000, MX27_GPIO5_BASE_ADDR + 0x38);
> +	writel(0xffff0fff, MX27_GPIO5_BASE_ADDR + 0x40);
> +
> +	imx27_ungate_all_peripherals();
> +	imx27_uart_setup_ll();
> +}
> +
>  void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
>  {
>  	unsigned long r;
> @@ -97,6 +111,7 @@ void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
>  		MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
>  
>  	sdram_init();
> +	setup_uart();
>  
>  	imx27_barebox_boot_nand_external(fdt);
>  }
> diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
> index 1550e05..6c9b21d 100644
> --- a/arch/arm/mach-imx/include/mach/debug_ll.h
> +++ b/arch/arm/mach-imx/include/mach/debug_ll.h
> @@ -56,6 +56,12 @@
>  #error "unknown i.MX debug uart soc type"
>  #endif
>  
> +static inline void imx27_uart_setup_ll(void)  {
> +	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
> +				CONFIG_DEBUG_IMX_UART_PORT));
> +	imx27_uart_setup(base);
> +}
> +
>  static inline void imx50_uart_setup_ll(void)
>  {
>  	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
> @@ -121,6 +127,7 @@ static inline void PUTC_LL(int c)
>  
>  #else
>  
> +static inline void imx27_uart_setup_ll(void) {}
>  static inline void imx50_uart_setup_ll(void) {}
>  static inline void imx51_uart_setup_ll(void) {}
>  static inline void imx53_uart_setup_ll(void) {}
> @@ -138,6 +145,12 @@ static inline void imx_ungate_all_peripherals(void __iomem *ccmbase)
>  		writel(0xffffffff, ccmbase + i);
>  }
>  
> +static inline void imx27_ungate_all_peripherals(void)
> +{
> +	writel(0xfffffbff, IOMEM(MX27_CCM_BASE_ADDR) + 0x20);
> +	writel(0xfffffffc, IOMEM(MX27_CCM_BASE_ADDR) + 0x24);
> +}
> +
>  static inline void imx6_ungate_all_peripherals(void)
>  {
>  	imx_ungate_all_peripherals(IOMEM(MX6_CCM_BASE_ADDR));
> diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
> index c236065..0c033c2 100644
> --- a/include/serial/imx-uart.h
> +++ b/include/serial/imx-uart.h
> @@ -155,6 +155,11 @@ static inline void imx_uart_set_dte(void __iomem *uartbase)
>  	writel(ufcr, uartbase + UFCR);
>  }
>  
> +static inline void imx27_uart_setup(void __iomem *uartbase)
> +{
> +	imx_uart_setup(uartbase, 66500000);
> +}
> +
>  static inline void imx50_uart_setup(void __iomem *uartbase)
>  {
>  	imx_uart_setup(uartbase, 66666666);
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[Andrey Smirnov]

On Thu, Aug 23, 2018 at 2:59 AM Florian Bäuerle
<florian.baeuerle@allegion.com> wrote:
>
> Signed-off-by: Florian Bäuerle <florian.baeuerle@allegion.com>
> ---
>  arch/arm/boards/phytec-phycard-imx27/lowlevel.c | 15 +++++++++++++++
>  arch/arm/mach-imx/include/mach/debug_ll.h       | 13 +++++++++++++
>  include/serial/imx-uart.h                       |  5 +++++
>  3 files changed, 33 insertions(+)
>
> diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> index e1132e0..8244337 100644
> --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> @@ -14,6 +14,8 @@
>  #include <mach/imx-pll.h>
>  #include <mach/esdctl.h>
>  #include <mach/imx-nand.h>
> +#include <mach/debug_ll.h>
> +#include <serial/imx-uart.h>
>
>  #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
>
> @@ -58,6 +60,18 @@ static void sdram_init(void)
>                         MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
>  }
>
> +static void setup_uart(void)
> +{
> +       /* Set PE[12-15] use, direction, function and pull-up */
> +       writel(0xfffc0f27, MX27_GPIO5_BASE_ADDR + 0x20);
> +       writel(0x00005000, MX27_GPIO5_BASE_ADDR);
> +       writel(0x00000000, MX27_GPIO5_BASE_ADDR + 0x38);
> +       writel(0xffff0fff, MX27_GPIO5_BASE_ADDR + 0x40);
> +

Can constants from iomux-imx27.h be used here?

> +       imx27_ungate_all_peripherals();
> +       imx27_uart_setup_ll();
> +}
> +
>  void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
>  {
>         unsigned long r;
> @@ -97,6 +111,7 @@ void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
>                 MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
>
>         sdram_init();
> +       setup_uart();

Majority of the boards gates this to happen on if
IS_ENABLED(CONFIG_DEBUG_LL) is true, so it might make sense to do the
same.

>
>         imx27_barebox_boot_nand_external(fdt);
>  }
> diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
> index 1550e05..6c9b21d 100644
> --- a/arch/arm/mach-imx/include/mach/debug_ll.h
> +++ b/arch/arm/mach-imx/include/mach/debug_ll.h
> @@ -56,6 +56,12 @@
>  #error "unknown i.MX debug uart soc type"
>  #endif
>
> +static inline void imx27_uart_setup_ll(void)  {
> +       void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
> +                               CONFIG_DEBUG_IMX_UART_PORT));
> +       imx27_uart_setup(base);
> +}
> +
>  static inline void imx50_uart_setup_ll(void)
>  {
>         void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
> @@ -121,6 +127,7 @@ static inline void PUTC_LL(int c)
>
>  #else
>
> +static inline void imx27_uart_setup_ll(void) {}
>  static inline void imx50_uart_setup_ll(void) {}
>  static inline void imx51_uart_setup_ll(void) {}
>  static inline void imx53_uart_setup_ll(void) {}
> @@ -138,6 +145,12 @@ static inline void imx_ungate_all_peripherals(void __iomem *ccmbase)
>                 writel(0xffffffff, ccmbase + i);
>  }
>
> +static inline void imx27_ungate_all_peripherals(void)
> +{
> +       writel(0xfffffbff, IOMEM(MX27_CCM_BASE_ADDR) + 0x20);
> +       writel(0xfffffffc, IOMEM(MX27_CCM_BASE_ADDR) + 0x24);
> +}

I think you can use  MX27_PCCR0 and  MX27_PCCR1 here instead of magic numbers.

> +
>  static inline void imx6_ungate_all_peripherals(void)
>  {
>         imx_ungate_all_peripherals(IOMEM(MX6_CCM_BASE_ADDR));
> diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
> index c236065..0c033c2 100644
> --- a/include/serial/imx-uart.h
> +++ b/include/serial/imx-uart.h
> @@ -155,6 +155,11 @@ static inline void imx_uart_set_dte(void __iomem *uartbase)
>         writel(ufcr, uartbase + UFCR);
>  }
>
> +static inline void imx27_uart_setup(void __iomem *uartbase)
> +{
> +       imx_uart_setup(uartbase, 66500000);
> +}
> +
>  static inline void imx50_uart_setup(void __iomem *uartbase)
>  {
>         imx_uart_setup(uartbase, 66666666);
> --
> 1.8.3.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[Sascha Hauer]

On Thu, Aug 23, 2018 at 12:20:32PM +0000, Baeuerle, Florian wrote:
> Some background on that patch:
> 
> I've tried to get barebox master compiled with OSELAS 2018 running on a
> phycard-imx27. I had a few problems with that:
> 
> It turned out, that I can boot the resulting image as a seconds stage (from an
> older version of barebox), after commenting out pca100_usb_init(). I suppose
> that is not a real problem, but probably related to some clock setup that
> barebox master does somewhere during early boot (which I suppose, is skipped
> when booting it as 2nd stage).
> 
> However, when flashing the resulting image to NAND, there seems to be a bigger
> issue somewhere during early boot. This problem does not exist when compiling
> barebox master with OSELAS 2016.
> 
> The result is that I do not see anything on the console. The imx27 also does not
> seem to enter bootstrap mode though.
> 
> Further I found out that with CONSOLE_PBL, barebox also has issues somewhere
> during early boot. It breaks either after calling pbl_set_putc(), or even
> without calling pbl_set_putc(), when I increase the compile and default
> loglevel.

You probably can't use CONSOLE_PBL on the pca100. The i.MX27 NAND boot
requires the initial image portion to fit into 2KiB. These 2KiB are
already almost full with the required code, no place to add console
support there. You could probably through in some putc_ll() into the
initial code (after you've configured the UART with your patch).

The 2KiB constraint makes the boot process rather tricky. I have a
PCA100 at work, I'll give it a try and reproduce the issue next week
when I'm back in the office.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[Sascha Hauer]

On Thu, Aug 23, 2018 at 12:20:32PM +0000, Baeuerle, Florian wrote:
> Some background on that patch:
> 
> I've tried to get barebox master compiled with OSELAS 2018 running on a
> phycard-imx27. I had a few problems with that:
> 
> It turned out, that I can boot the resulting image as a seconds stage (from an
> older version of barebox), after commenting out pca100_usb_init(). I suppose
> that is not a real problem, but probably related to some clock setup that
> barebox master does somewhere during early boot (which I suppose, is skipped
> when booting it as 2nd stage).
> 
> However, when flashing the resulting image to NAND, there seems to be a bigger
> issue somewhere during early boot. This problem does not exist when compiling
> barebox master with OSELAS 2016.

I gave it a test and can confirm that the board boots when compiled with
OSELAS 2016 and no longer boots with OSELAS 2018.

It's strange and I'm out of ideas for now. In
imx27_barebox_boot_nand_external() we have a place that copies the
initial image poprtion into SDRAM. It seems the SDRAM is never written
to - at least according to the information my BDI2000 gives me.

I assume it must be something to do with the SDRAM setup, but the code
and also the resulting assembly really looks harmless, though a little
different between both toolchains.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[Baeuerle, Florian]

Am Montag, den 27.08.2018, 14:10 +0200 schrieb Sascha Hauer:
> On Thu, Aug 23, 2018 at 12:20:32PM +0000, Baeuerle, Florian wrote:
> > Some background on that patch:
> > 
> > I've tried to get barebox master compiled with OSELAS 2018 running on a
> > phycard-imx27. I had a few problems with that:
> > 
> > It turned out, that I can boot the resulting image as a seconds stage (from an
> > older version of barebox), after commenting out pca100_usb_init(). I suppose
> > that is not a real problem, but probably related to some clock setup that
> > barebox master does somewhere during early boot (which I suppose, is skipped
> > when booting it as 2nd stage).
> > 
> > However, when flashing the resulting image to NAND, there seems to be a bigger
> > issue somewhere during early boot. This problem does not exist when compiling
> > barebox master with OSELAS 2016.
> 
> I gave it a test and can confirm that the board boots when compiled with
> OSELAS 2016 and no longer boots with OSELAS 2018.

Thanks for confirming this!
> 
> It's strange and I'm out of ideas for now. In
> imx27_barebox_boot_nand_external() we have a place that copies the
> initial image poprtion into SDRAM. It seems the SDRAM is never written
> to - at least according to the information my BDI2000 gives me.

What could you observe with your debugger?
I sadly do not have any hardware debugger available, so I was stuck with writing
characters on the UART which IIRC was completely unsuccessful in
imx27_barebox_boot_nand_external().
> 
> I assume it must be something to do with the SDRAM setup, but the code
> and also the resulting assembly really looks harmless, though a little
> different between both toolchains.
> 
> Sascha
> 
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[s.hauer]

On Mon, Aug 27, 2018 at 12:37:18PM +0000, Baeuerle, Florian wrote:
> Am Montag, den 27.08.2018, 14:10 +0200 schrieb Sascha Hauer:
> > On Thu, Aug 23, 2018 at 12:20:32PM +0000, Baeuerle, Florian wrote:
> > > Some background on that patch:
> > > 
> > > I've tried to get barebox master compiled with OSELAS 2018 running on a
> > > phycard-imx27. I had a few problems with that:
> > > 
> > > It turned out, that I can boot the resulting image as a seconds stage (from an
> > > older version of barebox), after commenting out pca100_usb_init(). I suppose
> > > that is not a real problem, but probably related to some clock setup that
> > > barebox master does somewhere during early boot (which I suppose, is skipped
> > > when booting it as 2nd stage).
> > > 
> > > However, when flashing the resulting image to NAND, there seems to be a bigger
> > > issue somewhere during early boot. This problem does not exist when compiling
> > > barebox master with OSELAS 2016.
> > 
> > I gave it a test and can confirm that the board boots when compiled with
> > OSELAS 2016 and no longer boots with OSELAS 2018.
> 
> Thanks for confirming this!
> > 
> > It's strange and I'm out of ideas for now. In
> > imx27_barebox_boot_nand_external() we have a place that copies the
> > initial image poprtion into SDRAM. It seems the SDRAM is never written
> > to - at least according to the information my BDI2000 gives me.
> 
> What could you observe with your debugger?
> I sadly do not have any hardware debugger available, so I was stuck with writing
> characters on the UART which IIRC was completely unsuccessful in
> imx27_barebox_boot_nand_external().

I can see that we execute this copy loop:

     518:	e592c000 	ldr	ip, [r2]
     51c:	e2822004 	add	r2, r2, #4
     520:	e580c000 	str	ip, [r0]
     524:	e1520001 	cmp	r2, r1
     528:	e2820332 	add	r0, r2, #-939524096	; 0xc8000000
     52c:	1afffff9 	bne	518 <imx27_barebox_boot_nand_external+0x18>

When stopping at 524 we have this register content:

         User     FIQ     Superv   Abort     IRQ      Undef
GPR00: a0000000 a0000000 a0000000 a0000000 a0000000 a0000000
GPR01: d8000800 d8000800 d8000800 d8000800 d8000800 d8000800
GPR02: d8000004 d8000004 d8000004 d8000004 d8000004 d8000004
GPR03: d80012a0 d80012a0 d80012a0 d80012a0 d80012a0 d80012a0
GPR04: d80012a0 d80012a0 d80012a0 d80012a0 d80012a0 d80012a0
GPR05: 28c04080 28c04080 28c04080 28c04080 28c04080 28c04080
GPR06: 22604914 22604914 22604914 22604914 22604914 22604914
GPR07: 062008cc 062008cc 062008cc 062008cc 062008cc 062008cc
GPR08: 04808005 20000061 04808005 04808005 04808005 04808005
GPR09: 2b3107cd 08930146 2b3107cd 2b3107cd 2b3107cd 2b3107cd
GPR10: 80140001 61081110 80140001 80140001 80140001 80140001
GPR11: 2310000d 00026000 2310000d 2310000d 2310000d 2310000d
GPR12: ea000012 a8080e28 ea000012 ea000012 ea000012 ea000012
GPR13: 294108a0 950200c0 ffffffec 45525940 80110208 82c00a08
GPR14: 89830033 19022184 d800005c 32010501 00140011 000d0812
PC   : d8000524
CPSR : 200000d3
SPSR :          00000010 00000010 00000010 00000010 00000010

So r0 correctly contains the destination address (0xa0000000), the ip
register (GPR12) contains the value read from 0xd8000000 (0xea000012),
but reading the memory at 0xa0000000 still contains the value that
was there before the first loop iteration, as if the memory was never
written to:

md 0xa0000000:
a0000000 : 0a884784 8340111c 00001004 02101308  .G....@.........
a0000010 : 50201a48 20a042c4 12d01504 10081000  H. P.B. ........
...

With OSELAS 2016 the copy loop looks a little different, but works as
expected.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH] ARM: phytec-phycard-imx27: Add debug UART support

[Baeuerle, Florian]

Am Donnerstag, den 23.08.2018, 18:57 -0700 schrieb Andrey Smirnov:
> On Thu, Aug 23, 2018 at 2:59 AM Florian Bäuerle
> <florian.baeuerle@allegion.com> wrote:
> > 
> > Signed-off-by: Florian Bäuerle <florian.baeuerle@allegion.com>
> > ---
> >  arch/arm/boards/phytec-phycard-imx27/lowlevel.c | 15 +++++++++++++++
> >  arch/arm/mach-imx/include/mach/debug_ll.h       | 13 +++++++++++++
> >  include/serial/imx-uart.h                       |  5 +++++
> >  3 files changed, 33 insertions(+)
> > 
> > diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> > index e1132e0..8244337 100644
> > --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> > +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
> > @@ -14,6 +14,8 @@
> >  #include <mach/imx-pll.h>
> >  #include <mach/esdctl.h>
> >  #include <mach/imx-nand.h>
> > +#include <mach/debug_ll.h>
> > +#include <serial/imx-uart.h>
> > 
> >  #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
> > 
> > @@ -58,6 +60,18 @@ static void sdram_init(void)
> >                         MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
> >  }
> > 
> > +static void setup_uart(void)
> > +{
> > +       /* Set PE[12-15] use, direction, function and pull-up */
> > +       writel(0xfffc0f27, MX27_GPIO5_BASE_ADDR + 0x20);
> > +       writel(0x00005000, MX27_GPIO5_BASE_ADDR);
> > +       writel(0x00000000, MX27_GPIO5_BASE_ADDR + 0x38);
> > +       writel(0xffff0fff, MX27_GPIO5_BASE_ADDR + 0x40);
> > +
> 
> Can constants from iomux-imx27.h be used here?

In theory yes, it could be done with imx_gpio_mode(). I think it's better to
leave it as is, otherwise, we'd need a) the pinctrl driver in
the pbl (probably
too large) or b) do the same as imx_gpio_mode and extract the ORed values from a
newly defined constant and basically
reimplement imx_gpio_mode.

The register offsets are also only defined in drivers/pinctrl/imx-iomux-v1.c

> 
> > +       imx27_ungate_all_peripherals();
> > +       imx27_uart_setup_ll();
> > +}
> > +
> >  void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
> >  {
> >         unsigned long r;
> > @@ -97,6 +111,7 @@ void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
> >                 MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
> > 
> >         sdram_init();
> > +       setup_uart();
> 
> Majority of the boards gates this to happen on if
> IS_ENABLED(CONFIG_DEBUG_LL) is true, so it might make sense to do the
> same.

you're right.

> 
> > 
> >         imx27_barebox_boot_nand_external(fdt);
> >  }
> > diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
> > index 1550e05..6c9b21d 100644
> > --- a/arch/arm/mach-imx/include/mach/debug_ll.h
> > +++ b/arch/arm/mach-imx/include/mach/debug_ll.h
> > @@ -56,6 +56,12 @@
> >  #error "unknown i.MX debug uart soc type"
> >  #endif
> > 
> > +static inline void imx27_uart_setup_ll(void)  {
> > +       void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
> > +                               CONFIG_DEBUG_IMX_UART_PORT));
> > +       imx27_uart_setup(base);
> > +}
> > +
> >  static inline void imx50_uart_setup_ll(void)
> >  {
> >         void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
> > @@ -121,6 +127,7 @@ static inline void PUTC_LL(int c)
> > 
> >  #else
> > 
> > +static inline void imx27_uart_setup_ll(void) {}
> >  static inline void imx50_uart_setup_ll(void) {}
> >  static inline void imx51_uart_setup_ll(void) {}
> >  static inline void imx53_uart_setup_ll(void) {}
> > @@ -138,6 +145,12 @@ static inline void imx_ungate_all_peripherals(void __iomem *ccmbase)
> >                 writel(0xffffffff, ccmbase + i);
> >  }
> > 
> > +static inline void imx27_ungate_all_peripherals(void)
> > +{
> > +       writel(0xfffffbff, IOMEM(MX27_CCM_BASE_ADDR) + 0x20);
> > +       writel(0xfffffffc, IOMEM(MX27_CCM_BASE_ADDR) + 0x24);
> > +}
> 
> I think you can use  MX27_PCCR0 and  MX27_PCCR1 here instead of magic numbers.

yep, thanks.

> 
> > +
> >  static inline void imx6_ungate_all_peripherals(void)
> >  {
> >         imx_ungate_all_peripherals(IOMEM(MX6_CCM_BASE_ADDR));
> > diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
> > index c236065..0c033c2 100644
> > --- a/include/serial/imx-uart.h
> > +++ b/include/serial/imx-uart.h
> > @@ -155,6 +155,11 @@ static inline void imx_uart_set_dte(void __iomem *uartbase)
> >         writel(ufcr, uartbase + UFCR);
> >  }
> > 
> > +static inline void imx27_uart_setup(void __iomem *uartbase)
> > +{
> > +       imx_uart_setup(uartbase, 66500000);
> > +}
> > +
> >  static inline void imx50_uart_setup(void __iomem *uartbase)
> >  {
> >         imx_uart_setup(uartbase, 66666666);
> > --
> > 1.8.3.1
> > 
> > 
> > _______________________________________________
> > barebox mailing list
> > barebox@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/barebox
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH v2] ARM: phytec-phycard-imx27: Add debug UART support

[Florian Bäuerle]

Signed-off-by: Florian Bäuerle <florian.baeuerle@allegion.com>
---
 arch/arm/boards/phytec-phycard-imx27/lowlevel.c | 16 ++++++++++++++++
 arch/arm/mach-imx/include/mach/debug_ll.h       | 13 +++++++++++++
 include/serial/imx-uart.h                       |  5 +++++
 3 files changed, 34 insertions(+)

diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
index e1132e0..a1f12e8 100644
--- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
@@ -14,6 +14,8 @@
 #include <mach/imx-pll.h>
 #include <mach/esdctl.h>
 #include <mach/imx-nand.h>
+#include <mach/debug_ll.h>
+#include <serial/imx-uart.h>
 
 #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
 
@@ -58,6 +60,18 @@ static void sdram_init(void)
 			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
 }
 
+static void setup_uart(void)
+{
+	/* Set PE[12-15] use, direction, function and pull-up */
+	writel(0xfffc0f27, MX27_GPIO5_BASE_ADDR + 0x20);
+	writel(0x00005000, MX27_GPIO5_BASE_ADDR);
+	writel(0x00000000, MX27_GPIO5_BASE_ADDR + 0x38);
+	writel(0xffff0fff, MX27_GPIO5_BASE_ADDR + 0x40);
+
+	imx27_ungate_all_peripherals();
+	imx27_uart_setup_ll();
+}
+
 void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
 {
 	unsigned long r;
@@ -97,6 +111,8 @@ void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
 		MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
 
 	sdram_init();
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
 
 	imx27_barebox_boot_nand_external(fdt);
 }
diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index 1550e05..e045a1f 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -56,6 +56,12 @@
 #error "unknown i.MX debug uart soc type"
 #endif
 
+static inline void imx27_uart_setup_ll(void)  {
+	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
+				CONFIG_DEBUG_IMX_UART_PORT));
+	imx27_uart_setup(base);
+}
+
 static inline void imx50_uart_setup_ll(void)
 {
 	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
@@ -121,6 +127,7 @@ static inline void PUTC_LL(int c)
 
 #else
 
+static inline void imx27_uart_setup_ll(void) {}
 static inline void imx50_uart_setup_ll(void) {}
 static inline void imx51_uart_setup_ll(void) {}
 static inline void imx53_uart_setup_ll(void) {}
@@ -138,6 +145,12 @@ static inline void imx_ungate_all_peripherals(void __iomem *ccmbase)
 		writel(0xffffffff, ccmbase + i);
 }
 
+static inline void imx27_ungate_all_peripherals(void)
+{
+	writel(0xfffffbff, IOMEM(MX27_CCM_BASE_ADDR) + MX27_PCCR0);
+	writel(0xfffffffc, IOMEM(MX27_CCM_BASE_ADDR) + MX27_PCCR1);
+}
+
 static inline void imx6_ungate_all_peripherals(void)
 {
 	imx_ungate_all_peripherals(IOMEM(MX6_CCM_BASE_ADDR));
diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
index c236065..0c033c2 100644
--- a/include/serial/imx-uart.h
+++ b/include/serial/imx-uart.h
@@ -155,6 +155,11 @@ static inline void imx_uart_set_dte(void __iomem *uartbase)
 	writel(ufcr, uartbase + UFCR);
 }
 
+static inline void imx27_uart_setup(void __iomem *uartbase)
+{
+	imx_uart_setup(uartbase, 66500000);
+}
+
 static inline void imx50_uart_setup(void __iomem *uartbase)
 {
 	imx_uart_setup(uartbase, 66666666);
-- 
1.8.3.1


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox