From: Lucas Stach <l.stach@pengutronix.de>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>,
barebox@lists.infradead.org, rcz@pengutronix.de,
Lucas Stach <lst@pengutronix.de>
Subject: Re: [PATCH 1/3] ARM64: entry: save/restore potentially clobbered registers
Date: Fri, 20 Dec 2019 16:42:01 +0100 [thread overview]
Message-ID: <98d2d1809d0ec5ce73883bea0280b171e44b7c69.camel@pengutronix.de> (raw)
In-Reply-To: <8b2367fa-b90e-0ce0-d906-cf4212a9ef2a@pengutronix.de>
Hi Ahmad,
On Fr, 2019-12-20 at 16:34 +0100, Ahmad Fatoum wrote:
> Hello Lucas,
>
> On 12/19/19 10:13 AM, Lucas Stach wrote:
> > While the comment is correct that currently arm_early_mmu_cache_invalidate()
> > is only a call to to v8_invalidate_icache_all() , which doesn't clobber x0-x2,
> > this starts to fall apart as soon as we do something more in this function.
> >
> > Make sure to properly save/restore the parameters passed to the entry function.
>
> I did the same in <20191002075754.9257-1-a.fatoum@pengutronix.de>, except for
> x4-x6 instead of x19-x21, but reported that his i.MX8 still didn't boot.
I have not thoroughly analyzed the called cache maintenance functions,
but I specifically used x19-x21 as they are defined as callee-saved in
the aarch64 calling convention.
x4-x6 would be function parameter/return values, so they might get
clobbered, right?
Regards,
Lucas
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next prev parent reply other threads:[~2019-12-20 15:42 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-19 9:13 [PATCH 0/3] ARM64 early cache fixes Lucas Stach
2019-12-19 9:13 ` [PATCH 1/3] ARM64: entry: save/restore potentially clobbered registers Lucas Stach
2019-12-20 15:34 ` Ahmad Fatoum
2019-12-20 15:42 ` Lucas Stach [this message]
2019-12-20 16:14 ` Ahmad Fatoum
2019-12-19 9:13 ` [PATCH 2/3] ARM: cache_64: invalidate dcache in arm_early_mmu_cache_invalidate Lucas Stach
2019-12-19 9:13 ` [PATCH 3/3] ARM: cache_64: invalidate icache in arm_early_mmu_cache_flush Lucas Stach
2019-12-20 15:14 ` [PATCH 0/3] ARM64 early cache fixes Sascha Hauer
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