[PATCH 00/11] ARM: i.MX8MQ and EVK support, part II

[PATCH 00/11] ARM: i.MX8MQ and EVK support, part II

[Andrey Smirnov]

Everyone:

This is part II of i.MX8MQ EVK board support patches. This time this
is bits and pieces that were necessary in order to allow booting
vendor Linux kernel availible here (tag: rel_imx_4.9.51_8mq_ga):

    https://source.codeaurora.org/external/imx/linux-imx

Sources for ATF were taken from here (tag: rel_imx_4.9.51_8mq_ga):

    https://source.codeaurora.org/external/imx/imx-atf

This patchest is also availible at:

    https://github.com/ndreys/barebox/tree/imx8m-support-part-II-v1

Feedback is welcome!

Thanks,
Andrey Smirnov

Andrey Smirnov (11):
  ARM: nxp-imx8mq-evk: Update DDR initialization code
  ARM: Add code to support SMCCC on AArch64
  ARM: i.MX8MQ: Configure cntfrq only in EL3
  ARM: i.MX8MQ: Add a macro to load BL31 ATF blob
  ARM: i.MX: xload-esdhc: Move image base to MX8MQ_ATF_BL33_BASE_ADDR
  ARM: i.MX: xload-esdhc: Allow patching first word of the image
  ARM: i.MX: fimware: Add pre-built BL31 ATF blob
  ARM: nxp-imx8mq-evk: Add code to load ATF BL31 blob
  ARM: i.MX8MQ: Query and display ATF fimware hash if availible
  ARM: nxp-imx8mq-evk: Add bootflow comments
  firmware: Fix copy-paste comment mistake

 arch/arm/Kconfig                              |   4 +
 arch/arm/boards/nxp-imx8mq-evk/ddr_init.c     | 120 +++++-----
 arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c | 219 +++++-------------
 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c     |  45 +++-
 arch/arm/cpu/Makefile                         |   4 +-
 arch/arm/cpu/smccc-call_64.S                  |  52 +++++
 arch/arm/include/asm/asm-offsets.h            |   1 +
 arch/arm/lib/asm-offsets.c                    |   7 +-
 arch/arm/mach-imx/Kconfig                     |   2 +
 arch/arm/mach-imx/imx8mq.c                    |  29 ++-
 arch/arm/mach-imx/include/mach/atf.h          |  63 +++++
 arch/arm/mach-imx/xload-esdhc.c               |  19 +-
 firmware/Kconfig                              |   3 +
 firmware/Makefile                             |   6 +-
 firmware/imx/imx8m-bl31.bin                   | Bin 0 -> 46744 bytes
 include/linux/arm-smccc.h                     | 135 +++++++++++
 16 files changed, 479 insertions(+), 230 deletions(-)
 create mode 100644 arch/arm/cpu/smccc-call_64.S
 create mode 100644 arch/arm/include/asm/asm-offsets.h
 create mode 100644 arch/arm/mach-imx/include/mach/atf.h
 create mode 100755 firmware/imx/imx8m-bl31.bin
 create mode 100644 include/linux/arm-smccc.h

-- 
2.17.1


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[PATCH 01/11] ARM: nxp-imx8mq-evk: Update DDR initialization code

[Andrey Smirnov]

Previous version of DDR initialization code was generated by a beta
version of MX8_DDR_tool. This updates the code to the output of
MX8_DDR_tool v1.0, which seem to fix the vendor Linux kernel hang*
that was happening with the previous version.

* The kernel would hang as soon as it tried to utilize DDR's DVFS
  features and switch DDR frequency (disabling busfreq-imx8mq.c would
  fix the problem).

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/nxp-imx8mq-evk/ddr_init.c     | 120 +++++-----
 arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c | 219 +++++-------------
 2 files changed, 125 insertions(+), 214 deletions(-)

diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
index 81691b2fa..44103b5e2 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
@@ -2,7 +2,8 @@
  * Copyright 2017 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
- * Generated code from MX8_DDR_tool
+ *
+ * Generated code from MX8M_DDR_tool
  */
 
 #include "ddr.h"
@@ -21,7 +22,7 @@ void ddr_init(void)
 	reg32_write(0x303a00f8,tmp);
 	reg32_write(0x30391000,0x8f000000);
 	reg32_write(0x30391004,0x8f000000);
-	reg32_write(0x30360068,0xbbe580);
+	reg32_write(0x30360068,0xece580);
 	tmp=reg32_read(0x30360060);
 	tmp &= ~0x80;
 	reg32_write(0x30360060,tmp);
@@ -41,18 +42,19 @@ void ddr_init(void)
 	reg32_write(0x30391000,0x8f000006);
 	reg32_write(0x3d400304,0x1);
 	reg32_write(0x3d400030,0x1);
-	reg32_write(0x3d400000,0x83080020);
+	reg32_write(0x3d400000,0xa3080020);
+	reg32_write(0x3d400028,0x0);
+	reg32_write(0x3d400020,0x203);
+	reg32_write(0x3d400024,0x186a000);
 	reg32_write(0x3d400064,0x6100e0);
 	reg32_write(0x3d4000d0,0xc003061c);
 	reg32_write(0x3d4000d4,0x9e0000);
 	reg32_write(0x3d4000dc,0xd4002d);
 	reg32_write(0x3d4000e0,0x310008);
-	reg32_write(0x3d4000e8,0x46004d);
-	reg32_write(0x3d4000ec,0x15004d);
-	reg32_write(0x3d4000f4,0x639);
+	reg32_write(0x3d4000e8,0x66004a);
+	reg32_write(0x3d4000ec,0x16004a);
 	reg32_write(0x3d400100,0x1a201b22);
 	reg32_write(0x3d400104,0x60633);
-	reg32_write(0x3d400108,0x70e1214);
 	reg32_write(0x3d40010c,0xc0c000);
 	reg32_write(0x3d400110,0xf04080f);
 	reg32_write(0x3d400114,0x2040c0c);
@@ -64,78 +66,77 @@ void ddr_init(void)
 	reg32_write(0x3d400144,0xa00050);
 	reg32_write(0x3d400180,0x3200018);
 	reg32_write(0x3d400184,0x28061a8);
+	reg32_write(0x3d400188,0x0);
 	reg32_write(0x3d400190,0x497820a);
 	reg32_write(0x3d400194,0x80303);
-	reg32_write(0x3d4001b4,0x170a);
-	reg32_write(0x3d4001b0,0x11);
 	reg32_write(0x3d4001a0,0xe0400018);
 	reg32_write(0x3d4001a4,0xdf00e4);
-	reg32_write(0x3d4001a8,0x0);
+	reg32_write(0x3d4001a8,0x80000000);
+	reg32_write(0x3d4001b0,0x11);
+	reg32_write(0x3d4001b4,0x170a);
 	reg32_write(0x3d4001c0,0x1);
 	reg32_write(0x3d4001c4,0x1);
+	reg32_write(0x3d4000f4,0x639);
+	reg32_write(0x3d400108,0x70e1214);
 	reg32_write(0x3d400200,0x15);
 	reg32_write(0x3d40020c,0x0);
 	reg32_write(0x3d400210,0x1f1f);
 	reg32_write(0x3d400204,0x80808);
 	reg32_write(0x3d400214,0x7070707);
 	reg32_write(0x3d400218,0x48080707);
+	reg32_write(0x3d402020,0x1);
+	reg32_write(0x3d402024,0x518b00);
+	reg32_write(0x3d402050,0x20d040);
+	reg32_write(0x3d402064,0x14002f);
+	reg32_write(0x3d4020dc,0x940009);
+	reg32_write(0x3d4020e0,0x310000);
+	reg32_write(0x3d4020e8,0x66004a);
+	reg32_write(0x3d4020ec,0x16004a);
+	reg32_write(0x3d402100,0xb070508);
+	reg32_write(0x3d402104,0x3040b);
+	reg32_write(0x3d402108,0x305090c);
+	reg32_write(0x3d40210c,0x505000);
+	reg32_write(0x3d402110,0x4040204);
+	reg32_write(0x3d402114,0x2030303);
+	reg32_write(0x3d402118,0x1010004);
+	reg32_write(0x3d40211c,0x301);
+	reg32_write(0x3d402130,0x20300);
+	reg32_write(0x3d402134,0xa100002);
+	reg32_write(0x3d402138,0x31);
+	reg32_write(0x3d402144,0x220011);
+	reg32_write(0x3d402180,0xa70006);
+	reg32_write(0x3d402190,0x3858202);
+	reg32_write(0x3d402194,0x80303);
+	reg32_write(0x3d4021b4,0x502);
 	reg32_write(0x3d400244,0x0);
-	reg32_write(0x3d400490,0x1);
-	reg32_write(0x3d400250,0x29001f01);
+	reg32_write(0x3d400250,0x29001505);
 	reg32_write(0x3d400254,0x2c);
-	reg32_write(0x3d400264,0x900093e7);
+	reg32_write(0x3d40025c,0x5900575b);
+	reg32_write(0x3d400264,0x9);
 	reg32_write(0x3d40026c,0x2005574);
-	reg32_write(0x3d400400,0x400);
+	reg32_write(0x3d400300,0x16);
+	reg32_write(0x3d400304,0x0);
+	reg32_write(0x3d40030c,0x0);
+	reg32_write(0x3d400320,0x1);
+	reg32_write(0x3d40036c,0x11);
+	reg32_write(0x3d400400,0x111);
+	reg32_write(0x3d400404,0x10f3);
 	reg32_write(0x3d400408,0x72ff);
-	reg32_write(0x3d400494,0x10e00);
-	reg32_write(0x3d400498,0x620096);
-	reg32_write(0x3d40049c,0x10e00);
-	reg32_write(0x3d4004a0,0x12c);
+	reg32_write(0x3d400490,0x1);
+	reg32_write(0x3d400494,0x1110d00);
+	reg32_write(0x3d400498,0x620790);
+	reg32_write(0x3d40049c,0x100001);
+	reg32_write(0x3d4004a0,0x41f);
 	reg32_write(0x30391000,0x8f000004);
 	reg32_write(0x30391000,0x8f000000);
-	reg32_write(0x3d400304,0x0);
 	reg32_write(0x3d400030,0xa8);
+	do{
+		tmp=reg32_read(0x3d400004);
+		if(tmp&0x223) break;
+	}while(1);
 	reg32_write(0x3d400320,0x0);
 	reg32_write(0x3d000000,0x1);
 	reg32_write(0x3d4001b0,0x10);
-	reg32_write(0x3d402100,0xa040305);
-	reg32_write(0x3d402104,0x30407);
-	reg32_write(0x3d402108,0x203060b);
-	reg32_write(0x3d40210c,0x505000);
-	reg32_write(0x3d402110,0x2040202);
-	reg32_write(0x3d402114,0x2030202);
-	reg32_write(0x3d402118,0x1010004);
-	reg32_write(0x3d40211c,0x301);
-	reg32_write(0x3d402138,0x1d);
-	reg32_write(0x3d402144,0x14000a);
-	reg32_write(0x3d403024,0x30d400);
-	reg32_write(0x3d402050,0x20d040);
-	reg32_write(0x3d402190,0x3818200);
-	reg32_write(0x3d4021b4,0x100);
-	reg32_write(0x3d402064,0xc001c);
-	reg32_write(0x3d4020dc,0x840000);
-	reg32_write(0x3d4020e8,0x46004d);
-	reg32_write(0x3d4020ec,0x15004d);
-	reg32_write(0x3d4020e0,0x310000);
-	reg32_write(0x3d403100,0x6010102);
-	reg32_write(0x3d403104,0x30404);
-	reg32_write(0x3d403108,0x203060b);
-	reg32_write(0x3d40310c,0x505000);
-	reg32_write(0x3d403110,0x2040202);
-	reg32_write(0x3d403114,0x2030202);
-	reg32_write(0x3d403118,0x1010004);
-	reg32_write(0x3d40311c,0x301);
-	reg32_write(0x3d403138,0x8);
-	reg32_write(0x3d403144,0x50003);
-	reg32_write(0x3d403024,0xc3500);
-	reg32_write(0x3d403050,0x20d040);
-	reg32_write(0x3d403190,0x3818200);
-	reg32_write(0x3d4031b4,0x100);
-	reg32_write(0x3d403064,0x30007);
-	reg32_write(0x3d4030dc,0x840000);
-	reg32_write(0x3d4030e8,0x46004d);
-	reg32_write(0x3d4030ec,0x15004d);
-	reg32_write(0x3d4030e0,0x310000);
 	reg32_write(0x3c040280,0x0);
 	reg32_write(0x3c040284,0x1);
 	reg32_write(0x3c040288,0x2);
@@ -218,6 +219,7 @@ void ddr_init(void)
 
 	/* enable port 0 */
 	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
-	tmp = reg32_read(DDRC_CRCPARSTAT(0));
-	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+	/* enable DDR auto-refresh mode */
+	tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
+	reg32_write(DDRC_RFSHCTL3(0), tmp);
 }
\ No newline at end of file
diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
index 156d7cf87..1b30ff725 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
@@ -2,6 +2,8 @@
  * Copyright 2017 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
  */
 
 #include "ddr.h"
@@ -32,14 +34,6 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c44857c,0x1ff);
 	reg32_write(0x3c44c17c,0x1ff);
 	reg32_write(0x3c44c57c,0x1ff);
-	reg32_write(0x3c84017c,0x1ff);
-	reg32_write(0x3c84057c,0x1ff);
-	reg32_write(0x3c84417c,0x1ff);
-	reg32_write(0x3c84457c,0x1ff);
-	reg32_write(0x3c84817c,0x1ff);
-	reg32_write(0x3c84857c,0x1ff);
-	reg32_write(0x3c84c17c,0x1ff);
-	reg32_write(0x3c84c57c,0x1ff);
 	reg32_write(0x3c000154,0x1ff);
 	reg32_write(0x3c004154,0x1ff);
 	reg32_write(0x3c008154,0x1ff);
@@ -52,22 +46,16 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c024154,0x1ff);
 	reg32_write(0x3c080314,0x19);
 	reg32_write(0x3c480314,0x7);
-	reg32_write(0x3c880314,0x7);
 	reg32_write(0x3c0800b8,0x2);
-	reg32_write(0x3c4800b8,0x2);
-	reg32_write(0x3c8800b8,0x2);
+	reg32_write(0x3c4800b8,0x1);
 	reg32_write(0x3c240810,0x0);
 	reg32_write(0x3c640810,0x0);
-	reg32_write(0x3ca40810,0x0);
 	reg32_write(0x3c080090,0xab);
 	reg32_write(0x3c0800e8,0x0);
 	reg32_write(0x3c480090,0xab);
 	reg32_write(0x3c0800e8,0x0);
-	reg32_write(0x3c880090,0xab);
-	reg32_write(0x3c0800e8,0x0);
-	reg32_write(0x3c080158,0x7);
+	reg32_write(0x3c080158,0x3);
 	reg32_write(0x3c480158,0xa);
-	reg32_write(0x3c880158,0xa);
 	reg32_write(0x3c040134,0xe00);
 	reg32_write(0x3c040534,0xe00);
 	reg32_write(0x3c044134,0xe00);
@@ -84,14 +72,6 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c448534,0xe00);
 	reg32_write(0x3c44c134,0xe00);
 	reg32_write(0x3c44c534,0xe00);
-	reg32_write(0x3c840134,0xe00);
-	reg32_write(0x3c840534,0xe00);
-	reg32_write(0x3c844134,0xe00);
-	reg32_write(0x3c844534,0xe00);
-	reg32_write(0x3c848134,0xe00);
-	reg32_write(0x3c848534,0xe00);
-	reg32_write(0x3c84c134,0xe00);
-	reg32_write(0x3c84c534,0xe00);
 	reg32_write(0x3c040124,0xfbe);
 	reg32_write(0x3c040524,0xfbe);
 	reg32_write(0x3c044124,0xfbe);
@@ -108,14 +88,6 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c448524,0xfbe);
 	reg32_write(0x3c44c124,0xfbe);
 	reg32_write(0x3c44c524,0xfbe);
-	reg32_write(0x3c840124,0xfbe);
-	reg32_write(0x3c840524,0xfbe);
-	reg32_write(0x3c844124,0xfbe);
-	reg32_write(0x3c844524,0xfbe);
-	reg32_write(0x3c848124,0xfbe);
-	reg32_write(0x3c848524,0xfbe);
-	reg32_write(0x3c84c124,0xfbe);
-	reg32_write(0x3c84c524,0xfbe);
 	reg32_write(0x3c00010c,0x63);
 	reg32_write(0x3c00410c,0x63);
 	reg32_write(0x3c00810c,0x63);
@@ -130,8 +102,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c0801d4,0x4);
 	reg32_write(0x3c080140,0x0);
 	reg32_write(0x3c080020,0x320);
-	reg32_write(0x3c480020,0x64);
-	reg32_write(0x3c880020,0x19);
+	reg32_write(0x3c480020,0xa7);
 	reg32_write(0x3c080220,0x9);
 	reg32_write(0x3c0802c8,0xdc);
 	reg32_write(0x3c04010c,0x5a1);
@@ -151,33 +122,21 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c44850c,0x5a1);
 	reg32_write(0x3c44c10c,0x5a1);
 	reg32_write(0x3c44c50c,0x5a1);
-	reg32_write(0x3c8802c8,0xdc);
-	reg32_write(0x3c84010c,0x5a1);
-	reg32_write(0x3c84050c,0x5a1);
-	reg32_write(0x3c84410c,0x5a1);
-	reg32_write(0x3c84450c,0x5a1);
-	reg32_write(0x3c84810c,0x5a1);
-	reg32_write(0x3c84850c,0x5a1);
-	reg32_write(0x3c84c10c,0x5a1);
-	reg32_write(0x3c84c50c,0x5a1);
 	reg32_write(0x3c0803e8,0x1);
 	reg32_write(0x3c4803e8,0x1);
-	reg32_write(0x3c8803e8,0x1);
 	reg32_write(0x3c080064,0x1);
 	reg32_write(0x3c480064,0x1);
-	reg32_write(0x3c880064,0x1);
-	reg32_write(0x3c0803c0,0x660);
+	reg32_write(0x3c0803c0,0x0);
 	reg32_write(0x3c0803c4,0x0);
 	reg32_write(0x3c0803c8,0x4444);
 	reg32_write(0x3c0803cc,0x8888);
-	reg32_write(0x3c0803d0,0x5665);
+	reg32_write(0x3c0803d0,0x5555);
 	reg32_write(0x3c0803d4,0x0);
 	reg32_write(0x3c0803d8,0x0);
 	reg32_write(0x3c0803dc,0xf000);
 	reg32_write(0x3c080094,0x0);
 	reg32_write(0x3c0800b4,0x0);
 	reg32_write(0x3c4800b4,0x0);
-	reg32_write(0x3c8800b4,0x0);
 	reg32_write(0x3c080180,0x2);
 
 	//enable APB bus to access DDRPHY RAM
@@ -195,31 +154,32 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x15);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x15);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1500);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1500);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600);
 
 	//disable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
@@ -233,96 +193,57 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 
 	//set the PHY input clock to the desired frequency for pstate 1
-	reg32_write(0x3038a008,0x7070000);
-	reg32_write(0x3038a004,0x5000000);
-	reg32_write(0x3038a088,0x7070000);
-	reg32_write(0x3038a084,0x2010000);
-	reg32_write(0x303a00ec,0xffff);
-	tmp=reg32_read(0x303a00f8);
-	tmp |= 0x20;
-	reg32_write(0x303a00f8,tmp);
-	reg32_write(0x30389804,0x1000000);
-
-	//enable APB bus to access DDRPHY RAM
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
-
-	reg32_write(0x3c150008,0x101);
-	reg32_write(0x3c15000c,0x190);
-	reg32_write(0x3c150020,0x121f);
-	reg32_write(0x3c150064,0x84);
-	reg32_write(0x3c150068,0x31);
-	reg32_write(0x3c15006c,0x4d46);
-	reg32_write(0x3c150070,0x4d08);
-	reg32_write(0x3c150074,0x0);
-	reg32_write(0x3c150078,0x15);
-	reg32_write(0x3c15007c,0x84);
-	reg32_write(0x3c150080,0x31);
-	reg32_write(0x3c150084,0x4d46);
-	reg32_write(0x3c150088,0x4d08);
-	reg32_write(0x3c15008c,0x0);
-	reg32_write(0x3c150090,0x15);
-	reg32_write(0x3c1500c8,0x8400);
-	reg32_write(0x3c1500cc,0x3100);
-	reg32_write(0x3c1500d0,0x4600);
-	reg32_write(0x3c1500d4,0x84d);
-	reg32_write(0x3c1500d8,0x4d);
-	reg32_write(0x3c1500dc,0x1500);
-	reg32_write(0x3c1500e0,0x8400);
-	reg32_write(0x3c1500e4,0x3100);
-	reg32_write(0x3c1500e8,0x4600);
-	reg32_write(0x3c1500ec,0x84d);
-	reg32_write(0x3c1500f0,0x4d);
-	reg32_write(0x3c1500f4,0x1500);
-	reg32_write(0x3c1500f8,0x0);
-
-	//disable APB bus to access DDRPHY RAM
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-	//Reset MPU and run
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
-
-	//configure DDRPHY-FW DMEM structure @clock2...
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
-
-	//set the PHY input clock to the desired frequency for pstate 2
-	reg32_write(0x3038a008,0x7070000);
-	reg32_write(0x3038a004,0x2000000);
 	reg32_write(0x3038a088,0x7070000);
-	reg32_write(0x3038a084,0x2010000);
+	reg32_write(0x3038a084,0x4030000);
 	reg32_write(0x303a00ec,0xffff);
 	tmp=reg32_read(0x303a00f8);
 	tmp |= 0x20;
 	reg32_write(0x303a00f8,tmp);
-	reg32_write(0x30389804,0x1000000);
+	reg32_write(0x30360068,0xf5a406);
+	tmp=reg32_read(0x30360060);
+	tmp &= ~0x80;
+	reg32_write(0x30360060,tmp);
+	tmp=reg32_read(0x30360060);
+	tmp |= 0x200;
+	reg32_write(0x30360060,tmp);
+	tmp=reg32_read(0x30360060);
+	tmp &= ~0x20;
+	reg32_write(0x30360060,tmp);
+	tmp=reg32_read(0x30360060);
+	tmp &= ~0x10;
+	reg32_write(0x30360060,tmp);
+	do{
+		tmp=reg32_read(0x30360060);
+		if(tmp&0x80000000) break;
+	}while(1);
+	reg32_write(0x30389808,0x1000000);
 
 	//enable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 
-	reg32_write(0x3c150008,0x102);
-	reg32_write(0x3c15000c,0x64);
+	reg32_write(0x3c150008,0x1);
+	reg32_write(0x3c15000c,0x29c);
 	reg32_write(0x3c150020,0x121f);
-	reg32_write(0x3c150064,0x84);
+	reg32_write(0x3c150064,0x994);
 	reg32_write(0x3c150068,0x31);
 	reg32_write(0x3c15006c,0x4d46);
 	reg32_write(0x3c150070,0x4d08);
 	reg32_write(0x3c150074,0x0);
 	reg32_write(0x3c150078,0x15);
-	reg32_write(0x3c15007c,0x84);
+	reg32_write(0x3c15007c,0x994);
 	reg32_write(0x3c150080,0x31);
 	reg32_write(0x3c150084,0x4d46);
 	reg32_write(0x3c150088,0x4d08);
 	reg32_write(0x3c15008c,0x0);
 	reg32_write(0x3c150090,0x15);
-	reg32_write(0x3c1500c8,0x8400);
-	reg32_write(0x3c1500cc,0x3100);
+	reg32_write(0x3c1500c8,0x9400);
+	reg32_write(0x3c1500cc,0x3109);
 	reg32_write(0x3c1500d0,0x4600);
 	reg32_write(0x3c1500d4,0x84d);
 	reg32_write(0x3c1500d8,0x4d);
 	reg32_write(0x3c1500dc,0x1500);
-	reg32_write(0x3c1500e0,0x8400);
-	reg32_write(0x3c1500e4,0x3100);
+	reg32_write(0x3c1500e0,0x9400);
+	reg32_write(0x3c1500e4,0x3109);
 	reg32_write(0x3c1500e8,0x4600);
 	reg32_write(0x3c1500ec,0x84d);
 	reg32_write(0x3c1500f0,0x4d);
@@ -344,7 +265,7 @@ void ddr_cfg_phy(void) {
 	tmp=reg32_read(0x303a00f8);
 	tmp |= 0x20;
 	reg32_write(0x303a00f8,tmp);
-	reg32_write(0x30360068,0xbbe580);
+	reg32_write(0x30360068,0xece580);
 	tmp=reg32_read(0x30360060);
 	tmp &= ~0x80;
 	reg32_write(0x30360060,tmp);
@@ -380,28 +301,28 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x15);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x15);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1500);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1500);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a);
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600);
 
 	//disable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
@@ -912,10 +833,6 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c480030,0xc9);
 	reg32_write(0x3c480034,0x7d1);
 	reg32_write(0x3c480038,0x2c);
-	reg32_write(0x3c88002c,0x65);
-	reg32_write(0x3c880030,0xc9);
-	reg32_write(0x3c880034,0x7d1);
-	reg32_write(0x3c880038,0x2c);
 	reg32_write(0x3c240030,0x0);
 	reg32_write(0x3c240034,0x173);
 	reg32_write(0x3c240038,0x60);
@@ -928,8 +845,6 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c080044,0x3);
 	reg32_write(0x3c480040,0x5a);
 	reg32_write(0x3c480044,0x3);
-	reg32_write(0x3c880040,0x5a);
-	reg32_write(0x3c880044,0x3);
 	reg32_write(0x3c100200,0xe0);
 	reg32_write(0x3c100204,0x12);
 	reg32_write(0x3c100208,0xe0);
@@ -942,12 +857,6 @@ void ddr_cfg_phy(void) {
 	reg32_write(0x3c50020c,0x12);
 	reg32_write(0x3c500210,0xe0);
 	reg32_write(0x3c500214,0x12);
-	reg32_write(0x3c900200,0xe0);
-	reg32_write(0x3c900204,0x12);
-	reg32_write(0x3c900208,0xe0);
-	reg32_write(0x3c90020c,0x12);
-	reg32_write(0x3c900210,0xe0);
-	reg32_write(0x3c900214,0x12);
 	reg32_write(0x3c1003f4,0xf);
 	reg32_write(0x3c040044,0x1);
 	reg32_write(0x3c040048,0x1);
-- 
2.17.1


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[PATCH 02/11] ARM: Add code to support SMCCC on AArch64

[Andrey Smirnov]

Port SMCCC code from Linux kernel. To accomodate that:

  - Introduce CONFIG_ARM_SMCCC, to allow enabling the code
    independent of CONFIG_ARM_SECURE_MONITOR

  - Bring <linux/arm-smccc.h> in

  - Add necessary constants to arch/arm/asm-offsets.c

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/Kconfig                   |   4 +
 arch/arm/cpu/Makefile              |   4 +-
 arch/arm/cpu/smccc-call_64.S       |  52 +++++++++++
 arch/arm/include/asm/asm-offsets.h |   1 +
 arch/arm/lib/asm-offsets.c         |   7 +-
 include/linux/arm-smccc.h          | 135 +++++++++++++++++++++++++++++
 6 files changed, 200 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/cpu/smccc-call_64.S
 create mode 100644 arch/arm/include/asm/asm-offsets.h
 create mode 100644 include/linux/arm-smccc.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3555b4ee5..6f8eec708 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -388,7 +388,11 @@ config ARM_SEMIHOSTING
 	  the data on the host computer connected to the target via
 	  debugging channel (JTAG, SWD). If unsure say N
 
+config ARM_SMCCC
+	bool
+
 config ARM_SECURE_MONITOR
+        select ARM_SMCCC
 	bool
 
 config ARM_PSCI
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 5b4b832e8..874d723e2 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -21,8 +21,8 @@ obj-$(CONFIG_CPU_32v7) += no-mmu.o
 endif
 
 obj-$(CONFIG_ARM_PSCI) += psci.o
-obj-$(CONFIG_ARM_SECURE_MONITOR) += smccc-call.o
-AFLAGS_smccc-call.o	:=-Wa,-march=armv7-a
+obj-pbl-$(CONFIG_ARM_SMCCC) += smccc-call$(S64).o
+AFLAGS_smccc-call$(S64).o :=-Wa,-march=armv$(if $(S64),8,7)-a
 obj-$(CONFIG_ARM_SECURE_MONITOR) += sm.o sm_as.o
 AFLAGS_sm_as.o		:=-Wa,-march=armv7-a
 
diff --git a/arch/arm/cpu/smccc-call_64.S b/arch/arm/cpu/smccc-call_64.S
new file mode 100644
index 000000000..44888fb59
--- /dev/null
+++ b/arch/arm/cpu/smccc-call_64.S
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License Version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/linkage.h>
+#include <linux/arm-smccc.h>
+#include <asm/asm-offsets.h>
+
+	.macro SMCCC instr
+	.cfi_startproc
+	\instr	#0
+	ldr	x4, [sp]
+	stp	x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
+	stp	x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
+	ldr	x4, [sp, #8]
+	cbz	x4, 1f /* no quirk structure */
+	ldr	x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
+	cmp	x9, #ARM_SMCCC_QUIRK_QCOM_A6
+	b.ne	1f
+	str	x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
+1:	ret
+	.cfi_endproc
+	.endm
+
+/*
+ * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
+ *		  unsigned long a3, unsigned long a4, unsigned long a5,
+ *		  unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
+ *		  struct arm_smccc_quirk *quirk)
+ */
+ENTRY(__arm_smccc_smc)
+	SMCCC	smc
+ENDPROC(__arm_smccc_smc)
+
+/*
+ * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
+ *		  unsigned long a3, unsigned long a4, unsigned long a5,
+ *		  unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
+ *		  struct arm_smccc_quirk *quirk)
+ */
+ENTRY(__arm_smccc_hvc)
+	SMCCC	hvc
+ENDPROC(__arm_smccc_hvc)
\ No newline at end of file
diff --git a/arch/arm/include/asm/asm-offsets.h b/arch/arm/include/asm/asm-offsets.h
new file mode 100644
index 000000000..2f84e8399
--- /dev/null
+++ b/arch/arm/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
\ No newline at end of file
diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index 7bf6d129c..cdff6f782 100644
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -9,8 +9,13 @@
  */
 
 #include <linux/kbuild.h>
+#include <linux/arm-smccc.h>
 
 int main(void)
 {
-	return 0;
+  DEFINE(ARM_SMCCC_RES_X0_OFFS,		offsetof(struct arm_smccc_res, a0));
+  DEFINE(ARM_SMCCC_RES_X2_OFFS,		offsetof(struct arm_smccc_res, a2));
+  DEFINE(ARM_SMCCC_QUIRK_ID_OFFS,	offsetof(struct arm_smccc_quirk, id));
+  DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS,	offsetof(struct arm_smccc_quirk, state));
+  return 0;
 }
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
new file mode 100644
index 000000000..1b38b7b37
--- /dev/null
+++ b/include/linux/arm-smccc.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __LINUX_ARM_SMCCC_H
+#define __LINUX_ARM_SMCCC_H
+
+/*
+ * This file provides common defines for ARM SMC Calling Convention as
+ * specified in
+ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
+ */
+
+/* This constant is shifted by 31, make sure it's of an unsigned type */
+#define ARM_SMCCC_STD_CALL		0UL
+#define ARM_SMCCC_FAST_CALL		1UL
+#define ARM_SMCCC_TYPE_SHIFT		31
+
+#define ARM_SMCCC_SMC_32		0
+#define ARM_SMCCC_SMC_64		1
+#define ARM_SMCCC_CALL_CONV_SHIFT	30
+
+#define ARM_SMCCC_OWNER_MASK		0x3F
+#define ARM_SMCCC_OWNER_SHIFT		24
+
+#define ARM_SMCCC_FUNC_MASK		0xFFFF
+
+#define ARM_SMCCC_IS_FAST_CALL(smc_val)	\
+	((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT))
+#define ARM_SMCCC_IS_64(smc_val) \
+	((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT))
+#define ARM_SMCCC_FUNC_NUM(smc_val)	((smc_val) & ARM_SMCCC_FUNC_MASK)
+#define ARM_SMCCC_OWNER_NUM(smc_val) \
+	(((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK)
+
+#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \
+	(((type) << ARM_SMCCC_TYPE_SHIFT) | \
+	((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \
+	(((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \
+	((func_num) & ARM_SMCCC_FUNC_MASK))
+
+#define ARM_SMCCC_OWNER_ARCH		0
+#define ARM_SMCCC_OWNER_CPU		1
+#define ARM_SMCCC_OWNER_SIP		2
+#define ARM_SMCCC_OWNER_OEM		3
+#define ARM_SMCCC_OWNER_STANDARD	4
+#define ARM_SMCCC_OWNER_TRUSTED_APP	48
+#define ARM_SMCCC_OWNER_TRUSTED_APP_END	49
+#define ARM_SMCCC_OWNER_TRUSTED_OS	50
+#define ARM_SMCCC_OWNER_TRUSTED_OS_END	63
+
+#define ARM_SMCCC_QUIRK_NONE		0
+#define ARM_SMCCC_QUIRK_QCOM_A6		1 /* Save/restore register a6 */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/linkage.h>
+#include <linux/types.h>
+/**
+ * struct arm_smccc_res - Result from SMC/HVC call
+ * @a0-a3 result values from registers 0 to 3
+ */
+struct arm_smccc_res {
+	unsigned long a0;
+	unsigned long a1;
+	unsigned long a2;
+	unsigned long a3;
+};
+
+/**
+ * struct arm_smccc_quirk - Contains quirk information
+ * @id: quirk identification
+ * @state: quirk specific information
+ * @a6: Qualcomm quirk entry for returning post-smc call contents of a6
+ */
+struct arm_smccc_quirk {
+	int	id;
+	union {
+		unsigned long a6;
+	} state;
+};
+
+/**
+ * __arm_smccc_smc() - make SMC calls
+ * @a0-a7: arguments passed in registers 0 to 7
+ * @res: result values from registers 0 to 3
+ * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
+ *
+ * This function is used to make SMC calls following SMC Calling Convention.
+ * The content of the supplied param are copied to registers 0 to 7 prior
+ * to the SMC instruction. The return values are updated with the content
+ * from register 0 to 3 on return from the SMC instruction.  An optional
+ * quirk structure provides vendor specific behavior.
+ */
+asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,
+			unsigned long a2, unsigned long a3, unsigned long a4,
+			unsigned long a5, unsigned long a6, unsigned long a7,
+			struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);
+
+/**
+ * __arm_smccc_hvc() - make HVC calls
+ * @a0-a7: arguments passed in registers 0 to 7
+ * @res: result values from registers 0 to 3
+ * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
+ *
+ * This function is used to make HVC calls following SMC Calling
+ * Convention.  The content of the supplied param are copied to registers 0
+ * to 7 prior to the HVC instruction. The return values are updated with
+ * the content from register 0 to 3 on return from the HVC instruction.  An
+ * optional quirk structure provides vendor specific behavior.
+ */
+asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
+			unsigned long a2, unsigned long a3, unsigned long a4,
+			unsigned long a5, unsigned long a6, unsigned long a7,
+			struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);
+
+#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL)
+
+#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__)
+
+#define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL)
+
+#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__)
+
+#endif /*__ASSEMBLY__*/
+#endif /*__LINUX_ARM_SMCCC_H*/
-- 
2.17.1


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[PATCH 03/11] ARM: i.MX8MQ: Configure cntfrq only in EL3

[Andrey Smirnov]

We only can (and should only need to) configure cntfrq when running in
EL3 and executing this code in any other exception level will result
in exception.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/imx8mq.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
index f3246e437..dbcf4fa59 100644
--- a/arch/arm/mach-imx/imx8mq.c
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -62,12 +62,14 @@ static void imx8mq_silicon_revision(void)
 
 static int imx8mq_init_syscnt_frequency(void)
 {
-	void __iomem *syscnt = IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR);
-	/*
-	 * Update with accurate clock frequency
-	 */
-	set_cntfrq(syscnt_get_cntfrq(syscnt));
-	syscnt_enable(syscnt);
+	if (current_el() == 3) {
+		void __iomem *syscnt = IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR);
+		/*
+		 * Update with accurate clock frequency
+		 */
+		set_cntfrq(syscnt_get_cntfrq(syscnt));
+		syscnt_enable(syscnt);
+	}
 
 	return 0;
 }
-- 
2.17.1


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[PATCH 04/11] ARM: i.MX8MQ: Add a macro to load BL31 ATF blob

[Andrey Smirnov]

Add a macro containing all of the code needed to load and transfer
control to BL31 ATF blob on i.MX8M.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/include/mach/atf.h | 63 ++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 arch/arm/mach-imx/include/mach/atf.h

diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h
new file mode 100644
index 000000000..0b5018459
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/atf.h
@@ -0,0 +1,63 @@
+#ifndef __IMX_ATF_H__
+#define __IMX_ATF_H__
+
+#include <asm/system.h>
+
+#define MX8MQ_ATF_BL31_SIZE_LIMIT	SZ_64K
+#define MX8MQ_ATF_BL31_BASE_ADDR	0x00910000
+#define MX8MQ_ATF_BL33_BASE_ADDR	0x40200000
+
+/**
+ * imx8mq_atf_load_bl31 - Load ATF BL31 blob and transfer contol to it
+ *
+ * @name:	Name of the BL31 blob
+ *
+ * This macro:
+
+ *     1. Copies built-in BL31 blob to an address i.MX8M's BL31
+ *        expects to be placed
+ *
+ *     2. Sets up temporary stack pointer for EL2, which is execution
+ *        level that BL31 will drop us off at after it completes its
+ *        initialization routine
+ *
+ *     3. Transfers control to BL31
+ *
+ * NOTE: This has to be a macro in order delay the expansion of
+ * get_builtin_firmware(), otherwise it'll incorrectly interpret
+ * "name" literally
+ *
+ * NOTE: This function will do nothing if executed at any other EL
+ * than EL3. This is done intentionally to support single entry point
+ * initialization (see i.MX8M EVK for an example)
+ *
+ * NOTE: This function expects NXP's implementation of ATF that can be
+ * found at:
+ *     https://source.codeaurora.org/external/imx/imx-atf
+ *
+ * any other implementation may or may not work
+ *
+ */
+#define imx8mq_atf_load_bl31(name)					\
+	do {								\
+		void __noreturn (*bl31)(void) =				\
+			(void *)MX8MQ_ATF_BL31_BASE_ADDR;		\
+		size_t bl31_size;					\
+		const u8 *fw;						\
+									\
+		if (current_el() != 3)					\
+			break;						\
+									\
+		get_builtin_firmware(name, &fw, &bl31_size);		\
+		if (WARN_ON(bl31_size > MX8MQ_ATF_BL31_SIZE_LIMIT))	\
+			break;						\
+									\
+		memcpy(bl31, fw, bl31_size);				\
+		asm volatile("msr sp_el2, %0" : :			\
+			     "r" (MX8MQ_ATF_BL33_BASE_ADDR - 16) :	\
+			     "cc");					\
+									\
+		bl31();							\
+	} while (0)
+
+#endif
\ No newline at end of file
-- 
2.17.1


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[PATCH 05/11] ARM: i.MX: xload-esdhc: Move image base to MX8MQ_ATF_BL33_BASE_ADDR

[Andrey Smirnov]

BL31 ATF implementation provided by NXP will jump to
MX8MQ_ATF_BL33_BASE_ADDR after completing its initialization. Move
image base used by imx8_esdhc_start_image() in order to support that.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/xload-esdhc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
index 08ba9b08d..98ebdfcf7 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/arch/arm/mach-imx/xload-esdhc.c
@@ -14,6 +14,7 @@
 #include <common.h>
 #include <io.h>
 #include <mci.h>
+#include <mach/atf.h>
 #include <mach/imx6-regs.h>
 #include <mach/imx8mq-regs.h>
 #include <mach/xload.h>
@@ -323,5 +324,5 @@ int imx8_esdhc_start_image(int instance)
 
 	esdhc.is_mx6 = 1;
 
-	return esdhc_start_image(&esdhc, MX8MQ_DDR_CSD1_BASE_ADDR, SZ_32K);
+	return esdhc_start_image(&esdhc, MX8MQ_ATF_BL33_BASE_ADDR, SZ_32K);
 }
\ No newline at end of file
-- 
2.17.1


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[PATCH 06/11] ARM: i.MX: xload-esdhc: Allow patching first word of the image

[Andrey Smirnov]

Depending on how SD card/eMMC was programmed first byte of the image
ther may or may not have appropriate branch instruction. Extend
esdhc_start_image() to allow passing a custom callback that would
patch the first instruction in memory to correctly redirect the CPU to
the resto of the code.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/xload-esdhc.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
index 98ebdfcf7..c017a8b10 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/arch/arm/mach-imx/xload-esdhc.c
@@ -219,7 +219,8 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
 }
 
 static int
-esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset)
+esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset,
+		  u32 (*opcode_b)(u32))
 {
 	void *buf = (void *)address;
 	u32 *ivt = buf + offset + SZ_1K;
@@ -254,6 +255,9 @@ esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset)
 
 	bb = buf + ofs;
 
+	if (opcode_b)
+		*(u32 *)buf = opcode_b(ofs);
+
 	bb();
 }
 
@@ -292,7 +296,12 @@ int imx6_esdhc_start_image(int instance)
 
 	esdhc.is_mx6 = 1;
 
-	return esdhc_start_image(&esdhc, 0x10000000, 0);
+	return esdhc_start_image(&esdhc, 0x10000000, 0, NULL);
+}
+
+static u32 aarch64_opcode_b(u32 to)
+{
+	return 0x14000000 | (to / 4);
 }
 
 /**
@@ -324,5 +333,8 @@ int imx8_esdhc_start_image(int instance)
 
 	esdhc.is_mx6 = 1;
 
-	return esdhc_start_image(&esdhc, MX8MQ_ATF_BL33_BASE_ADDR, SZ_32K);
+	return esdhc_start_image(&esdhc,
+				 MX8MQ_ATF_BL33_BASE_ADDR,
+				 SZ_32K,
+				 aarch64_opcode_b);
 }
\ No newline at end of file
-- 
2.17.1


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[PATCH 07/11] ARM: i.MX: fimware: Add pre-built BL31 ATF blob

[Andrey Smirnov]

Running Linux on i.MX8M requires us to use and proerly set up a ARM
Trusted Firmware blob. For the sake of convenience, add a pre-built
blob to our firmware tree, so it can be used by individual boards.

This blob was built using Buildroot:

 - commit: 6b02b8210acb18773f2c4b26cfc11d1f9bc4fb88
 - defconig: freescale_imx8mqevk_defconfig

The resulting file of interest is output/images/bl31.bin

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 firmware/Kconfig            |   3 +++
 firmware/Makefile           |   2 ++
 firmware/imx/imx8m-bl31.bin | Bin 0 -> 46744 bytes
 3 files changed, 5 insertions(+)
 create mode 100755 firmware/imx/imx8m-bl31.bin

diff --git a/firmware/Kconfig b/firmware/Kconfig
index b6449644b..3c5f0c30e 100644
--- a/firmware/Kconfig
+++ b/firmware/Kconfig
@@ -7,4 +7,7 @@ config EXTRA_FIRMWARE_DIR
 config FIRMWARE_IMX_LPDDR4_PMU_TRAIN
        	bool
 
+config CONFIG_FIRMWARE_IMX8MQ_ATF
+        bool
+
 endmenu
diff --git a/firmware/Makefile b/firmware/Makefile
index c82e81ae4..62124933d 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -9,6 +9,8 @@ firmware-$(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) += \
 	imx/lpddr4_pmu_train_2d_dmem.bin \
 	imx/lpddr4_pmu_train_2d_imem.bin
 
+firmware-$(CONFIG_FIRMWARE_IMX8MQ_ATF) += imx/imx8m-bl31.bin
+
 # Create $(fwabs) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a
 # leading /, it's relative to $(srctree).
 fwdir := $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE_DIR))
diff --git a/firmware/imx/imx8m-bl31.bin b/firmware/imx/imx8m-bl31.bin
new file mode 100755
index 0000000000000000000000000000000000000000..b2310e4334c498686550a2ecab796ba905a13ebe
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z{MG!`{MG!`{MG!`{MG!`{MG!`{MG!`{MG!`{MG!`{MG!`{MG!`{MG!`{MG!`{MG!`
z{MG!`{MG!`{MGz5_-pXj;IE-ShyEP;bExl7-=V%keun%E`T6d?{0ICAZ_ayjo*Ug8
zovq`x?(?@F&$Zq^_vcX`__+Un#n1F+am?aa@C$yy&(1rGZx-KzU+@clc73zBXK^q1
z1;5~Dam?~D%g2IW@C$y3YlwG<Yw!Bs;Q=1u34Z*x#b;hF@Cx_hd4~shgeQ207kGvH
z@z8yT2Y7@hc!n2vh5PV*cz{QEf@gSvSGbdxoxJSi<qiLaf5YFO3%-AT!^wLJChsYj
zyr<v^|Ac?Sukb7U3je?N9Xvb!+40Ygf5E@tU+`=E8o$PG@EiOFUtb>is|ng~WuKM(
zRrXccPh}sK{Zm`te}(o**&k(Jl>JclL7D$$-j}-8S32f*nb&1Lmw8;~Z<)7czLxsd
zH#+8JnU7^2mibraU72rXp8e7XlRQo0oLuMRJn8=_k13BSk13BSk13BSk13BqC+Gy7
zpc8b0PS6QDK_^{jsz<6vsz<6vsz<6vsz<6v&<Q$0C+Gy7pc8b0PS8pDN_9<jO?6Fm
zO?6FmO?6Fm4LU(5=medh6Lf-3&<Q&Ew{H3)^+)QD)E}uoQh%iWNc|CXf=<v0IzcDs
T1f8H0bnadH=+w{g^6$?d>FQ|r

literal 0
HcmV?d00001

-- 
2.17.1


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[PATCH 08/11] ARM: nxp-imx8mq-evk: Add code to load ATF BL31 blob

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 3 +++
 arch/arm/mach-imx/Kconfig                 | 2 ++
 firmware/Kconfig                          | 2 +-
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index 1ed918ee0..c2dc6460a 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -23,6 +23,7 @@
 #include <asm/cache.h>
 #include <asm/sections.h>
 #include <asm/mmu.h>
+#include <mach/atf.h>
 
 #include "ddr.h"
 
@@ -75,6 +76,8 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
 	if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR)
 		nxp_imx8mq_evk_sram_setup();
 
+	imx8mq_atf_load_bl31(imx_imx8m_bl31_bin);
+
 	barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR,
 			  SZ_2G + SZ_1G, __dtb_imx8mq_evk_start);
 }
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a743bbfda..0086a7803 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -449,6 +449,8 @@ config MACH_NXP_IMX8MQ_EVK
 	bool "NXP i.MX8MQ EVK Board"
 	select ARCH_IMX8MQ
 	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MQ_ATF
+	select ARM_SMCCC
 
 endif
 
diff --git a/firmware/Kconfig b/firmware/Kconfig
index 3c5f0c30e..a6f79e8a9 100644
--- a/firmware/Kconfig
+++ b/firmware/Kconfig
@@ -7,7 +7,7 @@ config EXTRA_FIRMWARE_DIR
 config FIRMWARE_IMX_LPDDR4_PMU_TRAIN
        	bool
 
-config CONFIG_FIRMWARE_IMX8MQ_ATF
+config FIRMWARE_IMX8MQ_ATF
         bool
 
 endmenu
-- 
2.17.1


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[PATCH 09/11] ARM: i.MX8MQ: Query and display ATF fimware hash if availible

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/imx8mq.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
index dbcf4fa59..152f07bc1 100644
--- a/arch/arm/mach-imx/imx8mq.c
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -20,11 +20,16 @@
 #include <mach/revision.h>
 #include <mach/imx8mq-regs.h>
 
+#include <linux/arm-smccc.h>
+
 #define IMX8MQ_ROM_VERSION_A0	0x800
 #define IMX8MQ_ROM_VERSION_B0	0x83C
 
 #define MX8MQ_ANATOP_DIGPROG	0x6c
 
+#define FSL_SIP_BUILDINFO			0xC2000003
+#define FSL_SIP_BUILDINFO_GET_COMMITHASH	0x00
+
 static void imx8mq_silicon_revision(void)
 {
 	void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
@@ -81,7 +86,17 @@ core_initcall(imx8mq_init_syscnt_frequency);
 
 int imx8mq_init(void)
 {
+	struct arm_smccc_res res;
+
 	imx8mq_silicon_revision();
 
+	if (IS_ENABLED(CONFIG_ARM_SMCCC) &&
+	    IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) {
+		arm_smccc_smc(FSL_SIP_BUILDINFO,
+			      FSL_SIP_BUILDINFO_GET_COMMITHASH,
+			      0, 0, 0, 0, 0, 0, &res);
+		pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0);
+	}
+
 	return 0;
 }
-- 
2.17.1


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[PATCH 10/11] ARM: nxp-imx8mq-evk: Add bootflow comments

[Andrey Smirnov]

Add some notes on how the boot-flow goes while I still remember it.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 42 +++++++++++++++++++++--
 1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index c2dc6460a..7dd778c21 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -66,6 +66,26 @@ static void nxp_imx8mq_evk_sram_setup(void)
 	BUG_ON(ret);
 }
 
+/*
+ * Power-on execution flow of start_nxp_imx8mq_evk() might not be
+ * obvious for a very frist read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ *    executed for the first time
+ *
+ * 2. DDR is initialized and full i.MX image is loaded to the
+ *    beginning of RAM
+ *
+ * 3. start_nxp_imx8mq_evk, now in RAM, is executed again
+ *
+ * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
+ *
+ * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
+ *    executing start_nxp_imx8mq_evk() the third time
+ *
+ * 6. Standard barebox boot flow continues
+ */
 ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
@@ -73,11 +93,29 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR)
+	if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) {
+		/*
+		 * We assume that we were just loaded by MaskROM into
+		 * SRAM if we are not running from DDR. We also assume
+		 * that means DDR needs to be initialized for the
+		 * first time.
+		 */
 		nxp_imx8mq_evk_sram_setup();
-
+	}
+
+	/*
+	 * Straight from the power-on we are at EL3, so the following
+	 * code _will_ load and jump to ATF.
+	 *
+	 * However when this function is re-executed upon exit from
+	 * ATF's initialization routine, it is EL2 and it is
+	 * short-circuited to a no-op.
+	 */
 	imx8mq_atf_load_bl31(imx_imx8m_bl31_bin);
 
+	/*
+	 * Standard entry we hit once we initialized both DDR and ATF
+	 */
 	barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR,
 			  SZ_2G + SZ_1G, __dtb_imx8mq_evk_start);
 }
-- 
2.17.1


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[PATCH 11/11] firmware: Fix copy-paste comment mistake

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 firmware/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/firmware/Makefile b/firmware/Makefile
index 62124933d..7f4dc4932 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -57,6 +57,6 @@ endif
 targets := $(patsubst $(obj)/%,%, \
                                 $(shell find $(obj) -name \*.gen.S 2>/dev/null))
 
-# just to build a built-in.o. Otherwise compilation fails when no devicetree is
-# created.
+# just to build a built-in.o. Otherwise compilation fails when no
+# firmware is built.
 obj- += dummy.o
-- 
2.17.1


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Re: [PATCH 07/11] ARM: i.MX: fimware: Add pre-built BL31 ATF blob

[Sascha Hauer]

On Fri, Jun 29, 2018 at 08:48:56PM -0700, Andrey Smirnov wrote:
> Running Linux on i.MX8M requires us to use and proerly set up a ARM
> Trusted Firmware blob. For the sake of convenience, add a pre-built
> blob to our firmware tree, so it can be used by individual boards.
> 
> This blob was built using Buildroot:
> 
>  - commit: 6b02b8210acb18773f2c4b26cfc11d1f9bc4fb88
>  - defconig: freescale_imx8mqevk_defconfig
> 
> The resulting file of interest is output/images/bl31.bin
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  firmware/Kconfig            |   3 +++
>  firmware/Makefile           |   2 ++
>  firmware/imx/imx8m-bl31.bin | Bin 0 -> 46744 bytes
>  3 files changed, 5 insertions(+)
>  create mode 100755 firmware/imx/imx8m-bl31.bin
> 
> diff --git a/firmware/Kconfig b/firmware/Kconfig
> index b6449644b..3c5f0c30e 100644
> --- a/firmware/Kconfig
> +++ b/firmware/Kconfig
> @@ -7,4 +7,7 @@ config EXTRA_FIRMWARE_DIR
>  config FIRMWARE_IMX_LPDDR4_PMU_TRAIN
>         	bool
>  
> +config CONFIG_FIRMWARE_IMX8MQ_ATF
> +        bool

This superfluous CONFIG_ is added here and removed later.

Sascha


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Re: [PATCH 10/11] ARM: nxp-imx8mq-evk: Add bootflow comments

[Sascha Hauer]

On Fri, Jun 29, 2018 at 08:48:59PM -0700, Andrey Smirnov wrote:
> Add some notes on how the boot-flow goes while I still remember it.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 42 +++++++++++++++++++++--
>  1 file changed, 40 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
> index c2dc6460a..7dd778c21 100644
> --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
> +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
> @@ -66,6 +66,26 @@ static void nxp_imx8mq_evk_sram_setup(void)
>  	BUG_ON(ret);
>  }
>  
> +/*
> + * Power-on execution flow of start_nxp_imx8mq_evk() might not be
> + * obvious for a very frist read, so here's, hopefully helpful,
> + * summary:
> + *
> + * 1. MaskROM uploads PBL into OCRAM and that's where this function is
> + *    executed for the first time
> + *
> + * 2. DDR is initialized and full i.MX image is loaded to the
> + *    beginning of RAM
> + *
> + * 3. start_nxp_imx8mq_evk, now in RAM, is executed again
> + *
> + * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
> + *
> + * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
> + *    executing start_nxp_imx8mq_evk() the third time
> + *
> + * 6. Standard barebox boot flow continues
> + */
>  ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
>  {
>  	arm_cpu_lowlevel_init();
> @@ -73,11 +93,29 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
>  	if (IS_ENABLED(CONFIG_DEBUG_LL))
>  		setup_uart();
>  
> -	if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR)
> +	if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) {
> +		/*
> +		 * We assume that we were just loaded by MaskROM into
> +		 * SRAM if we are not running from DDR. We also assume
> +		 * that means DDR needs to be initialized for the
> +		 * first time.
> +		 */
>  		nxp_imx8mq_evk_sram_setup();
> -
> +	}
> +
> +	/*
> +	 * Straight from the power-on we are at EL3, so the following
> +	 * code _will_ load and jump to ATF.
> +	 *
> +	 * However when this function is re-executed upon exit from
> +	 * ATF's initialization routine, it is EL2 and it is
> +	 * short-circuited to a no-op.
> +	 */
>  	imx8mq_atf_load_bl31(imx_imx8m_bl31_bin);

Maybe the flow would be more clear if we add a if (current_el() == 3)
around the imx8mq_atf_load_bl31()

Sascha

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Pengutronix e.K.                           |                             |
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Re: [PATCH 06/11] ARM: i.MX: xload-esdhc: Allow patching first word of the image

[Sascha Hauer]

On Fri, Jun 29, 2018 at 08:48:55PM -0700, Andrey Smirnov wrote:
> Depending on how SD card/eMMC was programmed first byte of the image
> ther may or may not have appropriate branch instruction. Extend
> esdhc_start_image() to allow passing a custom callback that would
> patch the first instruction in memory to correctly redirect the CPU to
> the resto of the code.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/mach-imx/xload-esdhc.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
> index 98ebdfcf7..c017a8b10 100644
> --- a/arch/arm/mach-imx/xload-esdhc.c
> +++ b/arch/arm/mach-imx/xload-esdhc.c
> @@ -219,7 +219,8 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
>  }
>  
>  static int
> -esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset)
> +esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset,
> +		  u32 (*opcode_b)(u32))
>  {
>  	void *buf = (void *)address;
>  	u32 *ivt = buf + offset + SZ_1K;
> @@ -254,6 +255,9 @@ esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset)
>  
>  	bb = buf + ofs;
>  
> +	if (opcode_b)
> +		*(u32 *)buf = opcode_b(ofs);
> +

If I understand correctly this is to make sure that the bl31 binary
which jumps to MX8MQ_ATF_BL33_BASE_ADDR jumps over the imx header
to the barebox image, right?

Maybe we should memmove the barebox image to MX8MQ_ATF_BL33_BASE_ADDR
instead of inserting handweaved assembly into the binary.

Sascha

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Re: [PATCH 04/11] ARM: i.MX8MQ: Add a macro to load BL31 ATF blob

[Sascha Hauer]

On Fri, Jun 29, 2018 at 08:48:53PM -0700, Andrey Smirnov wrote:
> Add a macro containing all of the code needed to load and transfer
> control to BL31 ATF blob on i.MX8M.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/mach-imx/include/mach/atf.h | 63 ++++++++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 arch/arm/mach-imx/include/mach/atf.h
> 
> diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h
> new file mode 100644
> index 000000000..0b5018459
> --- /dev/null
> +++ b/arch/arm/mach-imx/include/mach/atf.h
> @@ -0,0 +1,63 @@
> +#ifndef __IMX_ATF_H__
> +#define __IMX_ATF_H__
> +
> +#include <asm/system.h>
> +
> +#define MX8MQ_ATF_BL31_SIZE_LIMIT	SZ_64K
> +#define MX8MQ_ATF_BL31_BASE_ADDR	0x00910000
> +#define MX8MQ_ATF_BL33_BASE_ADDR	0x40200000
> +
> +/**
> + * imx8mq_atf_load_bl31 - Load ATF BL31 blob and transfer contol to it
> + *
> + * @name:	Name of the BL31 blob
> + *
> + * This macro:
> +
> + *     1. Copies built-in BL31 blob to an address i.MX8M's BL31
> + *        expects to be placed
> + *
> + *     2. Sets up temporary stack pointer for EL2, which is execution
> + *        level that BL31 will drop us off at after it completes its
> + *        initialization routine
> + *
> + *     3. Transfers control to BL31
> + *
> + * NOTE: This has to be a macro in order delay the expansion of
> + * get_builtin_firmware(), otherwise it'll incorrectly interpret
> + * "name" literally

You show a good reason why we should add the firmware name strings
to the image along with a function that iterates over them. How
to add the firmware name strings is already provided in the Kernels
firmware/Makefile.

Sascha

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Re: [PATCH 02/11] ARM: Add code to support SMCCC on AArch64

[Sascha Hauer]

On Fri, Jun 29, 2018 at 08:48:51PM -0700, Andrey Smirnov wrote:
> Port SMCCC code from Linux kernel. To accomodate that:
> 
>   - Introduce CONFIG_ARM_SMCCC, to allow enabling the code
>     independent of CONFIG_ARM_SECURE_MONITOR
> 
>   - Bring <linux/arm-smccc.h> in
> 
>   - Add necessary constants to arch/arm/asm-offsets.c
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/Kconfig                   |   4 +
>  arch/arm/cpu/Makefile              |   4 +-
>  arch/arm/cpu/smccc-call_64.S       |  52 +++++++++++
>  arch/arm/include/asm/asm-offsets.h |   1 +
>  arch/arm/lib/asm-offsets.c         |   7 +-
>  include/linux/arm-smccc.h          | 135 +++++++++++++++++++++++++++++
>  6 files changed, 200 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/cpu/smccc-call_64.S
>  create mode 100644 arch/arm/include/asm/asm-offsets.h
>  create mode 100644 include/linux/arm-smccc.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 3555b4ee5..6f8eec708 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -388,7 +388,11 @@ config ARM_SEMIHOSTING
>  	  the data on the host computer connected to the target via
>  	  debugging channel (JTAG, SWD). If unsure say N
>  
> +config ARM_SMCCC
> +	bool
> +
>  config ARM_SECURE_MONITOR
> +        select ARM_SMCCC

Whitespaces instead of tab here.

Sascha

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Re: [PATCH 02/11] ARM: Add code to support SMCCC on AArch64

[Andrey Smirnov]

On Sun, Jul 1, 2018 at 11:26 PM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Fri, Jun 29, 2018 at 08:48:51PM -0700, Andrey Smirnov wrote:
> > Port SMCCC code from Linux kernel. To accomodate that:
> >
> >   - Introduce CONFIG_ARM_SMCCC, to allow enabling the code
> >     independent of CONFIG_ARM_SECURE_MONITOR
> >
> >   - Bring <linux/arm-smccc.h> in
> >
> >   - Add necessary constants to arch/arm/asm-offsets.c
> >
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > ---
> >  arch/arm/Kconfig                   |   4 +
> >  arch/arm/cpu/Makefile              |   4 +-
> >  arch/arm/cpu/smccc-call_64.S       |  52 +++++++++++
> >  arch/arm/include/asm/asm-offsets.h |   1 +
> >  arch/arm/lib/asm-offsets.c         |   7 +-
> >  include/linux/arm-smccc.h          | 135 +++++++++++++++++++++++++++++
> >  6 files changed, 200 insertions(+), 3 deletions(-)
> >  create mode 100644 arch/arm/cpu/smccc-call_64.S
> >  create mode 100644 arch/arm/include/asm/asm-offsets.h
> >  create mode 100644 include/linux/arm-smccc.h
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 3555b4ee5..6f8eec708 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -388,7 +388,11 @@ config ARM_SEMIHOSTING
> >         the data on the host computer connected to the target via
> >         debugging channel (JTAG, SWD). If unsure say N
> >
> > +config ARM_SMCCC
> > +     bool
> > +
> >  config ARM_SECURE_MONITOR
> > +        select ARM_SMCCC
>
> Whitespaces instead of tab here.
>

OK, will fix in v2.

Thanks,
Andrey Smirnov

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Re: [PATCH 04/11] ARM: i.MX8MQ: Add a macro to load BL31 ATF blob

[Andrey Smirnov]

On Sun, Jul 1, 2018 at 11:25 PM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Fri, Jun 29, 2018 at 08:48:53PM -0700, Andrey Smirnov wrote:
> > Add a macro containing all of the code needed to load and transfer
> > control to BL31 ATF blob on i.MX8M.
> >
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > ---
> >  arch/arm/mach-imx/include/mach/atf.h | 63 ++++++++++++++++++++++++++++
> >  1 file changed, 63 insertions(+)
> >  create mode 100644 arch/arm/mach-imx/include/mach/atf.h
> >
> > diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h
> > new file mode 100644
> > index 000000000..0b5018459
> > --- /dev/null
> > +++ b/arch/arm/mach-imx/include/mach/atf.h
> > @@ -0,0 +1,63 @@
> > +#ifndef __IMX_ATF_H__
> > +#define __IMX_ATF_H__
> > +
> > +#include <asm/system.h>
> > +
> > +#define MX8MQ_ATF_BL31_SIZE_LIMIT    SZ_64K
> > +#define MX8MQ_ATF_BL31_BASE_ADDR     0x00910000
> > +#define MX8MQ_ATF_BL33_BASE_ADDR     0x40200000
> > +
> > +/**
> > + * imx8mq_atf_load_bl31 - Load ATF BL31 blob and transfer contol to it
> > + *
> > + * @name:    Name of the BL31 blob
> > + *
> > + * This macro:
> > +
> > + *     1. Copies built-in BL31 blob to an address i.MX8M's BL31
> > + *        expects to be placed
> > + *
> > + *     2. Sets up temporary stack pointer for EL2, which is execution
> > + *        level that BL31 will drop us off at after it completes its
> > + *        initialization routine
> > + *
> > + *     3. Transfers control to BL31
> > + *
> > + * NOTE: This has to be a macro in order delay the expansion of
> > + * get_builtin_firmware(), otherwise it'll incorrectly interpret
> > + * "name" literally
>
> You show a good reason why we should add the firmware name strings
> to the image along with a function that iterates over them. How
> to add the firmware name strings is already provided in the Kernels
> firmware/Makefile.
>

OK, makes sense. I'll work on adding that feature as a part of v2.

Thanks,
Andrey Smirnov

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Re: [PATCH 07/11] ARM: i.MX: fimware: Add pre-built BL31 ATF blob

[Andrey Smirnov]

On Sun, Jul 1, 2018 at 10:23 PM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Fri, Jun 29, 2018 at 08:48:56PM -0700, Andrey Smirnov wrote:
> > Running Linux on i.MX8M requires us to use and proerly set up a ARM
> > Trusted Firmware blob. For the sake of convenience, add a pre-built
> > blob to our firmware tree, so it can be used by individual boards.
> >
> > This blob was built using Buildroot:
> >
> >  - commit: 6b02b8210acb18773f2c4b26cfc11d1f9bc4fb88
> >  - defconig: freescale_imx8mqevk_defconfig
> >
> > The resulting file of interest is output/images/bl31.bin
> >
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > ---
> >  firmware/Kconfig            |   3 +++
> >  firmware/Makefile           |   2 ++
> >  firmware/imx/imx8m-bl31.bin | Bin 0 -> 46744 bytes
> >  3 files changed, 5 insertions(+)
> >  create mode 100755 firmware/imx/imx8m-bl31.bin
> >
> > diff --git a/firmware/Kconfig b/firmware/Kconfig
> > index b6449644b..3c5f0c30e 100644
> > --- a/firmware/Kconfig
> > +++ b/firmware/Kconfig
> > @@ -7,4 +7,7 @@ config EXTRA_FIRMWARE_DIR
> >  config FIRMWARE_IMX_LPDDR4_PMU_TRAIN
> >               bool
> >
> > +config CONFIG_FIRMWARE_IMX8MQ_ATF
> > +        bool
>
> This superfluous CONFIG_ is added here and removed later.
>

Ugh. Missed this. Will fix in v2.

Thanks,
Andrey Smirnov

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Re: [PATCH 10/11] ARM: nxp-imx8mq-evk: Add bootflow comments

[Andrey Smirnov]

On Sun, Jul 1, 2018 at 10:48 PM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Fri, Jun 29, 2018 at 08:48:59PM -0700, Andrey Smirnov wrote:
> > Add some notes on how the boot-flow goes while I still remember it.
> >
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > ---
> >  arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 42 +++++++++++++++++++++--
> >  1 file changed, 40 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
> > index c2dc6460a..7dd778c21 100644
> > --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
> > +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
> > @@ -66,6 +66,26 @@ static void nxp_imx8mq_evk_sram_setup(void)
> >       BUG_ON(ret);
> >  }
> >
> > +/*
> > + * Power-on execution flow of start_nxp_imx8mq_evk() might not be
> > + * obvious for a very frist read, so here's, hopefully helpful,
> > + * summary:
> > + *
> > + * 1. MaskROM uploads PBL into OCRAM and that's where this function is
> > + *    executed for the first time
> > + *
> > + * 2. DDR is initialized and full i.MX image is loaded to the
> > + *    beginning of RAM
> > + *
> > + * 3. start_nxp_imx8mq_evk, now in RAM, is executed again
> > + *
> > + * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
> > + *
> > + * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
> > + *    executing start_nxp_imx8mq_evk() the third time
> > + *
> > + * 6. Standard barebox boot flow continues
> > + */
> >  ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
> >  {
> >       arm_cpu_lowlevel_init();
> > @@ -73,11 +93,29 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
> >       if (IS_ENABLED(CONFIG_DEBUG_LL))
> >               setup_uart();
> >
> > -     if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR)
> > +     if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) {
> > +             /*
> > +              * We assume that we were just loaded by MaskROM into
> > +              * SRAM if we are not running from DDR. We also assume
> > +              * that means DDR needs to be initialized for the
> > +              * first time.
> > +              */
> >               nxp_imx8mq_evk_sram_setup();
> > -
> > +     }
> > +
> > +     /*
> > +      * Straight from the power-on we are at EL3, so the following
> > +      * code _will_ load and jump to ATF.
> > +      *
> > +      * However when this function is re-executed upon exit from
> > +      * ATF's initialization routine, it is EL2 and it is
> > +      * short-circuited to a no-op.
> > +      */
> >       imx8mq_atf_load_bl31(imx_imx8m_bl31_bin);
>
> Maybe the flow would be more clear if we add a if (current_el() == 3)
> around the imx8mq_atf_load_bl31()
>

Yeah, I think so too. I'll make the change in v2.

Thanks,
Andrey Smirnov

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Re: [PATCH 06/11] ARM: i.MX: xload-esdhc: Allow patching first word of the image

[Andrey Smirnov]

On Sun, Jul 1, 2018 at 11:20 PM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Fri, Jun 29, 2018 at 08:48:55PM -0700, Andrey Smirnov wrote:
> > Depending on how SD card/eMMC was programmed first byte of the image
> > ther may or may not have appropriate branch instruction. Extend
> > esdhc_start_image() to allow passing a custom callback that would
> > patch the first instruction in memory to correctly redirect the CPU to
> > the resto of the code.
> >
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > ---
> >  arch/arm/mach-imx/xload-esdhc.c | 18 +++++++++++++++---
> >  1 file changed, 15 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
> > index 98ebdfcf7..c017a8b10 100644
> > --- a/arch/arm/mach-imx/xload-esdhc.c
> > +++ b/arch/arm/mach-imx/xload-esdhc.c
> > @@ -219,7 +219,8 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
> >  }
> >
> >  static int
> > -esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset)
> > +esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset,
> > +               u32 (*opcode_b)(u32))
> >  {
> >       void *buf = (void *)address;
> >       u32 *ivt = buf + offset + SZ_1K;
> > @@ -254,6 +255,9 @@ esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset)
> >
> >       bb = buf + ofs;
> >
> > +     if (opcode_b)
> > +             *(u32 *)buf = opcode_b(ofs);
> > +
>
> If I understand correctly this is to make sure that the bl31 binary
> which jumps to MX8MQ_ATF_BL33_BASE_ADDR jumps over the imx header
> to the barebox image, right?
>

That's right.

> Maybe we should memmove the barebox image to MX8MQ_ATF_BL33_BASE_ADDR
> instead of inserting handweaved assembly into the binary.
>

Yeah good point, I haven't thought about that. We definitely should be
able to do this. But now that I think of it, it should be possible to
make second esdhc_read_blocks() call such that the image is placed the
way we want it without extra memmove(). I'll give both a try and will
update in v2 according to the results.

Thanks,
Andrey Smirnov.

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Re: [PATCH 04/11] ARM: i.MX8MQ: Add a macro to load BL31 ATF blob

[Andrey Smirnov]

On Tue, Jul 3, 2018 at 10:58 AM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
> On Sun, Jul 1, 2018 at 11:25 PM Sascha Hauer <s.hauer@pengutronix.de> wrote:
> >
> > On Fri, Jun 29, 2018 at 08:48:53PM -0700, Andrey Smirnov wrote:
> > > Add a macro containing all of the code needed to load and transfer
> > > control to BL31 ATF blob on i.MX8M.
> > >
> > > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > > ---
> > >  arch/arm/mach-imx/include/mach/atf.h | 63 ++++++++++++++++++++++++++++
> > >  1 file changed, 63 insertions(+)
> > >  create mode 100644 arch/arm/mach-imx/include/mach/atf.h
> > >
> > > diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h
> > > new file mode 100644
> > > index 000000000..0b5018459
> > > --- /dev/null
> > > +++ b/arch/arm/mach-imx/include/mach/atf.h
> > > @@ -0,0 +1,63 @@
> > > +#ifndef __IMX_ATF_H__
> > > +#define __IMX_ATF_H__
> > > +
> > > +#include <asm/system.h>
> > > +
> > > +#define MX8MQ_ATF_BL31_SIZE_LIMIT    SZ_64K
> > > +#define MX8MQ_ATF_BL31_BASE_ADDR     0x00910000
> > > +#define MX8MQ_ATF_BL33_BASE_ADDR     0x40200000
> > > +
> > > +/**
> > > + * imx8mq_atf_load_bl31 - Load ATF BL31 blob and transfer contol to it
> > > + *
> > > + * @name:    Name of the BL31 blob
> > > + *
> > > + * This macro:
> > > +
> > > + *     1. Copies built-in BL31 blob to an address i.MX8M's BL31
> > > + *        expects to be placed
> > > + *
> > > + *     2. Sets up temporary stack pointer for EL2, which is execution
> > > + *        level that BL31 will drop us off at after it completes its
> > > + *        initialization routine
> > > + *
> > > + *     3. Transfers control to BL31
> > > + *
> > > + * NOTE: This has to be a macro in order delay the expansion of
> > > + * get_builtin_firmware(), otherwise it'll incorrectly interpret
> > > + * "name" literally
> >
> > You show a good reason why we should add the firmware name strings
> > to the image along with a function that iterates over them. How
> > to add the firmware name strings is already provided in the Kernels
> > firmware/Makefile.
> >
>
> OK, makes sense. I'll work on adding that feature as a part of v2.
>

Hmm, I just realized two things:

    - Implementing that besides porting a bunch of code would require
early relocation, which I really would like to avoid

    - We can convert imx8mq_atf_load_bl31() into a function if we
change its signature to accept a blob pointer and blob size. And leave
it up to the user as to how that blob is obtained.

Given the first and simplicity of the second, I think I am going to go
that way for v2.

Thanks,
Andrey Smirnov

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