From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: "Yazdani, Reyhaneh" <RYazdani@data-modul.com>
Cc: "barebox@lists.infradead.org" <barebox@lists.infradead.org>
Subject: Re: Bringup Barebox on imx8mm
Date: Fri, 14 Jun 2019 00:11:20 -0700 [thread overview]
Message-ID: <CAHQ1cqHAz=ZAbUvThUOo8WcB74CgnoWdSgAEOTy_94TE81zwfQ@mail.gmail.com> (raw)
In-Reply-To: <c0432719-ac26-629d-01a0-bcf4106f8357@data-modul.com>
On Thu, Jun 13, 2019 at 8:14 AM Yazdani, Reyhaneh
<RYazdani@data-modul.com> wrote:
>
> Hello Everyone,
>
> I am trying to bringup Barebox on i.MX8MM-evk.
>
> I have followed all the commits related to the i.MX8MQ and added proper files
> and changes for i.MX8MM-evk board.
>
> The problem is Barebox stops at "ddrc_phy_wait_training_complete" function,
> exactly at sub-function "ddrc_phy_get_message". The read-value from the
>
> phy + DDRC_PHY_REG(0xd0004) is not correct, and it remains in while loop.
>
> I used the ddr_init and ddrphy_train files produced from mscale_ddr_tool of NXP,
> and even compared with the value from U-boot. All are similar.
>
> Does any body have an idea what would be the problem?
>
What about DDR PHY firmware? Is it the same as in working U-boot
image? From what you describe it sounds that DDR PHY is not
responding, so I am wondering if DDR firmware is running. Also, did
you check that various memory offsets in, say
arch/arm/mach-imx/include/mach/imx8-ddrc.h are valid for i.MX8MM and
are not values that MQ specific? Another thing to debug this would be
to trace all of the register reads/writes in working U-Boot vs Barebox
and see what the difference is.
Anyway, just my 2 cents.
Thanks,
Andrey Smirnov
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next prev parent reply other threads:[~2019-06-14 7:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-13 15:14 Yazdani, Reyhaneh
2019-06-14 7:11 ` Andrey Smirnov [this message]
2019-06-17 8:17 ` Yazdani, Reyhaneh
2019-06-25 9:12 ` Yazdani, Reyhaneh
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