Bringup Barebox on imx8mm

Bringup Barebox on imx8mm

[Yazdani, Reyhaneh]

Hello Everyone,

I am trying to bringup Barebox on i.MX8MM-evk.

I have followed all the commits related to the i.MX8MQ and added proper files
and changes for i.MX8MM-evk board.

The problem is Barebox stops at "ddrc_phy_wait_training_complete" function,
exactly at sub-function "ddrc_phy_get_message". The read-value from the

phy + DDRC_PHY_REG(0xd0004) is not correct, and it remains in while loop.

I used the ddr_init and ddrphy_train files produced from mscale_ddr_tool of NXP,
and even compared with the value from U-boot. All are similar.

Does any body have an idea what would be the problem?

Thanks

Reyhaneh

--
Reyhaneh Yazdani
Data Modul AG                            TEL:    +49-89-56017-154
Embedded development                 FAX:    +49-89-56017-119
Linux - Development                      RG: HR-Muenchen B-85591
Landsberger Str. 322 D-80687 Muenchen - http://www.data-modul.com

Vertrauliche E-Mail von / Confidential e-mail from: DATA MODUL AG
Vorstand / CEO: Dr. Florian Pesahl
Vorsitzende des Aufsichtsrates / Chairwoman of the Supervisory Board: Kristin D. Russell
Sitz der Gesellschaft / Registered Office: München
Registergericht / Registration Court: München Handelsregister B 85 591



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Re: Bringup Barebox on imx8mm

[Andrey Smirnov]

On Thu, Jun 13, 2019 at 8:14 AM Yazdani, Reyhaneh
<RYazdani@data-modul.com> wrote:
>
> Hello Everyone,
>
> I am trying to bringup Barebox on i.MX8MM-evk.
>
> I have followed all the commits related to the i.MX8MQ and added proper files
> and changes for i.MX8MM-evk board.
>
> The problem is Barebox stops at "ddrc_phy_wait_training_complete" function,
> exactly at sub-function "ddrc_phy_get_message". The read-value from the
>
> phy + DDRC_PHY_REG(0xd0004) is not correct, and it remains in while loop.
>
> I used the ddr_init and ddrphy_train files produced from mscale_ddr_tool of NXP,
> and even compared with the value from U-boot. All are similar.
>
> Does any body have an idea what would be the problem?
>

What about DDR PHY firmware? Is it the same as in working U-boot
image? From what you describe it sounds that DDR PHY is not
responding, so I am wondering if DDR firmware is running. Also, did
you check that various memory offsets in, say
arch/arm/mach-imx/include/mach/imx8-ddrc.h are valid for i.MX8MM and
are not values that MQ specific? Another thing to debug this would be
to trace all of the register reads/writes in working U-Boot vs Barebox
and see what the difference is.

Anyway, just my 2 cents.

Thanks,
Andrey Smirnov

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Re: Bringup Barebox on imx8mm

[Yazdani, Reyhaneh]

On 6/14/19 9:11 AM, Andrey Smirnov wrote:
> On Thu, Jun 13, 2019 at 8:14 AM Yazdani, Reyhaneh
> <RYazdani@data-modul.com> wrote:
>>
>> Hello Everyone,
>>
>> I am trying to bringup Barebox on i.MX8MM-evk.
>>
>> I have followed all the commits related to the i.MX8MQ and added proper files
>> and changes for i.MX8MM-evk board.
>>
>> The problem is Barebox stops at "ddrc_phy_wait_training_complete" function,
>> exactly at sub-function "ddrc_phy_get_message". The read-value from the
>>
>> phy + DDRC_PHY_REG(0xd0004) is not correct, and it remains in while loop.
>>
>> I used the ddr_init and ddrphy_train files produced from mscale_ddr_tool of NXP,
>> and even compared with the value from U-boot. All are similar.
>>
>> Does any body have an idea what would be the problem?
>>
>
> What about DDR PHY firmware? Is it the same as in working U-boot
> image? From what you describe it sounds that DDR PHY is not
> responding, so I am wondering if DDR firmware is running. Also, did
> you check that various memory offsets in, say
> arch/arm/mach-imx/include/mach/imx8-ddrc.h are valid for i.MX8MM and
> are not values that MQ specific? Another thing to debug this would be
> to trace all of the register reads/writes in working U-Boot vs Barebox
> and see what the difference is.
>
> Anyway, just my 2 cents.
>
> Thanks,
> Andrey Smirnov
>

Thanks Andrey.

I have read back all the DDR init writes and I am wonder the problem is related
to when the DDRC config starts (even before loading the Firmware). It seems DDRC
configuration is not applied, while when I read back the registers, the values
are all identical and not the one should be.

The point is, I still cannot find which configuration should be applied before
starting DDRC configuration. I have traced all registers r/w in Barebox and
U-boot, but no success.

Best,
Reyhaneh



--
Reyhaneh Yazdani
Data Modul AG                            TEL:    +49-89-56017-154
Embedded development                 FAX:    +49-89-56017-119
Linux - Development                      RG: HR-Muenchen B-85591
Landsberger Str. 322 D-80687 Muenchen - http://www.data-modul.com

Vertrauliche E-Mail von / Confidential e-mail from: DATA MODUL AG
Vorstand / CEO: Dr. Florian Pesahl
Vorsitzende des Aufsichtsrates / Chairwoman of the Supervisory Board: Kristin D. Russell
Sitz der Gesellschaft / Registered Office: München
Registergericht / Registration Court: München Handelsregister B 85 591



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Re: Bringup Barebox on imx8mm

[Yazdani, Reyhaneh]

Hello,

The issue is resolved. It was related to the DDR clock init. It was necessary to
initialize the DDR clock before starting ddr_init():


/* DDR clock init*/
writel( 0x3, 0x30384058);
writel(0x11000000, 0x3038a000);
writel(0x11000000,0x3038a080);
writel(0x3, 0x30384054);

Best,
Reyhaneh

On 6/14/19 9:11 AM, Andrey Smirnov wrote:
> On Thu, Jun 13, 2019 at 8:14 AM Yazdani, Reyhaneh
> <RYazdani@data-modul.com> wrote:
>>
>> Hello Everyone,
>>
>> I am trying to bringup Barebox on i.MX8MM-evk.
>>
>> I have followed all the commits related to the i.MX8MQ and added proper files
>> and changes for i.MX8MM-evk board.
>>
>> The problem is Barebox stops at "ddrc_phy_wait_training_complete" function,
>> exactly at sub-function "ddrc_phy_get_message". The read-value from the
>>
>> phy + DDRC_PHY_REG(0xd0004) is not correct, and it remains in while loop.
>>
>> I used the ddr_init and ddrphy_train files produced from mscale_ddr_tool of NXP,
>> and even compared with the value from U-boot. All are similar.
>>
>> Does any body have an idea what would be the problem?
>>
>
> What about DDR PHY firmware? Is it the same as in working U-boot
> image? From what you describe it sounds that DDR PHY is not
> responding, so I am wondering if DDR firmware is running. Also, did
> you check that various memory offsets in, say
> arch/arm/mach-imx/include/mach/imx8-ddrc.h are valid for i.MX8MM and
> are not values that MQ specific? Another thing to debug this would be
> to trace all of the register reads/writes in working U-Boot vs Barebox
> and see what the difference is.
>
> Anyway, just my 2 cents.
>
> Thanks,
> Andrey Smirnov
>

--
Reyhaneh Yazdani
Data Modul AG                            TEL:    +49-89-56017-154
Embedded development                 FAX:    +49-89-56017-119
Linux - Development                      RG: HR-Muenchen B-85591
Landsberger Str. 322 D-80687 Muenchen - http://www.data-modul.com

Vertrauliche E-Mail von / Confidential e-mail from: DATA MODUL AG
Vorstand / CEO: Dr. Florian Pesahl
Vorsitzende des Aufsichtsrates / Chairwoman of the Supervisory Board: Kristin D. Russell
Sitz der Gesellschaft / Registered Office: München
Registergericht / Registration Court: München Handelsregister B 85 591



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