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AJvYcCUzM0LlV4iug//u6d41niF9eHLAhbr7Ua5Fhy4jZZspX31/RlD51BQpfJoNR7p8aHWMuK4fTRU5@lists.infradead.org X-Gm-Message-State: AOJu0Yz2zB+TmrN/r2N0nkqxG4iY6iwW7WtG+aHrQID68Oo4dMLoeczn jOZY5Vf1cvBTsXS+QXHi+TVfCaHkkUzWEpZHZ7KYZpb1AbaQwKTTpgCJXZsgmu74M690tNwMzVX gzR1jWeE0yNN6BtO+0PnzrrupSENuWM4BhIOZAtgHow== X-Gm-Gg: ASbGncvwndMOBljesP9OnNG6J+tpl/Rrn5V53H7tgnkFaD682x8pjFmkSdnD6qELQr2 EJIfb053qu+KSAB4d0jDTle7M7EnMZPkAnRGAvR5UNfKA8AVUOcD+4vjJMYsFVr+tfrl8GIaHEj /zHWmtWMw0oSKfaeQMirTYcAoDsrUJdlIYaH4ukDHQxickRTxyRoRYTT6gNwGMr/+pNLsnm+J0I XfR X-Google-Smtp-Source: AGHT+IElUB7nGZyYz3NfcN+wY7u5wUFXf/xFt8Db+0w3haR1EZxWm8N4fYvCuSRCHo4rP28BTf0rnwmsaV1pyjFTOII= X-Received: by 2002:a17:907:728d:b0:adb:335b:decb with SMTP id a640c23a62f3a-addf8d1d6c5mr187252566b.24.1749031054894; Wed, 04 Jun 2025 02:57:34 -0700 (PDT) MIME-Version: 1.0 References: <20250603092044.1464440-1-f.pflug@pengutronix.de> <20250603092044.1464440-2-f.pflug@pengutronix.de> <569963942cf35755dfdf34b240c350986fda4727.camel@pengutronix.de> <6ce5c98c-4f8e-46f6-8dd3-7c911578feb8@pengutronix.de> <47261d55d72a6f34618ca9d4b86214f306a91f5a.camel@pengutronix.de> In-Reply-To: From: Rouven Czerwinski Date: Wed, 4 Jun 2025 11:57:22 +0200 X-Gm-Features: AX0GCFvNbKq3wZyyz3uyLQEbgn8r4GB70O6A623YaYdCgs-XUihohuWocMz1mTM Message-ID: To: Lucas Stach Cc: Ahmad Fatoum , Fabian Pflug , barebox@lists.infradead.org Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250604_025737_384373_1259BD63 X-CRM114-Status: GOOD ( 26.68 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.9 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH 2/2] ARM: optee-early: invalidate caches before jump to OP-TEE X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Hi, On Tue, 3 Jun 2025 at 17:20, Lucas Stach wrote: > > Am Dienstag, dem 03.06.2025 um 16:51 +0200 schrieb Ahmad Fatoum: > [...] > > > > > I guess it would be much better to simply have the > > > > > arm_early_mmu_cache_invalidate() as part of the Cortex A9 lowlevel CPU > > > > > initialization at the very start of the PBL entry. To add my few cents: I have had customer systems where without cache invalidation, imx-usb-loader would sporadically hang. This hang was fixed by calling arm_early_mmu_cache_invalidate() in the lowlevel pbl code as well. Barebox already has i.MX6 boards which to call the invalidation early in PBL, but unfortunately none have a comment or commit description why. > > > > > > > > We don't have a dedicated Cortex-A9 lowlevel entry function > > > > unfortunately, just some for specific processors, e.g. the > > > > imx6_cpu_lowlevel_init. > > > > > > > > We could add CONFIG_CPU_CORTEX_A9, select it from the relevant SoC > > > > options and depending on it, add the invalidation to > > > > arm_cpu_lowlevel_init()? What do you think? > > > > > > > This would then trigger the invalidation even on systems that don't > > > need it in case of a multiarch Barebox. There aren't that many Cortex > > > A9 based SoCs supported in Barebox and all of them should have a SoC > > > specific init function to apply the necessary workarounds, so I think > > > it would be fine to call the cache invalidate from the SoC specific > > > lowlevel init of those few SoCs? > > > > Fair enough. How do we know we only need this for Cortex-A9 though? > > Couldn't e.g. the Cortex-A8 also be affected? > > We can't be 100% sure without specific knowledge about each SoC > integration. Both the Cortex A8 [1] and Cortex A15 [2] TRMs define a > reset sequence that mandates the straps to be set in such a way that > the processor will clear all L1 and L2 memory arrays on power-on reset. > > The only odd one where the TRM doesn't even mention memory arrays in > the reset sequence is the Cortex A9 [3], which pretty much lines up > with the number of SoCs where we have seen issues due to uninitialized > cache content. > > Regards, > Lucas > > [1] https://developer.arm.com/documentation/ddi0344/k/Cihcbcgi > [2] https://developer.arm.com/documentation/ddi0438/i/functional-description/clocking-and-resets/resets > [3] https://developer.arm.com/documentation/100511/0401/functional-description/clocking-and-resets/reset Adding this to imx6_cpu_lowlevel_init() is IMO the correct way as well. - Rouven