Configure RAM size on iMX53 board

Configure RAM size on iMX53 board

[Jose Luis Zabalza]

Hello everybody

I have two iMX53 custom boards. They are the same board but 512MB vs
1GB RAM version.  Both boards are working with the same Uboot binary
but I would like use Barebox.

I have to be able to run Barebox on 1GB version but the same Barebox
binary don't work on 512MB version.

I use imx-usb-loader to put Barebox on the board. On 1GB version
Barebox are working OK and load Linux kernel successfully. On 512MB
Barebox are loaded successfully but don't work. lsusb tell me the
board is working on Serial Download mode yet. No message is printed on
the console.

Do I have to set Barebox for work with different RAM size?

Thanks in advance.

P.D. I don't use (yet) device tree with Barebox. The DCD table are the
same on both board.


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Re: Configure RAM size on iMX53 board

[Andrey Smirnov]

On Thu, Nov 3, 2016 at 1:30 PM, Jose Luis Zabalza <jlz.3008@gmail.com> wrote:
> Hello everybody
>
> I have two iMX53 custom boards. They are the same board but 512MB vs
> 1GB RAM version.  Both boards are working with the same Uboot binary
> but I would like use Barebox.
>
> I have to be able to run Barebox on 1GB version but the same Barebox
> binary don't work on 512MB version.
>
> I use imx-usb-loader to put Barebox on the board. On 1GB version
> Barebox are working OK and load Linux kernel successfully. On 512MB
> Barebox are loaded successfully but don't work. lsusb tell me the
> board is working on Serial Download mode yet. No message is printed on
> the console.
>
> Do I have to set Barebox for work with different RAM size?
>

One of the first things Barebox does when it start is placing itself
at the end of RAM as well as reserving adjacent areas for stack and
heap. So while you don't strictly have to configure it for different
RAM sizes it _does_ need to know actual RAM size to be able to
calculate various addresses correctly.

To the best of my knowledge there are two ways that knowledge is passed along:

     1) Hardcore that knowledge in entry point code as a part of PBL
     2) Implement additional memory size detection logic

AFAIK all i.MX variants in latest master should fall under second
category, so different RAM sizes should be accounted for.

You might gain some additional insight into the problem if you enable
CONFIG_DEBUG_LL (and route it to appropriate port) in "Debugging" menu
of menuconfig.

Hope this helps.

Regards,
Andrey Smirnov

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Re: Configure RAM size on iMX53 board

[Sascha Hauer]

Hi,

On Thu, Nov 03, 2016 at 09:30:03PM +0100, Jose Luis Zabalza wrote:
> Hello everybody
> 
> I have two iMX53 custom boards. They are the same board but 512MB vs
> 1GB RAM version.  Both boards are working with the same Uboot binary
> but I would like use Barebox.
> 
> I have to be able to run Barebox on 1GB version but the same Barebox
> binary don't work on 512MB version.
> 
> I use imx-usb-loader to put Barebox on the board. On 1GB version
> Barebox are working OK and load Linux kernel successfully. On 512MB
> Barebox are loaded successfully but don't work. lsusb tell me the
> board is working on Serial Download mode yet. No message is printed on
> the console.
> 
> Do I have to set Barebox for work with different RAM size?

Just like Andrey already said, barebox detects the RAM size by reading
back the values from the SDRAM controller to determine its memory
layout, so the configured values must be correct. In your case they can
only be correct for the 1GB version.

What you can do in this case is:

- in your boards lowlevel.c detect your actual RAM size by testing for
  mirrors in the SDRAM Address space.
- Instead of imx53_barebox_entry() call barebox_arm_entry() with the
  actual RAM size.

This should already bring you through the lowlevel setup succesfully.

Then in your board file add this:

#include <mach/esdctl.h>

static int myboard_init(void)
{
	imx_esdctl_disable();

	arm_add_mem_device("ram0", MX53_CSD0_BASE_ADDR, size);

	return 0;
}
core_initcall(myboard_init);

Note you can't use a variable to safe the calculated SDRAM size from
lowlevel.c to your board file. It's probably best to do the same test
again.

Sascha

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Re: Configure RAM size on iMX53 board

[Jose Luis Zabalza]

Thanks Sascha, but something I do wrong

I tried set fixed size to 512M, but neither works.

With these changes does not work or 512MB board  or 1GB board.

=========<cut lowlevel.c>===============

#include <common.h>
#include <mach/imx53-regs.h>
#include <mach/esdctl.h>
#include <mach/generic.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>

void __naked barebox_arm_reset_vector(void)
{
    imx5_cpu_lowlevel_init();
    arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
//    imx53_barebox_entry(NULL);
    barebox_arm_entry(MX53_CSD0_BASE_ADDR,SZ_512M,NULL);
}
=========================================

==========<cut board.c>==================
#include <common.h>
#include <environment.h>
#include <fcntl.h>
#include <platform_data/eth-fec.h>
#include <fs.h>
#include <init.h>
#include <nand.h>
#include <net.h>
#include <partition.h>
#include <linux/sizes.h>
#include <gpio.h>
#include <mci.h>

#include <generated/mach-types.h>

#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
#include <mach/imx-nand.h>
#include <mach/iim.h>
#include <mach/imx5.h>
#include <mach/esdctl.h>

#include <asm/armlinux.h>
#include <io.h>
#include <asm/mmu.h>

........ other device init functions ......

static int myboard_init(void)
{
        imx_esdctl_disable();

        arm_add_mem_device("ram0", MX53_CSD0_BASE_ADDR, SZ_512M);

        return 0;
}
core_initcall(myboard_init);
========================================

Thanks in advanced.

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Re: Configure RAM size on iMX53 board

[Sascha Hauer]

On Sat, Nov 05, 2016 at 07:39:53AM +0100, Jose Luis Zabalza wrote:
> Thanks Sascha, but something I do wrong
> 
> I tried set fixed size to 512M, but neither works.
> 
> With these changes does not work or 512MB board  or 1GB board.
> 
> =========<cut lowlevel.c>===============
> 
> #include <common.h>
> #include <mach/imx53-regs.h>
> #include <mach/esdctl.h>
> #include <mach/generic.h>
> #include <asm/barebox-arm-head.h>
> #include <asm/barebox-arm.h>
> 
> void __naked barebox_arm_reset_vector(void)
> {
>     imx5_cpu_lowlevel_init();
>     arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
> //    imx53_barebox_entry(NULL);
>     barebox_arm_entry(MX53_CSD0_BASE_ADDR,SZ_512M,NULL);
> }

Hm, it should work like this, but maybe the memory layout is not what we
expect. Could you apply the following and see what we get for both
memory variants (still using imx53_barebox_entry() above so that you
actually get to that point)?

Sascha

--------------------------------8<--------------------------------------

From c3024dcd0e9c494adeb3f9ffbb6ec41ee4787b2d Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Mon, 7 Nov 2016 08:41:01 +0100
Subject: [PATCH] ARM: i.MX53: Add some memory debug

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/esdctl.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 106e648..d217495 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -276,6 +276,9 @@ static void imx_esdctl_v3_add_mem(void *esdctlbase, struct imx_esdctl_data *data
 
 static void imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
 {
+	printf("CS0: 0x%08lx\n", imx_v4_sdram_size(esdctlbase, 0));
+	printf("CS1: 0x%08lx\n", imx_v4_sdram_size(esdctlbase, 1));
+
 	add_mem(data->base0, imx_v4_sdram_size(esdctlbase, 0),
 			data->base1, imx_v4_sdram_size(esdctlbase, 1));
 }
-- 
2.10.1

-- 
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Re: Configure RAM size on iMX53 board

[Jose Luis Zabalza]

Thanks Sascha

RAM memory reference is MT41K128M16JT-125 XIT
https://www.micron.com/parts/dram/ddr3-sdram/mt41k128m16jt-125-xit

================<cut>=========================
barebox 2016.09.0-00071-ga38b701-dirty #11 Tue Nov 8 05:56:31 CET 2016


Board: MyBoard i.MX53
detected i.MX53 revision 2.1
CS0: 0x20000000
CS1: 0x20000000
...

================<cut>=========================




2016-11-07 8:43 GMT+01:00 Sascha Hauer <s.hauer@pengutronix.de>:
> On Sat, Nov 05, 2016 at 07:39:53AM +0100, Jose Luis Zabalza wrote:
>> Thanks Sascha, but something I do wrong
>>
>> I tried set fixed size to 512M, but neither works.
>>
>> With these changes does not work or 512MB board  or 1GB board.
>>
>> =========<cut lowlevel.c>===============
>>
>> #include <common.h>
>> #include <mach/imx53-regs.h>
>> #include <mach/esdctl.h>
>> #include <mach/generic.h>
>> #include <asm/barebox-arm-head.h>
>> #include <asm/barebox-arm.h>
>>
>> void __naked barebox_arm_reset_vector(void)
>> {
>>     imx5_cpu_lowlevel_init();
>>     arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
>> //    imx53_barebox_entry(NULL);
>>     barebox_arm_entry(MX53_CSD0_BASE_ADDR,SZ_512M,NULL);
>> }
>
> Hm, it should work like this, but maybe the memory layout is not what we
> expect. Could you apply the following and see what we get for both
> memory variants (still using imx53_barebox_entry() above so that you
> actually get to that point)?
>
> Sascha
>
> --------------------------------8<--------------------------------------
>
> From c3024dcd0e9c494adeb3f9ffbb6ec41ee4787b2d Mon Sep 17 00:00:00 2001
> From: Sascha Hauer <s.hauer@pengutronix.de>
> Date: Mon, 7 Nov 2016 08:41:01 +0100
> Subject: [PATCH] ARM: i.MX53: Add some memory debug
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-imx/esdctl.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> index 106e648..d217495 100644
> --- a/arch/arm/mach-imx/esdctl.c
> +++ b/arch/arm/mach-imx/esdctl.c
> @@ -276,6 +276,9 @@ static void imx_esdctl_v3_add_mem(void *esdctlbase, struct imx_esdctl_data *data
>
>  static void imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
>  {
> +       printf("CS0: 0x%08lx\n", imx_v4_sdram_size(esdctlbase, 0));
> +       printf("CS1: 0x%08lx\n", imx_v4_sdram_size(esdctlbase, 1));
> +
>         add_mem(data->base0, imx_v4_sdram_size(esdctlbase, 0),
>                         data->base1, imx_v4_sdram_size(esdctlbase, 1));
>  }
> --
> 2.10.1
>
> --
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



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Re: Configure RAM size on iMX53 board

[Sascha Hauer]

On Tue, Nov 08, 2016 at 06:09:52AM +0100, Jose Luis Zabalza wrote:
> Thanks Sascha
> 
> RAM memory reference is MT41K128M16JT-125 XIT
> https://www.micron.com/parts/dram/ddr3-sdram/mt41k128m16jt-125-xit
> 
> ================<cut>=========================
> barebox 2016.09.0-00071-ga38b701-dirty #11 Tue Nov 8 05:56:31 CET 2016
> 
> 
> Board: MyBoard i.MX53
> detected i.MX53 revision 2.1
> CS0: 0x20000000
> CS1: 0x20000000
> ...
> 
> ================<cut>=========================

So you have 512MiB on each chip select, so I assume that on the 512MiB
board variants CS1 is not equipped. In that case you can in lowlevel.c
test if you find SDRAM on CS1 and if not, disable the chip select
completely in the SDRAM controller.
I am not sure how you can detect if there's SDRAM on CS1. I've seen
situations in which the board just hangs if you access non existent RAM
areas.

Sascha


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Re: Configure RAM size on iMX53 board

[Jose Luis Zabalza]

> So you have 512MiB on each chip select, so I assume that on the 512MiB
> board variants CS1 is not equipped.

Yes, it is.

>In that case you can in lowlevel.c
> test if you find SDRAM on CS1 and if not, disable the chip select
> completely in the SDRAM controller.

OK. But how ? I enable CS0 and CS1 on DCD table. Is there any way to
tell barebox not to use CS1 ?

> I am not sure how you can detect if there's SDRAM on CS1. I've seen
> situations in which the board just hangs if you access non existent RAM
> areas.

I have tried it, but I have not be able to implement a code for
autodetect. If the code write or read a value on a position without
physical  chip, the microcontroller hangs. ????

But it's not a problem. A solution is configure both CS and MMU. If
bootloader don't access to high positions, there is not problem. After
I set a environment variable with memory size and the mem kernel
parameter (or ATAG) does the rest.

So, I have to make sure Barebox don't reach CS1 memory positions. That is all.

Thanks for your help. See you later.


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Re: Configure RAM size on iMX53 board

[Sascha Hauer]

On Tue, Nov 08, 2016 at 09:51:36PM +0100, Jose Luis Zabalza wrote:
> > So you have 512MiB on each chip select, so I assume that on the 512MiB
> > board variants CS1 is not equipped.
> 
> Yes, it is.
> 
> >In that case you can in lowlevel.c
> > test if you find SDRAM on CS1 and if not, disable the chip select
> > completely in the SDRAM controller.
> 
> OK. But how ? I enable CS0 and CS1 on DCD table. Is there any way to
> tell barebox not to use CS1 ?
> 
> > I am not sure how you can detect if there's SDRAM on CS1. I've seen
> > situations in which the board just hangs if you access non existent RAM
> > areas.
> 
> I have tried it, but I have not be able to implement a code for
> autodetect. If the code write or read a value on a position without
> physical  chip, the microcontroller hangs. ????
> 
> But it's not a problem. A solution is configure both CS and MMU. If
> bootloader don't access to high positions, there is not problem. After
> I set a environment variable with memory size and the mem kernel
> parameter (or ATAG) does the rest.

You said that both board variants work with the same U-Boot binary, how
does it work there? Is there some detection mechanism or is it only some
environment variable that you have to set manually?

Sascha

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Re: Configure RAM size on iMX53 board

[Jose Luis Zabalza]

There is no form of detection. UBoot (a very old version) don't use
any CS1 address, except with the memtest command.
If memtest command is executed with 512MB version, UBoot hangs, as expected.
I set the mem kernel parameter using a environment variable and kernel
can reach CS1 memory.


2016-11-08 22:24 GMT+01:00 Sascha Hauer <s.hauer@pengutronix.de>:
> On Tue, Nov 08, 2016 at 09:51:36PM +0100, Jose Luis Zabalza wrote:
>> > So you have 512MiB on each chip select, so I assume that on the 512MiB
>> > board variants CS1 is not equipped.
>>
>> Yes, it is.
>>
>> >In that case you can in lowlevel.c
>> > test if you find SDRAM on CS1 and if not, disable the chip select
>> > completely in the SDRAM controller.
>>
>> OK. But how ? I enable CS0 and CS1 on DCD table. Is there any way to
>> tell barebox not to use CS1 ?
>>
>> > I am not sure how you can detect if there's SDRAM on CS1. I've seen
>> > situations in which the board just hangs if you access non existent RAM
>> > areas.
>>
>> I have tried it, but I have not be able to implement a code for
>> autodetect. If the code write or read a value on a position without
>> physical  chip, the microcontroller hangs. ????
>>
>> But it's not a problem. A solution is configure both CS and MMU. If
>> bootloader don't access to high positions, there is not problem. After
>> I set a environment variable with memory size and the mem kernel
>> parameter (or ATAG) does the rest.
>
> You said that both board variants work with the same U-Boot binary, how
> does it work there? Is there some detection mechanism or is it only some
> environment variable that you have to set manually?
>
> Sascha
>
> --
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



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Re: Configure RAM size on iMX53 board

[Sascha Hauer]

On Wed, Nov 09, 2016 at 05:23:10AM +0100, Jose Luis Zabalza wrote:
> There is no form of detection. UBoot (a very old version) don't use
> any CS1 address, except with the memtest command.
> If memtest command is executed with 512MB version, UBoot hangs, as expected.
> I set the mem kernel parameter using a environment variable and kernel
> can reach CS1 memory.

Then you could drop the CS1 setup from the DCD table and do the same.
You can then create a command or similar which initializes the CS1
memory and registers the new memory bank.

Sascha

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