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Fri, 18 Mar 2022 14:41:44 -0700 (PDT) MIME-Version: 1.0 References: <20220317074628.GT405@pengutronix.de> <20220318115925.GC12181@pengutronix.de> In-Reply-To: <20220318115925.GC12181@pengutronix.de> From: Trent Piepho Date: Fri, 18 Mar 2022 14:41:33 -0700 Message-ID: To: Sascha Hauer Cc: Tibault Damman , "barebox@lists.infradead.org" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220318_144147_492841_2896A2C8 X-CRM114-Status: GOOD ( 16.42 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:e::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.6 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: nand "BCH decoding failed" when using bch8_hw_romcode ecc mode X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) On Fri, Mar 18, 2022 at 5:00 AM Sascha Hauer wrote: > > On Fri, Mar 18, 2022 at 11:32:36AM +0100, Tibault Damman wrote: > > Gah, I just saw how that mail was sent, let me try that again: > > > > > > Because the data looks right(?), despite the error prints, I tried > > ubiformat again from barebox, then booted linux from SD, and attached > > the ubi nand partition in linux... which worked fine. > > All volumes and data were there. > > > > Very confused about what's going wrong here. > > You can correctly write to the NAND and can even correctly read the > data, that's good news. Yes, NAND hardware likely works fine. This looks like a BCH layout flaw to me. Some background: (for Tibault, I'm sure Sascha knows this!) Normal read/writes to NAND use some kind of ECC. The real data is written, unmodified, to NAND, and then also some extra bytes of ECC information. The real data and the ECC data are probably interleaved in various complicated ways that are a pain to deal with. Suppose the ECC data isn't done correctly. It's generated incorrectly, *written to the wrong spot*, read from the wrong location, etc. It doesn't work. But we still write the real data somewhere too. And can then read it back from that same place. Maybe we are writing the real data to the incorrect locations, but as long as we read it back from the same incorrect locations, it appears to work. So what happens? We can write data, then read it back, but get many ECC errors, because ECC is broken. This looks like your problem. ECC needs to work, as modern MLC/TLC/QLC NAND is not reliable enough to use without ECC. You can test one page one time and it worked with no errors, but test the entire chip many times and it will become clear it just isn't good enough. _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox