From: Trent Piepho <firstname.lastname@example.org>
To: Andrej Picej <email@example.com>
Cc: Barebox List <firstname.lastname@example.org>
Subject: Re: [PATCH 2/2] ARM: i.MX: xload: consider ECC strength when reading page
Date: Mon, 14 Jun 2021 15:14:22 -0700 [thread overview]
Message-ID: <CAMHeXxNttLL84+xoJXALcK7dnBSUVJUDj9fR=wUBEfSg8eG7=A@mail.gmail.com> (raw)
On Tue, Jun 8, 2021 at 11:34 PM Andrej Picej <email@example.com> wrote:
> On 8. 06. 21 14:38, Trent Piepho wrote:
> > On Tue, Jun 8, 2021 at 12:23 AM Andrej Picej <firstname.lastname@example.org> wrote:
> >> On 7. 06. 21 22:03, Trent Piepho wrote:
> > Ok, so 4 ecc bits was used for testing, but your actual use case is
> > for flash that uses 8 bits when NAND has 128 OOB bytes, which the
> > current code uses a value different than 8? My calculation is that
> > 0x800+0x80 would use 18 bit ECC.
> Actually 8 ECC bits was used for testing. Maybe it was wrong that I
> named EccBlockNEccType (from i.MX 6Dual/6Quad Applications Processor
> Reference Manual) as ECC strength (in commit message) as it gets shifted
> to the left for one bit to get ECC size in bits. So yes, we agree, 8 bit
> ECC for 0x800+0x80 (4<<1 = 8) and 18 bit ECC for 0x800+0x80 (9<<1 = 18).
Ok, I see. I discovered this too, as the kernel bug caused Linux to
use 4 bit ECC instead of 8 bit. I instrumented Linux driver and found
it was using 4 bit. I inspected the FCB manually and it was 0x04, so
4 bit ECC is connect? But I have all these NAND errors! I was sure it
would be bad BCH config! Maybe NAND timing? Bad PCB? Nope. FCB ECC
field is half the real ECC value and this is not documented in RM. If
the FCB is 0x04 that is called 8 bits in all BCH documentation in iMX
RM and also Linux driver, dts properties, and so on.
> OK, I see. This is a valid point. Didn't really understand that updating
> only 2nd stage barebox is a common practice. Do you know of any imx6
> board that does that, because this xloader is imx6 specific?
I do not see any imx nand xloader users at all in mainlinux Barebox
codebase. Which is annoying, since I'm trying to boot barebox from
NAND on iMX6ULL and there are no boards in barebox that do this. So I
have to do it from scratch, even though I know such boards exist and
in fact you are using one.
Do I do not know of any specific imx6 boards that do this. As there
are apparently no imx boards booting barebox from nand....
I do know of a specific cyclone5 board that does this.
There is also plenty of documentation that calls for writing 2nd stage
bootloader in Linux with nandwrite. So I think it's reasonable
someone would do this. I think if I setup rauc to do a software
update, I do not see support for FCB update, but there is a raw nand
partition that can easily do 2nd stage bootloader.
But consider that even if barebox spl can support two different BCH
configs on same nand device for booting, neither Barebox nor Linux
support this concept at all. BCH must be the same for entire device,
even with ecc info in the device tree it cannot be done. If there was
a manufacturing step that did a post programming re-flash on first
boot, which reprogrammed to standard BCH parameters, this would almost
certainly save future pain.
> > A solution that works for boths cases, but is also ugly and difficult,
> > is to try both. If xload sees FCB values != calculated values, then
> > just try both settings. One is virtually assured that the incorrect
> > settings will produce massive numbers of errors from BCH. Read a
> > couple pages and the settings which result in uncorrectable ECC errors
> > on all pages are the wrong ones.
> Yes that would be an ugly fix for this.
> But I see one problem. If different ECC values are used for
> pre-bootloader and main bootloader (like it is the case in example that
> you provided) we would have to read pre-bootloader and main bootloader
> with different ECC settings.
Since only the ROM loader boots the pre-bootloader, then it should not
matter if linux can read it. Well, it would be nice if it worked, but
it doesn't need too.
> So the xload would look something like:
> - read a couple of pages from pre-bootloader and select appropriate
> - copy pre-bootloader to RAM with selected "readtotal_pbl"
> - read a couple of pages from main-bootloader and select appropriate
> - copy the remaining pages (main barebox) to RAM with selected
> Now for this we would need to find out where PBL ends and main barebox
> starts (probably from boot data?).
> This would solve all of the problems right?
I think only the last two steps are needed? Since the xloader is
already in RAM, it only needs to load the main bootlaoder.
barebox mailing list
next prev parent reply other threads:[~2021-06-14 22:20 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 9:09 [PATCH 1/2] ARM: i.MX: xload-gpmi-nand: fix bad block mark swapping Andrej Picej
2021-06-07 9:09 ` [PATCH 2/2] ARM: i.MX: xload: consider ECC strength when reading page Andrej Picej
2021-06-07 20:03 ` Trent Piepho
2021-06-08 6:28 ` Sascha Hauer
2021-06-08 7:23 ` Andrej Picej
2021-06-08 12:38 ` Trent Piepho
2021-06-09 6:34 ` Andrej Picej
2021-06-14 22:14 ` Trent Piepho [this message]
2021-06-15 14:35 ` Sascha Hauer
2021-06-15 20:25 ` Trent Piepho
2021-06-16 7:48 ` Andrej Picej
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