[PATCH] clk: imx: clk-imx6ul: The i.mx6ul has no aips_tx3 clock

[PATCH] clk: imx: clk-imx6ul: The i.mx6ul has no aips_tx3 clock

[Robin van der Gracht]

The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register.

Signed-off-by: Robin van der Gracht <robin@protonic.nl>
---
 drivers/clk/imx/clk-imx6ul.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index f28660d..5879661 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -71,7 +71,7 @@ static struct clk *clks[IMX6UL_CLK_END];
 static struct clk_onecell_data clk_data;
 
 static int const clks_init_on[] __initconst = {
-	IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3,
+	IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2,
 	IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
 	IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
 };
@@ -275,7 +275,6 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6UL_CLK_GPT2_SERIAL]	= imx_clk_gate2("gpt2_serial",	"perclk",	base + 0x68,	26);
 	clks[IMX6UL_CLK_UART2_IPG]	= imx_clk_gate2("uart2_ipg",	"ipg",		base + 0x68,	28);
 	clks[IMX6UL_CLK_UART2_SERIAL]	= imx_clk_gate2("uart2_serial",	"uart_podf",	base + 0x68,	28);
-	clks[IMX6UL_CLK_AIPSTZ3]	= imx_clk_gate2("aips_tz3",	"ahb",		base + 0x68,	30);
 
 	/* CCGR1 */
 	clks[IMX6UL_CLK_ECSPI1]		= imx_clk_gate2("ecspi1",	"ecspi_podf",	base + 0x6c,	0);
-- 
2.9.3


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Re: [PATCH] clk: imx: clk-imx6ul: The i.mx6ul has no aips_tx3 clock

[Fabio Estevam]

In the Subject I guess you meant "aips_tz3"

On Fri, Mar 3, 2017 at 10:28 AM, Robin van der Gracht <robin@protonic.nl> wrote:
> The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register.
>
> Signed-off-by: Robin van der Gracht <robin@protonic.nl>
> ---

You should have marked it as v2.

Good catch, with the Subject fixed you can add:
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

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Re: [PATCH] clk: imx: clk-imx6ul: The i.mx6ul has no aips_tx3 clock

[Fabio Estevam]

On Fri, Mar 3, 2017 at 10:36 AM, Fabio Estevam <festevam@gmail.com> wrote:
> In the Subject I guess you meant "aips_tz3"
>
> On Fri, Mar 3, 2017 at 10:28 AM, Robin van der Gracht <robin@protonic.nl> wrote:
>> The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register.
>>
>> Signed-off-by: Robin van der Gracht <robin@protonic.nl>
>> ---
>
> You should have marked it as v2.

Sorry, I just realized that you sent two patches: one for Barebox and
another one for the kernel, so it is not a v2 :-)

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