From: Alexander Shiyan <eagle.alexander923@gmail.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [RFC] clk: rockchip: Fix CPLL setup issue
Date: Mon, 29 Sep 2025 11:29:04 +0300 [thread overview]
Message-ID: <CAP1tNvRnHbCoi=29u_6WbXbD_CZ1kc01deppba4WuWW5mrcMXg@mail.gmail.com> (raw)
In-Reply-To: <aNo_htA1L8khUehc@pengutronix.de>
Hello.
> On Fri, Sep 26, 2025 at 04:15:14PM +0300, Alexander Shiyan wrote:
> > This is a dirty patch to solve the RK3588 CPLL clock setup issue.
> > It's taken from the Rockchip U-Boot repository [1].
> > Any ideas on how to improve it?
> >
> > [1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81
...
> > + /* Barebox addition */
> > + if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
> > + /* Determine CPLL clock and patch clk_bisrintf_pllsrc_en back */
> > + writel(HIWORD_UPDATE(0, BIT(1), 0),
> > + pll->ctx->reg_base + 0x84c);
> > + }
>
> Resetting this bit is not in the U-Boot patch you reference. Do we need
> this?
Yes.
https://github.com/rockchip-linux/u-boot/commit/7560cacdd3a68bb475f23b4249a98025c89064d4
next prev parent reply other threads:[~2025-09-29 8:29 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-26 13:15 Alexander Shiyan
2025-09-29 8:12 ` Sascha Hauer
2025-09-29 8:29 ` Alexander Shiyan [this message]
2025-09-29 8:44 ` Sascha Hauer
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