[RFC] clk: rockchip: Fix CPLL setup issue

[RFC] clk: rockchip: Fix CPLL setup issue

[Alexander Shiyan]

This is a dirty patch to solve the RK3588 CPLL clock setup issue.
It's taken from the Rockchip U-Boot repository [1].
Any ideas on how to improve it?

[1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 drivers/clk/rockchip/clk-pll.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 904d70d5d4..4b92639e1b 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -940,6 +940,13 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
 		}
 	}
 
+	/* Barebox addition */
+	if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
+		/* Determine CPLL clock and patch clk_bisrintf_pllsrc_en */
+		writel(HIWORD_UPDATE(BIT(1), BIT(1), 0),
+		       pll->ctx->reg_base + 0x84c);
+	}
+
 	/* set pll power down */
 	writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN,
 			     RK3588_PLLCON1_PWRDOWN, 0),
@@ -971,6 +978,13 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
 	if ((pll->type == pll_rk3588) && rate_change_remuxed)
 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 
+	/* Barebox addition */
+	if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
+		/* Determine CPLL clock and patch clk_bisrintf_pllsrc_en back */
+		writel(HIWORD_UPDATE(0, BIT(1), 0),
+		       pll->ctx->reg_base + 0x84c);
+	}
+
 	return ret;
 }
 
-- 
2.38.2

Re: [RFC] clk: rockchip: Fix CPLL setup issue

[Sascha Hauer]

On Fri, Sep 26, 2025 at 04:15:14PM +0300, Alexander Shiyan wrote:
> This is a dirty patch to solve the RK3588 CPLL clock setup issue.
> It's taken from the Rockchip U-Boot repository [1].
> Any ideas on how to improve it?
> 
> [1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81
> 
> Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> ---
>  drivers/clk/rockchip/clk-pll.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
> index 904d70d5d4..4b92639e1b 100644
> --- a/drivers/clk/rockchip/clk-pll.c
> +++ b/drivers/clk/rockchip/clk-pll.c
> @@ -940,6 +940,13 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
>  		}
>  	}
>  
> +	/* Barebox addition */
> +	if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
> +		/* Determine CPLL clock and patch clk_bisrintf_pllsrc_en */
> +		writel(HIWORD_UPDATE(BIT(1), BIT(1), 0),
> +		       pll->ctx->reg_base + 0x84c);
> +	}
> +
>  	/* set pll power down */
>  	writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN,
>  			     RK3588_PLLCON1_PWRDOWN, 0),
> @@ -971,6 +978,13 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
>  	if ((pll->type == pll_rk3588) && rate_change_remuxed)
>  		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
>  
> +	/* Barebox addition */
> +	if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
> +		/* Determine CPLL clock and patch clk_bisrintf_pllsrc_en back */
> +		writel(HIWORD_UPDATE(0, BIT(1), 0),
> +		       pll->ctx->reg_base + 0x84c);
> +	}

Resetting this bit is not in the U-Boot patch you reference. Do we need
this?

If yes, please add a variable insted of duplicating this test, like for
example

	bool need_pll3_fix = pll->reg_base == pll->ctx->reg_base + 0x1a0;

Other than that the itself looks ok. Polish the commit message a bit and
we are good to go.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [RFC] clk: rockchip: Fix CPLL setup issue

[Alexander Shiyan]

Hello.

> On Fri, Sep 26, 2025 at 04:15:14PM +0300, Alexander Shiyan wrote:
> > This is a dirty patch to solve the RK3588 CPLL clock setup issue.
> > It's taken from the Rockchip U-Boot repository [1].
> > Any ideas on how to improve it?
> >
> > [1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81
...
> > +     /* Barebox addition */
> > +     if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
> > +             /* Determine CPLL clock and patch clk_bisrintf_pllsrc_en back */
> > +             writel(HIWORD_UPDATE(0, BIT(1), 0),
> > +                    pll->ctx->reg_base + 0x84c);
> > +     }
>
> Resetting this bit is not in the U-Boot patch you reference. Do we need
> this?

Yes.
https://github.com/rockchip-linux/u-boot/commit/7560cacdd3a68bb475f23b4249a98025c89064d4

Re: [RFC] clk: rockchip: Fix CPLL setup issue

[Sascha Hauer]

On Mon, Sep 29, 2025 at 11:29:04AM +0300, Alexander Shiyan wrote:
> Hello.
> 
> > On Fri, Sep 26, 2025 at 04:15:14PM +0300, Alexander Shiyan wrote:
> > > This is a dirty patch to solve the RK3588 CPLL clock setup issue.
> > > It's taken from the Rockchip U-Boot repository [1].
> > > Any ideas on how to improve it?
> > >
> > > [1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81
> ...
> > > +     /* Barebox addition */
> > > +     if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
> > > +             /* Determine CPLL clock and patch clk_bisrintf_pllsrc_en back */
> > > +             writel(HIWORD_UPDATE(0, BIT(1), 0),
> > > +                    pll->ctx->reg_base + 0x84c);
> > > +     }
> >
> > Resetting this bit is not in the U-Boot patch you reference. Do we need
> > this?
> 
> Yes.
> https://github.com/rockchip-linux/u-boot/commit/7560cacdd3a68bb475f23b4249a98025c89064d4

Ah, alright, they fixed it in a later commit. I only looked at the
commit you referenced. So please reference both in the commit message.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |