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Mon, 27 Oct 2025 07:27:56 -0700 (PDT) MIME-Version: 1.0 References: <20251027141555.846950-1-s.hauer@pengutronix.de> In-Reply-To: <20251027141555.846950-1-s.hauer@pengutronix.de> From: Alexander Shiyan Date: Mon, 27 Oct 2025 17:27:43 +0300 X-Gm-Features: AWmQ_bm0xCzZy7JglYT5esuY_lll_2r1BPQlv3hELL-2amSMgYRJVHqewMtvYYo Message-ID: To: Sascha Hauer Cc: Barebox List , Michael Tretter Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251027_072758_144491_C1824D14 X-CRM114-Status: GOOD ( 22.19 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-3.7 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH] clk: rockchip rk3588: configure CPLL in driver X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Hello. PLL_PPLL -> PLL_CPLL ? =D0=BF=D0=BD, 27 =D0=BE=D0=BA=D1=82. 2025=E2=80=AF=D0=B3. =D0=B2 17:16, Sas= cha Hauer : > > The rk3588 CPLL should be configured to 1.5GHz and 09c87c85e0 ("ARM: > dts: rockchip: Set CPLL frequency for RK3588") does this. It does it > however after the assigned-clocks/assigned-clock-rates properties of the > "rockchip,rk3588-cru" node have been evaluated which contain a setting > of CLK_150M_SRC which is a child clock of the CPLL. Configuring the > CPLL after CLK_150M_SRC alters the setting of the just configured 150M > clock again. > > We must make sure to configure the CPLL before its child clocks. For > this we could overwrite the assigned-* properties in the > "rockchip,rk3588-cru" node, but with that we would miss future updates > to this property, so configure the CPLL in the driver code instead right > before we call into of_clk_add_provider(). > > Fixes: 09c87c85e0 ("ARM: dts: rockchip: Set CPLL frequency for RK3588") > Signed-off-by: Sascha Hauer > --- > arch/arm/dts/rk3588.dtsi | 3 --- > drivers/clk/rockchip/clk-rk3588.c | 7 +++++++ > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi > index 42d692a9bd..416700cf0e 100644 > --- a/arch/arm/dts/rk3588.dtsi > +++ b/arch/arm/dts/rk3588.dtsi > @@ -1,9 +1,6 @@ > // SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > / { > - assigned-clocks =3D <&cru PLL_CPLL>; > - assigned-clock-rates =3D <1500000000>; > - > dmc: memory-controller { > compatible =3D "rockchip,rk3588-dmc"; > rockchip,pmu =3D <&pmu1grf>; > diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk= -rk3588.c > index 5aecfb3b1b..fcf95131df 100644 > --- a/drivers/clk/rockchip/clk-rk3588.c > +++ b/drivers/clk/rockchip/clk-rk3588.c > @@ -2500,6 +2500,13 @@ static void __init rk3588_clk_init(struct device_n= ode *np) > > rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST); > > + /* > + * CPLL must run at 1.5GHz. Do this here instead via assigned-clo= cks > + * in the device tree so that we do not have to overwrite the pro= perties > + * in the upstream device tree. > + */ > + clk_set_rate(ctx->clk_data.clks[PLL_PPLL], 1500000000); > + > rockchip_clk_of_add_provider(np, ctx); > } > > -- > 2.47.3 >