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From: Michael Graichen <michael.graichen@hotmail.com>
To: "barebox@lists.infradead.org" <barebox@lists.infradead.org>
Subject: Barebox for Zedboard
Date: Thu, 19 Mar 2020 10:38:41 +0000	[thread overview]
Message-ID: <DB7PR02MB43321CDF6386A16A725DC131ABF40@DB7PR02MB4332.eurprd02.prod.outlook.com> (raw)

Hey,

i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC.
I have seen that Barebox has an defconfig for the zynq
so i tried

export ARCH=arm
export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf-
export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH
make zynq_defconfig
make -j`nproc`

which compiles me the image

barebox-flash-image -> images/barebox-avnet-zedboard.img

when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool

dev$ bootgen -image bootimage.bif -o i BOOT.bin

and .bif file was

dev$ cat bootimage.bif
//arch = zynq; split = false; format = BIN
the_ROM_image:
{
     [bootloader]FSBL.elf
     design_1_wrapper.bit
     u-boot.elf
}


that i copied onto an SD-Card and powed up the board. 

But since i want to use Barebox how do i produce the BOOT.bin file? 
and how is the programming of the FPGA Logic done?

Best Regards 
Michael


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             reply	other threads:[~2020-03-19 10:38 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-19 10:38 Michael Graichen [this message]
2020-03-19 10:53 ` Lucas Stach
2020-03-23 14:22   ` AW: " Michael Graichen
2020-03-23 15:18   ` Michael Graichen

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