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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: pliops.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PR3P195MB0555.EURP195.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: b79daad1-8d1f-49ed-f1bc-08db60496b40 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2023 13:34:25.1086 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 40fe8f47-55ac-403a-a5ab-1be3dd209cf8 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3QUYP7Y6yc4s+FA2dayGwgFLiZ+NEkSmcxJBz6kwvxyqsR4Y4rzWMnRGLeB2FkO0zQ3Al2nTkipJKdz3/+v3DQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P195MB0580 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230529_063434_726936_33BE5DF7 X-CRM114-Status: GOOD ( 34.22 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: RE: [PATCH v2] Porting barebox to a new SoC X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Hi Ahmad, I have revised the addresses and used DRAM address @ 0 instead: #define UARTBASE (0xD000307000) #define DRAM_ADDR (0x00000000) #define MY_STACK_TOP (0x00000000 + SZ_2M) // Set the stack 2MB from DRAM= start static inline void spider_serial_putc(void *base, int c) { *((volatile unsigned *)base) =3D c; } I will try to test it on QEMU using an initial QEMU machine we made for Spi= der. In this machine we only have 3 memory regions and a PL011 UART: spider_soc_memories soc_memories[] =3D { {.name =3D "SPIDER_GPRAM", .add =3D 0xC000000000ULL, .size =3D 4 * Mi= B}, {.name =3D "SPIDER_ROM", .add =3D 0xC004000000ULL, .size =3D 128 * = KiB}, {.name =3D "SPIDER_DRAM", .add =3D 0x0000000000ULL, .size =3D 1 * Gi= B}, }; This special QEMU machine can run our BL1 code from "ROM" address (we set t= he RVBAR to point there). So my idea is to test the barebox image by the following steps: 1. Modify the QEMU code to have a "ROM" with the size of 128M. 2. Compile our BL1 code to include the barebox.bin as a const array, copy i= t to "DRAM" @ address 0 and jump there. For this to work I wanted to understand how to call (i.e. what arguments to= pass) to barebox. So I checked the barebox.map and found the function "start" on address 0. Then I went to arch/arm/cpu/start.c and realized that the code is compiled = with CONFIG_PBL_IMAGE. In that case I assume I need to pass 3 arguments and use this function prot= otype: void start(unsigned long membase, unsigned long memsize, void *boarddata); Few questions: 1. Will that call work: typedef void (*barebox_start)(unsigned long , unsigned long , void *); #define DRAM_START (0) barebox_start p_barebox =3D (barebox_start)DRAM_START; p_barebox(DRAM_START, DRAM_START+SZ_2M, (void *)(DRAM_START+SZ_4M)); This assumes that my BL1 code also copied the device tree (barebox-dt-2= nd.img? start_dt_2nd.pblb? start_spider_mk1_evk.pblb?) 2. Do I want to have my code compiled with CONFIG_PBL_IMAGE? If I understand correctly, it means that my code will provide a PBL (a.= k.a BL2) which will set the DRAM and STACK among other things (MMU?). In that case I assume it is OK. 3. If I try to remove it by having CONFIG_PBL_IMAGE=3Dn on spider_defconfig= this doesn't do anything The build (make spider_defconfig) ignores it and say that " No change t= o .config ". 4. I also tried to understand how to implement PUTC_LL but not sure I under= stand. 4.1 When I set "CONFIG_DEBUG_LL=3Dy" on spider_defconfig it is again not= written to .config and I get " No change to .config " message. 4.2 Do I need to have my own debug_ll.h file? 5. When I make changes to spider_defconfig and try to regenerate the .confi= g and I get " No change to .config " message, does it mean that those macro= s are "hidden" symbols like you said about the CONFIG_CPU_V8? Apologize for so many questions :-)=20 Cheers, Lior. -----Original Message----- From: Lior Weintraub=20 Sent: Sunday, May 28, 2023 11:16 PM To: Ahmad Fatoum ; barebox@lists.infradead.org Subject: RE: [PATCH v2] Porting barebox to a new SoC Hi Ahmad, Thank you so much for your kind support! Indeed we also have a 16GB DRAM that starts from address 0 (though currentl= y we don't have the controller settings (under development)). I also wrote the BootROM (BL1) for this SoC (128KB ROM @ address 0xC0040000= 00). I understand now that it would be best for me to develop BL2 that will run = from our SRAM. As this BL2 code is bare-metal I have no problem or limitations with the 40= bit addresses. The BL2 code will initialize the DRAM controller and then copy Barebox imag= e from NOR Flash to address 0 of the DRAM. Our NOR Flash is 128MB in size and it is accessed via QSPI controller. I tried applying your suggested patch but got an error while doing so: $git apply 0002-Ahmad.patch 0002-Ahmad.patch:115: trailing whitespace. .of_compatible =3D spider_board_of_match, }; error: corrupt patch at line 117 After some digging I found that my Outlook probably messed with the patch f= ormat (even though I am using text only and no HTML format). When I went to the web and copied the patch from there (mailing list archiv= e) it was working well (i.e. no compilation error). Cheers, Lior. -----Original Message----- From: Ahmad Fatoum Sent: Sunday, May 28, 2023 6:38 PM To: barebox@lists.infradead.org Cc: Lior Weintraub Subject: [PATCH v2] Porting barebox to a new SoC CAUTION: External Sender From: Lior Weintraub Hi, I tried to follow the porting guide on https://ddec1-0-en-ctp.trendmicro.co= m:443/wis/clicktime/v1/query?url=3Dhttps%3a%2f%2fwww.barebox.org%2fdoc%2fla= test%2fdevel%2fporting.html%23&umid=3D60097eda-f136-45a1-9c8e-cf6a76e45cf8&= auth=3D860a7ebb9feba264acc79b6e38eb59582349362c-480ae23736add41c88ab8d30c09= 0a75517ca7f9e but couldn't follow the instructions. I would like to port barebox to a new SoC (which is not a derivative of any= known SoC). It has the following: * Single Cortex A53 * SRAM (4MB) located on address 0xC000000000 The below patch shows my initial test to try and have a starting point. I am setting env variables: export ARCH=3Darm64 export CROSS_COMPILE=3D/home/pliops/workspace/ARM/arm-gnu-toolchain/bin/aar= ch64-none-elf- Then I build with: make spider_defconfig && make This gives an error: aarch64-none-elf-gcc: error: unrecognized argument in option '-mabi=3Dapcs-= gnu' aarch64-none-elf-gcc: note: valid arguments to '-mabi=3D' are: ilp32 lp64 aarch64-none-elf-gcc: error: unrecognized command-line option '-msoft-float= ' aarch64-none-elf-gcc: error: unrecognized command-line option '-mno-unalign= ed-access' /home/pliops/workspace/simplest-linux-demo/barebox/scripts/Makefile.build:1= 40: recipe for target 'scripts/mod/empty.o' failed make[2]: *** [scripts/mod/empty.o] Error 1 Not sure why the compiler flags get -mabi=3Dapcs-gnu when I explicitly set = CONFIG_CPU_V8 and the arch/arm/Makefile has: ifeq ($(CONFIG_CPU_V8), y) CFLAGS_ABI :=3D-mabi=3Dlp64 The changes I did: >>From 848b5f9b18bb1bb96d197cbc1b368ee0a729d581 Mon Sep 17 00:00:00 2001 --- arch/arm/Kconfig | 13 ++++++++ arch/arm/Makefile | 1 + arch/arm/boards/Makefile | 1 + arch/arm/boards/spider-evk/Makefile | 4 +++ arch/arm/boards/spider-evk/board.c | 26 +++++++++++++++ arch/arm/boards/spider-evk/lowlevel.c | 30 +++++++++++++++++ arch/arm/configs/spider_defconfig | 8 +++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/spider-mk1-evk.dts | 10 ++++++ arch/arm/dts/spider-mk1.dtsi | 46 +++++++++++++++++++++++++++ arch/arm/mach-spider/Kconfig | 16 ++++++++++ arch/arm/mach-spider/Makefile | 1 + arch/arm/mach-spider/lowlevel.c | 14 ++++++++ images/Makefile | 1 + images/Makefile.spider | 5 +++ include/mach/spider/lowlevel.h | 7 ++++ 16 files changed, 184 insertions(+) create mode 100644 arch/arm/boards/spider-evk/Makefile create mode 100644 arch/arm/boards/spider-evk/board.c create mode 100644 arch/arm/boards/spider-evk/lowlevel.c create mode 100644 arch/arm/configs/spider_defconfig create mode 100644 a= rch/arm/dts/spider-mk1-evk.dts create mode 100644 arch/arm/dts/spider-mk1.= dtsi create mode 100644 arch/arm/mach-spider/Kconfig create mode 100644 a= rch/arm/mach-spider/Makefile create mode 100644 arch/arm/mach-spider/lowle= vel.c create mode 100644 images/Makefile.spider create mode 100644 includ= e/mach/spider/lowlevel.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e76ee0f6dfe1..e5dcf1= 28447e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -255,6 +255,18 @@ config ARCH_ROCKCHIP select HAS_DEBUG_LL imply GPIO_ROCKCHIP +config ARCH_SPIDER + bool "Pliops Spider based" + depends on 64BIT + depends on ARCH_MULTIARCH + select GPIOLIB + select HAVE_PBL_MULTI_IMAGES + select COMMON_CLK + select CLKDEV_LOOKUP + select COMMON_CLK_OF_PROVIDER + select OFTREE + select OFDEVICE + config ARCH_STM32MP bool "STMicroelectronics STM32MP" depends on 32BIT @@ -331,6 +343,7 @@ source "arch/arm/mach-omap/Kconfig" source "arch/arm/mach-pxa/Kconfig" source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-socfpga/Kconfig" +source "arch/arm/mach-spider/Kconfig" source "arch/arm/mach-stm32mp/Kconfig" source "arch/arm/mach-versatile/Kconfig" source "arch/arm/mach-vexpress/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 35ebc70f44e2..4c63= dfee48f4 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -101,6 +101,7 @@ machine-$(CONFIG_ARCH_MXS) +=3D mxs machine-$(CONFIG_ARCH_MVEBU) +=3D mvebu machine-$(CONFIG_ARCH_NOMADIK) +=3D nomadik machine-$(CONFIG_ARCH_OMAP) +=3D omap +machine-$(CONFIG_ARCH_SPIDER) +=3D spider machine-$(CONFIG_ARCH_PXA) +=3D pxa machine-$(CONFIG_ARCH_ROCKCHIP) +=3D rockchip machine-$(CONFIG_ARCH_SAMSUNG) +=3D samsung diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 2877= debad535..6fe0a90c81ea 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -135,6 +135,7 @@ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += =3D terasic-de10-nano/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) +=3D terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) +=3D solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) +=3D solidrun-microsom/ +obj-$(CONFIG_MACH_SPIDER_MK1_EVK) +=3D spider-evk/ obj-$(CONFIG_MACH_STM32MP15XX_DKX) +=3D stm32mp15xx-dkx/ obj-$(CONFIG_MACH_STM32MP13XX_DK) +=3D stm32mp13xx-dk/ obj-$(CONFIG_MACH_LXA_MC1) +=3D lxa-mc1/ diff --git a/arch/arm/boards/spider-evk/Makefile b/arch/arm/boards/spider-e= vk/Makefile new file mode 100644 index 000000000000..da63d2625f7a --- /dev/null +++ b/arch/arm/boards/spider-evk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y +=3D board.o +lwl-y +=3D lowlevel.o diff --git a/arch/arm/boards/spider-evk/board.c b/arch/arm/boards/spider-ev= k/board.c new file mode 100644 index 000000000000..3920e83b457d --- /dev/null +++ b/arch/arm/boards/spider-evk/board.c @@ -0,0 +1,26 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +static int spider_board_probe(struct device *dev) { + /* Do some board-specific setup */ + return 0; +} + +static const struct of_device_id spider_board_of_match[] =3D { + { .compatible =3D "pliops,spider-mk1-evk" }, + { /* sentinel */ }, +}; + +static struct driver spider_board_driver =3D { + .name =3D "board-spider", + .probe =3D spider_board_probe, + .of_compatible =3D spider_board_of_match, };=20 +device_platform_driver(spider_board_driver); diff --git a/arch/arm/boards/spider-evk/lowlevel.c b/arch/arm/boards/spider= -evk/lowlevel.c new file mode 100644 index 000000000000..e36fcde4208e --- /dev/null +++ b/arch/arm/boards/spider-evk/lowlevel.c @@ -0,0 +1,30 @@ +#include +#include +#include + +#define BASE_ADDR (0xD000307000) +#define GPRAM_ADDR (0xC000000000) +#define MY_STACK_TOP (0xC000000000 + SZ_2M) // Set the stack 2MB from G= PRAM start (excatly in the middle) +static inline void spider_serial_putc(void *base, int c) { +// if (!(readl(base + UCR1) & UCR1_UARTEN)) +// return; +// +// while (!(readl(base + USR2) & USR2_TXDC)); +// +// writel(c, base + URTX0); +} + +ENTRY_FUNCTION_WITHSTACK(start_spider_mk1_evk, MY_STACK_TOP, r0, r1, +r2) { + extern char __dtb_spider_mk1_evk_start[]; + + spider_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + pbl_set_putc(spider_serial_putc, (void *)BASE_ADDR); + + barebox_arm_entry(GPRAM_ADDR, SZ_2M,=20 +__dtb_spider_mk1_evk_start); } diff --git a/arch/arm/configs/spider_defconfig b/arch/arm/configs/spider_de= fconfig new file mode 100644 index 000000000000..c91bb889d97f --- /dev/null +++ b/arch/arm/configs/spider_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARCH_SPIDER=3Dy +CONFIG_MACH_SPIDER_MK1_EVK=3Dy +CONFIG_BOARD_ARM_GENERIC_DT=3Dy +CONFIG_MALLOC_TLSF=3Dy +CONFIG_KALLSYMS=3Dy +CONFIG_RELOCATABLE=3Dy +CONFIG_CONSOLE_ALLOW_COLOR=3Dy +CONFIG_PBL_CONSOLE=3Dy diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 98f4c4e019= 4b..94b304d4878f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -134,6 +134,7 @@ lwl-$(CONFIG_MACH_SOLIDRUN_CUBOX) +=3D dove-cubox-bb.dt= b.o lwl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) +=3D imx6dl-hummingboard.dtb.o imx6q-= hummingboard.dtb.o \ imx6dl-hummingboard2.dtb.o imx6q-hummingboa= rd2.dtb.o \ imx6q-h100.dtb.o +lwl-$(CONFIG_MACH_SPIDER_MK1_EVK) +=3D spider-mk1-evk.dtb.o lwl-$(CONFIG_MACH_SKOV_IMX6) +=3D imx6s-skov-imx6.dtb.o imx6dl-skov-imx6.d= tb.o imx6q-skov-imx6.dtb.o lwl-$(CONFIG_MACH_SKOV_ARM9CPU) +=3D at91-skov-arm9cpu.dtb.o lwl-$(CONFIG_MACH_SEEED_ODYSSEY) +=3D stm32mp157c-odyssey.dtb.o diff --git= a/arch/arm/dts/spider-mk1-evk.dts b/arch/arm/dts/spider-mk1-evk.dts new fi= le mode 100644 index 000000000000..b8081cb85bf8 --- /dev/null +++ b/arch/arm/dts/spider-mk1-evk.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 + +/dts-v1/; + +#include "spider-mk1.dtsi" + +/ { + model =3D "Pliops Spider MK-I EVK"; + compatible =3D "pliops,spider-mk1-evk"; }; diff --git a/arch/arm/dts/spider-mk1.dtsi b/arch/arm/dts/spider-mk1.dtsi ne= w file mode 100644 index 000000000000..d4613848169d --- /dev/null +++ b/arch/arm/dts/spider-mk1.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { + stdout-path =3D &uart0; + }; + + aliases { + serial0 =3D &uart0; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + }; + }; + + memory@1000000 { + reg =3D <0x0 0x1000000 0x0 0x400000>; /* 128M */ + device_type =3D "memory"; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + sram@c000000000 { + compatible =3D "mmio-sram"; + reg =3D <0xc0 0x0 0x0 0x400000>; + }; + + uart0: serial@d000307000 { + compatible =3D "pliops,spider-uart"; + reg =3D <0xd0 0x307000 0 0x1000>; + }; + }; +}; diff --git a/arch/arm/mach-spider/Kconfig b/arch/arm/mach-spider/Kconfig ne= w file mode 100644 index 000000000000..6d2f888a5fd8 --- /dev/null +++ b/arch/arm/mach-spider/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if ARCH_SPIDER + +config ARCH_SPIDER_MK1 + bool + select CPU_V8 + help + The first Cortex-A53-based SoC of the spider family. + This symbol is invisble and select by boards + +config MACH_SPIDER_MK1_EVK + bool "Pliops Spider Reference Design Board" + select ARCH_SPIDER_MK1 + +endif diff --git a/arch/arm/mach-spider/Makefile b/arch/arm/mach-spider/Makefile = new file mode 100644 index 000000000000..b08c4a93ca27 --- /dev/null +++ b/arch/arm/mach-spider/Makefile @@ -0,0 +1 @@ +lwl-y +=3D lowlevel.o diff --git a/arch/arm/mach-spider/lowlevel.c b/arch/arm/mach-spider/lowleve= l.c new file mode 100644 index 000000000000..5d62ef0f39e5 --- /dev/null +++ b/arch/arm/mach-spider/lowlevel.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include + +void spider_lowlevel_init(void) +{ + arm_cpu_lowlevel_init(); + /* + * not yet relocated, only do writel/readl for stuff that's + * critical to run early. No global variables allowed. + */ +} diff --git a/images/Makefile b/images/Makefile index c93f9e268978..97521e71= 3228 100644 --- a/images/Makefile +++ b/images/Makefile @@ -150,6 +150,7 @@ include $(srctree)/images/Makefile.mxs include $(srctr= ee)/images/Makefile.omap3 include $(srctree)/images/Makefile.rockchip include $(srctree)/images/Makefile.socfpga +include $(srctree)/images/Makefile.spider include $(srctree)/images/Makefile.stm32mp include $(srctree)/images/Makefile.tegra include $(srctree)/images/Makefi= le.versatile diff --git a/images/Makefile.spider b/images/Makefile.spider new file mode = 100644 index 000000000000..c32f2762df04 --- /dev/null +++ b/images/Makefile.spider @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +pblb-$(CONFIG_MACH_SPIDER_MK1_EVK) +=3D start_spider_mk1_evk=20 +FILE_barebox-spider-mk1-evk.img =3D start_spider_mk1_evk.pblb +image-$(CONFIG_MACH_SPIDER_MK1_EVK) +=3D barebox-spider-mk1-evk.img diff --git a/include/mach/spider/lowlevel.h b/include/mach/spider/lowlevel.= h new file mode 100644 index 000000000000..6e0ce1c77f7e --- /dev/null +++ b/include/mach/spider/lowlevel.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MACH_SPIDER_H_=20 +#define __MACH_SPIDER_H_ + +void spider_lowlevel_init(void); + +#endif -- 2.38.4