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charset="Windows-1252" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: pliops.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PR3P195MB0555.EURP195.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 9afed496-2802-434f-87d9-08db9f28c82b X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Aug 2023 13:49:30.8327 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 40fe8f47-55ac-403a-a5ab-1be3dd209cf8 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: +g+JPnoYPl9WFI1fvw6j35u4SG/mfeMBZhFGxkovpgjIhyL9N39BcltVvbeNDH98eYK/ivoeYLy30mYomaoVOQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9P195MB2131 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230817_064944_034223_B9FC74A2 X-CRM114-Status: GOOD ( 30.18 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.9 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.2 Subject: RE: ARM: mmu_early_enable X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Hi Sascha, I read your answer again and realized my misunderstanding. So essentially what you say is that all 48 bits of the address space would = be set as flat 1:1 un-cached and only the SRAM region will be set as cached= . In that case the UART at address 0xD0_0030_7000 and our ROM at address 0xC0= _0400_0000 should be OK to access. We will further investigate and try to figure out what went wrong. Thanks, Lior. > -----Original Message----- > From: Lior Weintraub > Sent: Thursday, August 17, 2023 10:32 AM > To: Sascha Hauer > Cc: barebox@lists.infradead.org > Subject: RE: ARM: mmu_early_enable >=20 > But the UART is set on a total different memory space. > The SRAM where barebox runs and also given as membase and memsize is in > the region of 0xC0_0000_0000 > The UART is in the region of 0xD0_0030_7000. >=20 > According the tarmac log, it looks like access to this location caused th= e > exception: > 3505306 ns ES (000000c0000814ac:910003fd) O el3h: mov x29, > sp (console_putc) > R X29 (AARCH64) 000000c0 00377ac0 > 3505306 ns ES (000000c0000814b0:f9400460) O el3h: ldr x0, > [x3, #8] (console_putc) > LD 000000c0000825d0 ........ ........ 000000d0 00307= 000 > S:c0000825d0 > R X0 (AARCH64) 000000d0 00307000 > 3505307 ns ES (000000c0000814b4:d63f0040) O el3h: blr x2 > (console_putc) > R X30 (AARCH64) 000000c0 000814b8 > 3505371 ns ES (000000c000000b5c:b9000001) O el3h: str w1, > [x0] (spider_serial_putc) > EXC [0x200] Synchronous Current EL with SP_ELx > R FAR_EL3 (AARCH64) 000000c0 00000b5c > R ESR_EL3 (AARCH64) 8600000f > R CPSR 200003cd > R SPSR_EL3 (AARCH64) 200003cd > R ELR_EL3 (AARCH64) 000000c0 00000b5c > 3505443 ns ES (000000c004000a00:14000586) O el3h: b > c004002018 (Vectors) > EXC [0x200] Synchronous Current EL with SP_ELx > R FAR_EL3 (AARCH64) 000000c0 04000a00 > R ESR_EL3 (AARCH64) 8600000e > R CPSR 200003cd > R SPSR_EL3 (AARCH64) 200003cd > R ELR_EL3 (AARCH64) 000000c0 04000a00 >=20 > BTW, In addition to the UART, there seems to be another issue. > The Vectors themselves are located in our ROM location which also resides= on > a different memory area (0xC0_0400_0000 space). > Once the UART access caused an exception, the jump to Vectors caused > another exception so we are in a loop. >=20 > Looks like a catch22 to me. > On one hand the barebox wanted to start clean and disabled the MMU but on > the other hand the mmu_early_enable sets a partial MMU which causes > exceptions. > What do you think needs to be the best solution here? >=20 > Cheers, > Lior. >=20 > > -----Original Message----- > > From: Sascha Hauer > > Sent: Thursday, August 17, 2023 10:18 AM > > To: Lior Weintraub > > Cc: barebox@lists.infradead.org > > Subject: Re: ARM: mmu_early_enable > > > > CAUTION: External Sender > > > > On Thu, Aug 17, 2023 at 06:22:50AM +0000, Lior Weintraub wrote: > > > Hi Sascha, > > > > > > I think I found an issue with the CONFIG_MMU feature. > > > When the code under barebox_pbl_start calls mmu_early_enable, the > MMU > > > is set such that only the given SRAM is defined (membase, memsize). > > > But then, if DEBUG_LL is in use and the function pr_debug is called w= e > > > get an exception because the UART address is not included in the MMU. > > > > That shouldn't happen. See the code in mmu_early_enable(): > > > > early_remap_range(0, 1UL << (BITS_PER_VA - 1), MAP_UNCACHED); > > early_remap_range(membase, memsize - OPTEE_SIZE, MAP_CACHED); > > early_remap_range(membase + memsize - OPTEE_SIZE, OPTEE_SIZE, > > MAP_FAULT); > > > > The first line maps the whole address space uncached in a flat 1:1 > > mapping. The second and third lines map the SDRAM (SRAM in your case) > > cached. > > > > Your availabe memory is quite small (3MiB) and by skipping the > > relocation your SRAM layout is not standard. Could it be that something > > overwrites your page tables? > > > > Sascha > > > > -- > > Pengutronix e.K. | = | > > Steuerwalder Str. 21 | http://secure- > > web.cisco.com/1OEKFl2BnNpoLNUlGA--QcqTLOmehOhRYUZN- > > THBCB91kVNePMy2om4tD5Nv- > > > _isTZzlwD1lXGQLUMWmqHlBH9dEe0vcctRC7gn_a6v7IxQu5RV7VCRo5Rl7Tylx > > vh1hfoYe3c1lCTbGAEE5kXKVZLdKBs7oNP9Xn4ml3gy7I78- > > > c_QsTMlZ4xNZj06ORqpIvkGFgk72fNMsGjjLXZP6zTk2yEI2gjapDB8ClJ0mVtAl > > oiP9YHbgjuY0qbUbZfQq-UuasUtCi2rRo0Pu2jKm7sqnlCFb16xbdfl- > > > JN9oqUXAy8l3lHq0yGyfhYZnzWTxH/http%3A%2F%2Fwww.pengutronix.de% > > 2F | > > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 = | > > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-555= 5 |