Re: [PATCH 10/10] clk: socfpga: add agilex5 clock support

[Sascha Hauer <s.hauer@pengutronix.de>]

On Tue, Oct 29, 2024 at 09:42:40AM +0100, Steffen Trumtrar wrote:
> Add support for the Stratix10 and Agilex5 pll,gate and periph clocks.
> 
> Only tested on Agilex5.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
>  drivers/clk/socfpga/Makefile              |   4 +-
>  drivers/clk/socfpga/clk-agilex5.c         | 834 ++++++++++++++++++++++++++++++
>  drivers/clk/socfpga/clk-gate-s10.c        | 184 +++++++
>  drivers/clk/socfpga/clk-periph-s10.c      | 163 ++++++
>  drivers/clk/socfpga/clk-pll-s10.c         | 140 +++++
>  drivers/clk/socfpga/clk.h                 |   9 +
>  drivers/clk/socfpga/stratix10-clk.h       |  73 +++
>  include/dt-bindings/clock/agilex5-clock.h | 135 +++--
>  8 files changed, 1488 insertions(+), 54 deletions(-)

Move this patch up. clk support should be available when adding a board
using it.

> +static int agilex5_clkmgr_probe(struct device *dev)
> +{
> +	struct device_node *np = dev->of_node;
> +	struct stratix10_clock_data *clk_data;
> +	struct resource *res;
> +	int i, num_clks;
> +
> +	res = dev_get_resource(dev, IORESOURCE_MEM, 0);
> +	if (IS_ERR(res))
> +		return PTR_ERR(res);
> +
> +	num_clks = AGILEX5_NUM_CLKS;
> +
> +	clk_data = xzalloc(struct_size(clk_data, clk_data.hws, num_clks));
> +	if (!clk_data)
> +		return -ENOMEM;

Won't happen.

> +static int socfpga_gate_get_parent(struct clk_hw *hwclk)
> +{
> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> +	u32 mask, second_bypass;
> +	u8 parent = 0;
> +	const char *name = clk_hw_get_name(hwclk);
> +
> +printk("%s: %s\n", __func__, name);
> +
> +	if (socfpgaclk->bypass_reg) {
> +		mask = (0x1 << socfpgaclk->bypass_shift);
> +		parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
> +			  socfpgaclk->bypass_shift);
> +printk("%s: parent %d\n", __func__, parent);

Debugging leftovers.

> +struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
> +{
> +	struct clk_hw *hw_clk;
> +	struct socfpga_gate_clk *socfpga_clk;
> +	struct clk_init_data init;
> +	const char *parent_name = clks->parent_name;
> +	int ret;
> +
> +	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
> +	if (!socfpga_clk)
> +		return NULL;

Won't happen.

> diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h

We have dts/include/dt-bindings/clock/intel,agilex5-clkmgr.h derived
from upstream dts import. Please switch to this one instead.

Sascha

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